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76f6a3d4c3
Move Xilinx specific code into shared folder so it can be re-used by different examples. Use the shared RAM code and make use of byte enable signal. Fixes lowrisc/ibex#144
18 lines
493 B
Text
18 lines
493 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:fpga_xilinx_shared"
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description: "Collection of useful RTL for Xilinx based examples"
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filesets:
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files_sv:
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files:
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- rtl/fpga/xilinx/prim_clock_gating.sv
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- rtl/fpga/xilinx/clkgen_xil7series.sv
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- rtl/ram_1p.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_sv
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