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prim_assert.sv is a file containing assertion macros (defines). Previously, prim_assert.sv was compiled as normal SystemVerilog file. This made the defines available for the whole compilation unit as soon as they were defined. Since all cores using prim_assert depended (in fusesoc) on the lowrisc:prim:assert core, prim_assert was always compiled first, and the defines were visible in subsequent files. All of that is only true if all files end up in one comilation unit. The SV standard states that what makes up a compilation unit is tool-defined, but also states that typically, passing multiple files (or a file list/.f file) to a single tool invocation means that all files end up in one compilation unit; if the tool is called multiple times, then the files end up in separate compilation units. Edalize (the fusesoc backend) doesn't guarantee either behavior, and so it happens that for Vivado, Verilator, Cadence and Synopsys simulators, all files are compiled into a single compilation unit. But for Riviera, each file is a separate compilation unit. To avoid relying on the definition of compilation units, and to do the generally right thing (TM), this commit changes the code to always include the prim_assert.sv file when it is used in a source file. Include guards are introduced in the prim_assert.sv file to avoid defining things twice.
17 lines
400 B
Text
17 lines
400 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:prim:assert:0.1"
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description: "Assertion primitives"
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filesets:
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files_rtl:
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files:
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- rtl/prim_assert.sv : {is_include_file : true}
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_rtl
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