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9858198ee5
correctly in the EX stage without impacting the WB stage Also align simchecker and tracer to this
819 lines
32 KiB
Systemverilog
819 lines
32 KiB
Systemverilog
// Copyright 2015 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Matthias Baer - baermatt@student.ethz.ch //
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// //
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// Additional contributions by: //
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// Igor Loi - igor.loi@unibo.it //
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// Andreas Traber - atraber@student.ethz.ch //
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// Sven Stucki - svstucki@student.ethz.ch //
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// //
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// Design Name: Top level module //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Top level module of the RISC-V core. //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "riscv_defines.sv"
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module riscv_core
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#(
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parameter N_EXT_PERF_COUNTERS = 0,
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parameter INSTR_RDATA_WIDTH = 32
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)
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(
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// Clock and Reset
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input logic clk,
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input logic rst_n,
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input logic test_en_i, // enable all clock gates for testing
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// Core ID, Cluster ID and boot address are considered more or less static
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input logic [31:0] boot_addr_i,
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input logic [4:0] core_id_i,
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input logic [4:0] cluster_id_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Interrupt inputs
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input logic [31:0] irq_i, // level sensitive IR lines
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// Debug Interface
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input logic dbginf_stall_i,
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output logic dbginf_bp_o,
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input logic dbginf_strobe_i,
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output logic dbginf_ack_o,
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input logic dbginf_we_i,
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input logic [15:0] dbginf_addr_i,
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input logic [31:0] dbginf_data_i,
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output logic [31:0] dbginf_data_o,
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// CPU Control Signals
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input logic fetch_enable_i,
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output logic core_busy_o,
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input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_counters_i
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);
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localparam N_HWLP = 2;
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localparam N_HWLP_BITS = $clog2(N_HWLP);
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// IF/ID signals
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logic is_hwlp_id;
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logic [N_HWLP-1:0] hwlp_dec_cnt_id;
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logic instr_valid_id;
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logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage
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logic is_compressed_id;
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logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
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logic [31:0] current_pc_if; // Current Program counter
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logic [31:0] current_pc_id; // Current Program counter
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logic clear_instr_valid;
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logic pc_set;
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logic [2:0] pc_mux_id; // Mux selector for next PC
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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logic [4:0] exc_vec_pc_mux_id; // Mux selector for vectorized IR lines
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logic lsu_load_err;
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logic lsu_store_err;
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// ID performance counter signals
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logic is_decoding;
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logic useincr_addr_ex; // Active when post increment
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logic data_misaligned;
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// Jump and branch target and decision (EX->IF)
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logic [31:0] jump_target_id, jump_target_ex;
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logic branch_in_ex;
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logic branch_decision;
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logic core_busy;
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logic if_busy;
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logic [31:0] branch_pc_ex; // PC of last executed branch
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// ALU Control
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logic [`ALU_OP_WIDTH-1:0] alu_operator_ex;
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logic [31:0] alu_operand_a_ex;
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logic [31:0] alu_operand_b_ex;
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logic [31:0] alu_operand_c_ex;
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logic vector_mode_ex;
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// Multiplier Control
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logic mult_en_ex;
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logic [1:0] mult_sel_subword_ex;
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logic [1:0] mult_signed_mode_ex;
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logic mult_mac_en_ex;
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logic [31:0] mult_operand_a_ex;
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logic [31:0] mult_operand_b_ex;
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logic [31:0] mult_operand_c_ex;
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// Register Write Control
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logic [4:0] regfile_waddr_ex;
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logic regfile_we_ex;
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logic [4:0] regfile_waddr_fw_wb_o; // From WB to ID
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logic regfile_we_wb;
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logic [31:0] regfile_wdata;
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logic [4:0] regfile_alu_waddr_ex;
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logic regfile_alu_we_ex;
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logic [4:0] regfile_alu_waddr_fw;
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logic regfile_alu_we_fw;
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logic [31:0] regfile_alu_wdata_fw;
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// CSR control
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logic csr_access_ex;
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logic [1:0] csr_op_ex;
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logic csr_access;
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logic [1:0] csr_op;
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logic [11:0] csr_addr;
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logic [11:0] csr_addr_int;
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logic [31:0] csr_rdata;
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logic [31:0] csr_wdata;
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// Data Memory Control: From ID stage (id-ex pipe) <--> load store unit
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logic data_we_ex;
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logic [1:0] data_type_ex;
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logic data_sign_ext_ex;
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logic [1:0] data_reg_offset_ex;
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logic data_req_ex;
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logic data_misaligned_ex;
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// stall control
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logic halt_if;
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logic if_ready;
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logic id_ready;
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logic ex_ready;
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logic if_valid;
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logic id_valid;
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logic ex_valid;
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logic wb_valid;
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logic lsu_ready_ex;
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logic lsu_ready_wb;
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// Signals between instruction core interface and pipe (if and id stages)
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logic instr_req_int; // Id stage asserts a req to instruction core interface
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// Interrupts
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logic irq_enable;
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logic [31:0] mepc;
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logic [5:0] exc_cause;
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logic save_exc_cause;
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logic exc_save_id;
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logic exc_restore_id;
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// Hardware loop controller signals
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logic [N_HWLP-1:0] [31:0] hwlp_start;
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logic [N_HWLP-1:0] [31:0] hwlp_end;
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logic [N_HWLP-1:0] [31:0] hwlp_cnt;
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// used to write from CS registers to hardware loop registers
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logic [N_HWLP_BITS-1:0] csr_hwlp_regid;
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logic [2:0] csr_hwlp_we;
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logic [31:0] csr_hwlp_data;
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// Debug Unit
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logic dbg_stall;
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logic dbg_stop_req;
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logic dbg_trap;
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logic dbg_step_en; // single-step trace mode enabled
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logic [1:0] dbg_dsr; // Debug Stop Register
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logic dbg_reg_mux;
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logic dbg_sp_mux;
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logic dbg_reg_we;
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logic [11:0] dbg_reg_addr;
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logic [31:0] dbg_reg_wdata;
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logic [31:0] dbg_reg_rdata;
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logic [31:0] dbg_rdata;
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logic [31:0] dbg_npc;
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logic dbg_set_npc;
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// Performance Counters
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logic perf_imiss;
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logic perf_jump;
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logic perf_jr_stall;
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logic perf_ld_stall;
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assign core_busy_o = if_busy || core_busy;
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//////////////////////////////////////////////////
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// ___ _____ ____ _____ _ ____ _____ //
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// |_ _| ___| / ___|_ _|/ \ / ___| ____| //
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// | || |_ \___ \ | | / _ \| | _| _| //
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// | || _| ___) || |/ ___ \ |_| | |___ //
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// |___|_| |____/ |_/_/ \_\____|_____| //
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// //
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//////////////////////////////////////////////////
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riscv_if_stage
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#(
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.N_HWLP ( N_HWLP ),
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.RDATA_WIDTH ( INSTR_RDATA_WIDTH )
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)
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if_stage_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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// boot address (trap vector location)
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.boot_addr_i ( boot_addr_i ),
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// instruction request control
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.req_i ( instr_req_int ),
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// instruction cache interface
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.instr_req_o ( instr_req_o ),
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.instr_addr_o ( instr_addr_o ),
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.instr_gnt_i ( instr_gnt_i ),
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.instr_rvalid_i ( instr_rvalid_i ),
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.instr_rdata_i ( instr_rdata_i ),
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// outputs to ID stage
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.hwlp_dec_cnt_id_o ( hwlp_dec_cnt_id ),
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.is_hwlp_id_o ( is_hwlp_id ),
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.instr_valid_id_o ( instr_valid_id ),
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.instr_rdata_id_o ( instr_rdata_id ),
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.is_compressed_id_o ( is_compressed_id ),
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.illegal_c_insn_id_o ( illegal_c_insn_id ),
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.current_pc_if_o ( current_pc_if ),
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.current_pc_id_o ( current_pc_id ),
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// control signals
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.clear_instr_valid_i ( clear_instr_valid ),
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( mepc ), // exception return address
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.pc_mux_i ( pc_mux_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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// from hwloop registers
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.hwlp_start_i ( hwlp_start ),
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.hwlp_end_i ( hwlp_end ),
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.hwlp_cnt_i ( hwlp_cnt ),
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// from debug unit
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.dbg_npc_i ( dbg_npc ),
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.dbg_set_npc_i ( dbg_set_npc ),
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// Jump targets
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.jump_target_id_i ( jump_target_id ),
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.jump_target_ex_i ( jump_target_ex ),
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// pipeline stalls
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.halt_if_i ( halt_if ),
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.if_ready_o ( if_ready ),
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.id_ready_i ( id_ready ),
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.if_valid_o ( if_valid ),
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.if_busy_o ( if_busy ),
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.perf_imiss_o ( perf_imiss )
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);
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/////////////////////////////////////////////////
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// ___ ____ ____ _____ _ ____ _____ //
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// |_ _| _ \ / ___|_ _|/ \ / ___| ____| //
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// | || | | | \___ \ | | / _ \| | _| _| //
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// | || |_| | ___) || |/ ___ \ |_| | |___ //
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// |___|____/ |____/ |_/_/ \_\____|_____| //
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// //
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/////////////////////////////////////////////////
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riscv_id_stage
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#(
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.N_HWLP ( N_HWLP )
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)
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id_stage_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.test_en_i ( test_en_i ),
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// Processor Enable
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.fetch_enable_i ( fetch_enable_i ),
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.core_busy_o ( core_busy ),
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.is_decoding_o ( is_decoding ),
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// Interface to instruction memory
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.hwlp_dec_cnt_i ( hwlp_dec_cnt_id ),
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.is_hwlp_i ( is_hwlp_id ),
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.instr_valid_i ( instr_valid_id ),
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.instr_rdata_i ( instr_rdata_id ),
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.instr_req_o ( instr_req_int ),
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// Jumps and branches
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.branch_in_ex_o ( branch_in_ex ),
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.branch_decision_i ( branch_decision ),
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.jump_target_o ( jump_target_id ),
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// IF and ID control signals
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.clear_instr_valid_o ( clear_instr_valid ),
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.pc_set_o ( pc_set ),
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.pc_mux_o ( pc_mux_id ),
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.exc_vec_pc_mux_o ( exc_vec_pc_mux_id ),
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.illegal_c_insn_i ( illegal_c_insn_id ),
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.is_compressed_i ( is_compressed_id ),
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.current_pc_if_i ( current_pc_if ),
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.current_pc_id_i ( current_pc_id ),
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// Stalls
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.halt_if_o ( halt_if ),
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.if_ready_i ( if_ready ),
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.id_ready_o ( id_ready ),
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.ex_ready_i ( ex_ready ),
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.if_valid_i ( if_valid ),
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.id_valid_o ( id_valid ),
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.ex_valid_i ( ex_valid ),
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.wb_valid_i ( wb_valid ),
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// From the Pipeline ID/EX
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.branch_pc_ex_o ( branch_pc_ex ),
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.alu_operand_a_ex_o ( alu_operand_a_ex ),
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.alu_operand_b_ex_o ( alu_operand_b_ex ),
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.alu_operand_c_ex_o ( alu_operand_c_ex ),
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.regfile_waddr_ex_o ( regfile_waddr_ex ),
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.regfile_we_ex_o ( regfile_we_ex ),
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.regfile_alu_we_ex_o ( regfile_alu_we_ex ),
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.regfile_alu_waddr_ex_o ( regfile_alu_waddr_ex ),
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// ALU
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.alu_operator_ex_o ( alu_operator_ex ),
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// MUL
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.mult_en_ex_o ( mult_en_ex ), // from ID to EX stage
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.mult_sel_subword_ex_o ( mult_sel_subword_ex ), // from ID to EX stage
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.mult_signed_mode_ex_o ( mult_signed_mode_ex ), // from ID to EX stage
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.mult_mac_en_ex_o ( mult_mac_en_ex ), // from ID to EX stage
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.mult_operand_a_ex_o ( mult_operand_a_ex ),
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.mult_operand_b_ex_o ( mult_operand_b_ex ),
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.mult_operand_c_ex_o ( mult_operand_c_ex ),
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.vector_mode_ex_o ( vector_mode_ex ), // from ID to EX stage
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// CSR ID/EX
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.csr_access_ex_o ( csr_access_ex ),
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.csr_op_ex_o ( csr_op_ex ),
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// hardware loop signals to IF hwlp controller
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.hwlp_start_o ( hwlp_start ),
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.hwlp_end_o ( hwlp_end ),
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.hwlp_cnt_o ( hwlp_cnt ),
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// hardware loop signals from CSR
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.csr_hwlp_regid_i ( csr_hwlp_regid ),
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.csr_hwlp_we_i ( csr_hwlp_we ),
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.csr_hwlp_data_i ( csr_hwlp_data ),
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// LSU
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.data_req_ex_o ( data_req_ex ), // to load store unit
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.data_we_ex_o ( data_we_ex ), // to load store unit
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.data_type_ex_o ( data_type_ex ), // to load store unit
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.data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
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.data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit
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.data_misaligned_ex_o ( data_misaligned_ex ), // to load store unit
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.prepost_useincr_ex_o ( useincr_addr_ex ),
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.data_misaligned_i ( data_misaligned ),
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// Interrupt Signals
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.irq_i ( irq_i ), // incoming interrupts
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.irq_enable_i ( irq_enable ), // global interrupt enable
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.exc_cause_o ( exc_cause ),
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.save_exc_cause_o ( save_exc_cause ),
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.exc_save_id_o ( exc_save_id ), // control signal to save pc
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.exc_restore_id_o ( exc_restore_id ), // control signal to restore pc
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.lsu_load_err_i ( lsu_load_err ),
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.lsu_store_err_i ( lsu_store_err ),
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// Debug Unit Signals
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.dbg_stop_req_i ( dbg_stop_req ),
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.dbg_step_en_i ( dbg_step_en ),
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.dbg_dsr_i ( dbg_dsr ),
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.dbg_stall_i ( dbg_stall ),
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.dbg_trap_o ( dbg_trap ),
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.dbg_reg_mux_i ( dbg_reg_mux ),
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.dbg_reg_we_i ( dbg_reg_we ),
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.dbg_reg_addr_i ( dbg_reg_addr[4:0] ),
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.dbg_reg_wdata_i ( dbg_reg_wdata ),
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.dbg_reg_rdata_o ( dbg_reg_rdata ),
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.dbg_set_npc_i ( dbg_set_npc ),
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// Forward Signals
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.regfile_waddr_wb_i ( regfile_waddr_fw_wb_o), // Write address ex-wb pipeline
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.regfile_we_wb_i ( regfile_we_wb ), // write enable for the register file
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.regfile_wdata_wb_i ( regfile_wdata ), // write data to commit in the register file
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.regfile_alu_waddr_fw_i ( regfile_alu_waddr_fw ),
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.regfile_alu_we_fw_i ( regfile_alu_we_fw ),
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.regfile_alu_wdata_fw_i ( regfile_alu_wdata_fw ),
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// Performance Counters
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.perf_jump_o ( perf_jump ),
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.perf_jr_stall_o ( perf_jr_stall ),
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.perf_ld_stall_o ( perf_ld_stall )
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);
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/////////////////////////////////////////////////////
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// _______ __ ____ _____ _ ____ _____ //
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// | ____\ \/ / / ___|_ _|/ \ / ___| ____| //
|
|
// | _| \ / \___ \ | | / _ \| | _| _| //
|
|
// | |___ / \ ___) || |/ ___ \ |_| | |___ //
|
|
// |_____/_/\_\ |____/ |_/_/ \_\____|_____| //
|
|
// //
|
|
/////////////////////////////////////////////////////
|
|
riscv_ex_stage ex_stage_i
|
|
(
|
|
// Global signals: Clock and active low asynchronous reset
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
// Alu signals from ID stage
|
|
.alu_operator_i ( alu_operator_ex ), // from ID/EX pipe registers
|
|
.alu_operand_a_i ( alu_operand_a_ex ), // from ID/EX pipe registers
|
|
.alu_operand_b_i ( alu_operand_b_ex ), // from ID/EX pipe registers
|
|
.alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers
|
|
|
|
.vector_mode_i ( vector_mode_ex ), // from ID/EX pipe registers
|
|
|
|
// Multipler
|
|
.mult_en_i ( mult_en_ex ),
|
|
.mult_sel_subword_i ( mult_sel_subword_ex ),
|
|
.mult_signed_mode_i ( mult_signed_mode_ex ),
|
|
.mult_mac_en_i ( mult_mac_en_ex ),
|
|
.mult_operand_a_i ( mult_operand_a_ex ), // from ID/EX pipe registers
|
|
.mult_operand_b_i ( mult_operand_b_ex ), // from ID/EX pipe registers
|
|
.mult_operand_c_i ( mult_operand_c_ex ), // from ID/EX pipe registers
|
|
|
|
// interface with CSRs
|
|
.csr_access_i ( csr_access_ex ),
|
|
.csr_rdata_i ( csr_rdata ),
|
|
|
|
// From ID Stage: Regfile control signals
|
|
.branch_in_ex_i ( branch_in_ex ),
|
|
.regfile_alu_waddr_i ( regfile_alu_waddr_ex ),
|
|
.regfile_alu_we_i ( regfile_alu_we_ex ),
|
|
|
|
.regfile_waddr_i ( regfile_waddr_ex ),
|
|
.regfile_we_i ( regfile_we_ex ),
|
|
|
|
// Output of ex stage pipeline
|
|
.regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ),
|
|
.regfile_we_wb_o ( regfile_we_wb ),
|
|
|
|
// To IF: Jump and branch target and decision
|
|
.jump_target_o ( jump_target_ex ),
|
|
.branch_decision_o ( branch_decision ),
|
|
|
|
// To ID stage: Forwarding signals
|
|
.regfile_alu_waddr_fw_o ( regfile_alu_waddr_fw ),
|
|
.regfile_alu_we_fw_o ( regfile_alu_we_fw ),
|
|
.regfile_alu_wdata_fw_o ( regfile_alu_wdata_fw ),
|
|
|
|
// stall control
|
|
.lsu_ready_ex_i ( lsu_ready_ex ),
|
|
|
|
.ex_ready_o ( ex_ready ),
|
|
.ex_valid_o ( ex_valid ),
|
|
.wb_ready_i ( lsu_ready_wb )
|
|
);
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
// _ ___ _ ____ ____ _____ ___ ____ _____ _ _ _ _ ___ _____ //
|
|
// | | / _ \ / \ | _ \ / ___|_ _/ _ \| _ \| ____| | | | | \ | |_ _|_ _| //
|
|
// | | | | | |/ _ \ | | | | \___ \ | || | | | |_) | _| | | | | \| || | | | //
|
|
// | |__| |_| / ___ \| |_| | ___) || || |_| | _ <| |___ | |_| | |\ || | | | //
|
|
// |_____\___/_/ \_\____/ |____/ |_| \___/|_| \_\_____| \___/|_| \_|___| |_| //
|
|
// //
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
riscv_load_store_unit load_store_unit_i
|
|
(
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
//output to data memory
|
|
.data_req_o ( data_req_o ),
|
|
.data_gnt_i ( data_gnt_i ),
|
|
.data_rvalid_i ( data_rvalid_i ),
|
|
.data_err_i ( data_err_i ),
|
|
|
|
.data_addr_o ( data_addr_o ),
|
|
.data_we_o ( data_we_o ),
|
|
.data_be_o ( data_be_o ),
|
|
.data_wdata_o ( data_wdata_o ),
|
|
.data_rdata_i ( data_rdata_i ),
|
|
|
|
// signal from ex stage
|
|
.data_we_ex_i ( data_we_ex ),
|
|
.data_type_ex_i ( data_type_ex ),
|
|
.data_wdata_ex_i ( alu_operand_c_ex ),
|
|
.data_reg_offset_ex_i ( data_reg_offset_ex ),
|
|
.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
|
|
|
|
.data_rdata_ex_o ( regfile_wdata ),
|
|
.data_req_ex_i ( data_req_ex ),
|
|
.operand_a_ex_i ( alu_operand_a_ex ),
|
|
.operand_b_ex_i ( alu_operand_b_ex ),
|
|
.addr_useincr_ex_i ( useincr_addr_ex ),
|
|
|
|
.data_misaligned_ex_i ( data_misaligned_ex ), // from ID/EX pipeline
|
|
.data_misaligned_o ( data_misaligned ),
|
|
|
|
// exception signals
|
|
.load_err_o ( lsu_load_err ),
|
|
.store_err_o ( lsu_store_err ),
|
|
|
|
// control signals
|
|
.lsu_ready_ex_o ( lsu_ready_ex ),
|
|
.lsu_ready_wb_o ( lsu_ready_wb ),
|
|
|
|
.ex_valid_i ( ex_valid )
|
|
);
|
|
|
|
assign wb_valid = lsu_ready_wb;
|
|
|
|
|
|
//////////////////////////////////////
|
|
// ____ ____ ____ //
|
|
// / ___/ ___|| _ \ ___ //
|
|
// | | \___ \| |_) / __| //
|
|
// | |___ ___) | _ <\__ \ //
|
|
// \____|____/|_| \_\___/ //
|
|
// //
|
|
// Control and Status Registers //
|
|
//////////////////////////////////////
|
|
|
|
riscv_cs_registers
|
|
#(
|
|
.N_EXT_CNT ( N_EXT_PERF_COUNTERS )
|
|
)
|
|
cs_registers_i
|
|
(
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
// Core and Cluster ID from outside
|
|
.core_id_i ( core_id_i ),
|
|
.cluster_id_i ( cluster_id_i ),
|
|
|
|
// Interface to CSRs (SRAM like)
|
|
.csr_access_i ( csr_access_ex ),
|
|
.csr_addr_i ( csr_addr ),
|
|
.csr_wdata_i ( csr_wdata ),
|
|
.csr_op_i ( csr_op ),
|
|
.csr_rdata_o ( csr_rdata ),
|
|
|
|
// Interrupt related control signals
|
|
.irq_enable_o ( irq_enable ),
|
|
.mepc_o ( mepc ),
|
|
|
|
.curr_pc_id_i ( current_pc_id ), // from IF stage
|
|
.exc_save_i ( exc_save_id ),
|
|
.exc_restore_i ( exc_restore_id ),
|
|
|
|
.exc_cause_i ( exc_cause ),
|
|
.save_exc_cause_i ( save_exc_cause ),
|
|
|
|
// from hwloop registers
|
|
.hwlp_start_i ( hwlp_start ),
|
|
.hwlp_end_i ( hwlp_end ),
|
|
.hwlp_cnt_i ( hwlp_cnt ),
|
|
|
|
.hwlp_regid_o ( csr_hwlp_regid ),
|
|
.hwlp_we_o ( csr_hwlp_we ),
|
|
.hwlp_data_o ( csr_hwlp_data ),
|
|
|
|
// performance counter related signals
|
|
.id_valid_i ( id_valid ),
|
|
.is_compressed_i ( is_compressed_id ),
|
|
.is_decoding_i ( is_decoding ),
|
|
|
|
.imiss_i ( perf_imiss ),
|
|
.pc_set_i ( pc_set ),
|
|
.jump_i ( perf_jump ),
|
|
.branch_i ( branch_in_ex ),
|
|
.branch_taken_i ( branch_decision ),
|
|
.ld_stall_i ( perf_ld_stall ),
|
|
.jr_stall_i ( perf_jr_stall ),
|
|
|
|
.mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ),
|
|
.mem_store_i ( data_req_o & data_gnt_i & data_we_o ),
|
|
|
|
.ext_counters_i ( ext_perf_counters_i )
|
|
);
|
|
|
|
// Mux for CSR access through Debug Unit
|
|
assign csr_access = (dbg_sp_mux == 1'b0) ? csr_access_ex : 1'b1;
|
|
assign csr_addr = (dbg_sp_mux == 1'b0) ? csr_addr_int : dbg_reg_addr;
|
|
assign csr_wdata = (dbg_sp_mux == 1'b0) ? alu_operand_a_ex : dbg_reg_wdata;
|
|
assign csr_op = (dbg_sp_mux == 1'b0) ? csr_op_ex
|
|
: (dbg_reg_we == 1'b1 ? `CSR_OP_WRITE
|
|
: `CSR_OP_NONE );
|
|
assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata;
|
|
|
|
assign csr_addr_int = csr_access_ex ? alu_operand_b_ex[11:0] : '0;
|
|
|
|
|
|
/////////////////////////////////////////////////////////////
|
|
// ____ _____ ____ _ _ ____ _ _ _ _ ___ _____ //
|
|
// | _ \| ____| __ )| | | |/ ___| | | | | \ | |_ _|_ _| //
|
|
// | | | | _| | _ \| | | | | _ | | | | \| || | | | //
|
|
// | |_| | |___| |_) | |_| | |_| | | |_| | |\ || | | | //
|
|
// |____/|_____|____/ \___/ \____| \___/|_| \_|___| |_| //
|
|
// //
|
|
/////////////////////////////////////////////////////////////
|
|
|
|
riscv_debug_unit debug_unit_i
|
|
(
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
// Debug Interface
|
|
.dbginf_stall_i ( dbginf_stall_i ),
|
|
.dbginf_bp_o ( dbginf_bp_o ),
|
|
.dbginf_strobe_i ( dbginf_strobe_i ),
|
|
.dbginf_ack_o ( dbginf_ack_o ),
|
|
.dbginf_we_i ( dbginf_we_i ),
|
|
.dbginf_addr_i ( dbginf_addr_i ),
|
|
.dbginf_data_i ( dbginf_data_i ),
|
|
.dbginf_data_o ( dbginf_data_o ),
|
|
|
|
// To/From Core
|
|
.dbg_step_en_o ( dbg_step_en ),
|
|
.dbg_dsr_o ( dbg_dsr ),
|
|
|
|
.stall_core_o ( dbg_stall ),
|
|
.stop_req_o ( dbg_stop_req ),
|
|
.trap_i ( dbg_trap ),
|
|
|
|
// register file access
|
|
.sp_mux_o ( dbg_sp_mux ),
|
|
.regfile_mux_o ( dbg_reg_mux ),
|
|
.regfile_we_o ( dbg_reg_we ),
|
|
.regfile_addr_o ( dbg_reg_addr ),
|
|
.regfile_wdata_o ( dbg_reg_wdata ),
|
|
.regfile_rdata_i ( dbg_rdata ),
|
|
|
|
// signals for PPC and NPC
|
|
.curr_pc_if_i ( current_pc_if ), // from IF stage
|
|
.curr_pc_id_i ( current_pc_id ), // from IF stage
|
|
.branch_pc_i ( branch_pc_ex ), // PC of last executed branch (in EX stage)
|
|
|
|
.branch_in_ex_i ( branch_in_ex ),
|
|
.branch_taken_i ( branch_decision ),
|
|
|
|
.npc_o ( dbg_npc ), // PC from debug unit
|
|
.set_npc_o ( dbg_set_npc ) // set PC to new value
|
|
);
|
|
|
|
|
|
`ifdef TRACE_EXECUTION
|
|
riscv_tracer riscv_tracer_i
|
|
(
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
.fetch_enable ( fetch_enable_i ),
|
|
.core_id ( core_id_i ),
|
|
.cluster_id ( cluster_id_i ),
|
|
|
|
.pc ( id_stage_i.current_pc_id_i ),
|
|
.instr ( id_stage_i.instr ),
|
|
.compressed ( id_stage_i.is_compressed_i ),
|
|
.id_valid ( id_stage_i.id_valid_o ),
|
|
.is_decoding ( id_stage_i.is_decoding_o ),
|
|
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
|
|
|
.rs1_value ( id_stage_i.operand_a_fw_id ),
|
|
.rs2_value ( id_stage_i.operand_b_fw_id ),
|
|
.rs3_value ( id_stage_i.alu_operand_c ),
|
|
|
|
.ex_valid ( ex_valid ),
|
|
.ex_reg_addr ( regfile_alu_waddr_fw ),
|
|
.ex_reg_we ( regfile_alu_we_fw ),
|
|
.ex_reg_wdata ( regfile_alu_wdata_fw ),
|
|
|
|
.ex_data_addr ( data_addr_o ),
|
|
.ex_data_req ( data_req_o ),
|
|
.ex_data_gnt ( data_gnt_i ),
|
|
.ex_data_we ( data_we_o ),
|
|
.ex_data_wdata ( data_wdata_o ),
|
|
|
|
.wb_bypass ( ex_stage_i.branch_in_ex_i ),
|
|
|
|
.wb_valid ( wb_valid ),
|
|
.wb_reg_addr ( regfile_waddr_fw_wb_o ),
|
|
.wb_reg_we ( regfile_we_wb ),
|
|
.wb_reg_wdata ( regfile_wdata ),
|
|
|
|
.imm_u_type ( id_stage_i.imm_u_type ),
|
|
.imm_uj_type ( id_stage_i.imm_uj_type ),
|
|
.imm_i_type ( id_stage_i.imm_i_type ),
|
|
.imm_iz_type ( id_stage_i.imm_iz_type[11:0] ),
|
|
.imm_z_type ( id_stage_i.imm_z_type ),
|
|
.imm_s_type ( id_stage_i.imm_s_type ),
|
|
.imm_sb_type ( id_stage_i.imm_sb_type )
|
|
);
|
|
`endif
|
|
|
|
`ifdef SIMCHECKER
|
|
logic is_interrupt;
|
|
assign is_interrupt = (pc_mux_id == `PC_EXCEPTION) && (exc_pc_mux_id == `EXC_PC_IRQ);
|
|
|
|
riscv_simchecker riscv_simchecker_i
|
|
(
|
|
.clk ( clk ),
|
|
.rst_n ( rst_n ),
|
|
|
|
.fetch_enable ( fetch_enable_i ),
|
|
.boot_addr ( boot_addr_i ),
|
|
.core_id ( core_id_i ),
|
|
.cluster_id ( cluster_id_i ),
|
|
|
|
.instr_compressed ( if_stage_i.fetch_rdata[15:0] ),
|
|
.pc_set ( pc_set ),
|
|
.if_valid ( if_valid ),
|
|
|
|
.pc ( id_stage_i.current_pc_id_i ),
|
|
.instr ( id_stage_i.instr ),
|
|
.is_compressed ( is_compressed_id ),
|
|
.id_valid ( id_stage_i.id_valid_o ),
|
|
.is_decoding ( id_stage_i.is_decoding_o ),
|
|
.is_illegal ( id_stage_i.illegal_insn_dec ),
|
|
.is_interrupt ( is_interrupt ),
|
|
.irq_no ( exc_vec_pc_mux_id ),
|
|
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
|
|
|
.ex_valid ( ex_valid ),
|
|
.ex_reg_addr ( id_stage_i.registers_i.waddr_b_i ),
|
|
.ex_reg_we ( id_stage_i.registers_i.we_b_i ),
|
|
.ex_reg_wdata ( id_stage_i.registers_i.wdata_b_i ),
|
|
|
|
.ex_data_addr ( data_addr_o ),
|
|
.ex_data_req ( data_req_o ),
|
|
.ex_data_gnt ( data_gnt_i ),
|
|
.ex_data_we ( data_we_o ),
|
|
.ex_data_wdata ( data_wdata_o ),
|
|
|
|
.wb_bypass ( ex_stage_i.branch_in_ex_i ),
|
|
.lsu_misaligned ( data_misaligned ),
|
|
|
|
.wb_valid ( wb_valid ),
|
|
.wb_reg_addr ( id_stage_i.registers_i.waddr_a_i ),
|
|
.wb_reg_we ( id_stage_i.registers_i.we_a_i ),
|
|
.wb_reg_wdata ( id_stage_i.registers_i.wdata_a_i ),
|
|
|
|
.wb_data_rvalid ( data_rvalid_i ),
|
|
.wb_data_rdata ( data_rdata_i )
|
|
);
|
|
`endif
|
|
|
|
endmodule
|