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088cd11593
- Add the minimum amount of trigger system to support GDB hbreak - Only a single trigger is implemented - Only instruction address matching - Only break into debug mode (no native debug) - Fixes #382 Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
39 lines
1.9 KiB
ReStructuredText
39 lines
1.9 KiB
ReStructuredText
.. _debug-support:
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Debug Support
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=============
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Ibex offers support for execution-based debug according to the RISC-V Debug Specification, version 0.13.
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Interface
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---------
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+-----------------+-----------+-----------------------------+
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| Signal | Direction | Description |
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+=================+===========+=============================+
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| ``debug_req_i`` | input | Request to enter Debug Mode |
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+-----------------+-----------+-----------------------------+
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``debug_req_i`` is the "debug interrupt", issued by the debug module when the core should enter Debug Mode.
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Parameters
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----------
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+---------------------+-----------------------------------------------------------------+
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| Parameter | Description |
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+=====================+=================================================================+
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| ``DmHaltAddr`` | Address to jump to when entering Debug Mode |
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+---------------------+-----------------------------------------------------------------+
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| ``DmExceptionAddr`` | Address to jump to when an exception occurs while in Debug Mode |
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+---------------------+-----------------------------------------------------------------+
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| ``DbgTriggerEn`` | Enable support for debug triggers |
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+---------------------+-----------------------------------------------------------------+
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Core Debug Registers
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--------------------
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Ibex implements four core debug registers, namely :ref:`csr-dcsr`, :ref:`csr-dpc`, and two debug scratch registers.
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If the ``DbgTriggerEn`` parameter is set, debug trigger registers are available.
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See :ref:`csr-tselect`, :ref:`csr-tdata1` and :ref:`csr-tdata2` for details.
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All those registers are accessible from Debug Mode only.
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If software tries to access them without the core being in Debug Mode, an illegal instruction exception is triggered.
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