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The third pipeline stage is a new writeback stage. Ibex can now be configured as the original two stage design or the new three stage design using the `WritebackStage` parameter in ibex_core. This defaults to 0 (giving the original two stage design). The three stage design is *EXPERIMENTAL* In the three stage design all register write back occurs in the third, final stage. This allows a cycle for responses to loads and stores so when the memory system can respond in a single cycle there will be no stall. This offers significant performance benefits. Documentation of the three stage design is still to be written so existing documentation applies to the two stage design only as various aspects of Ibex behaviour will change in the three stage design. Signed-off-by: Greg Chadwick <gac@lowrisc.org>
106 lines
2.6 KiB
Text
106 lines
2.6 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core:0.1"
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description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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files:
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- rtl/ibex_pkg.sv
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- rtl/ibex_alu.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_counters.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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- rtl/ibex_pmp.sv
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- rtl/ibex_wb_stage.sv
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# XXX: Figure out the best way to switch these two implementations
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# dynamically on the target.
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# - rtl/ibex_register_file_latch.sv # ASIC
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# - rtl/ibex_register_file_fpga.sv # FPGA
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- rtl/ibex_register_file_ff.sv # generic FF-based
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- rtl/ibex_core.sv
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file_type: systemVerilogSource
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files_lint:
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depend:
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- lowrisc:ibex:sim_shared
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_check_tool_requirements:
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depend:
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- lowrisc:ibex:check_tool_requirements
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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RV32E:
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datatype: bool
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paramtype: vlogparam
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RV32M:
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datatype: bool
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paramtype: vlogparam
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MultiplierImplementation:
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datatype: str
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paramtype: vlogparam
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description: "Multiplier implementation. Valid values: fast, slow"
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default: fast
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BranchTargetALU:
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datatype: int
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paramtype: vlogparam
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default: 0
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description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
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WritebackStage:
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datatype: int
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paramtype: vlogparam
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default: 0
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description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
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targets:
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default:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_check_tool_requirements
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lint:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_lint
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- files_check_tool_requirements
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: verilator
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toplevel: ibex_core
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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