Rupert Swarbrick e0b477069e Update lowrisc_ip to lowRISC/opentitan@7117c349d ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7117c349d5465b5152d3bb774079013924a3e9ba * [dv/common] Improve coverage exclusion method (Cindy Chen) * [prim] Waive unused parameter warnings for an FPGA-specific param (Rupert Swarbrick) * [dpi] Fix indexing bug in ecc32_mem_area (Rupert Swarbrick) * [dv, xcelium] Dump covergroup report (Srikrishna Iyer) * [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer) * [otp_ctrl] Workaround for generated prim depending on generated prim (Michael Schaffner) * [dpi_memutil] Fix bug in RegisterMemoryArea (Rupert Swarbrick) * [rom_ctrl/dv] Add skeleton testbench (Tom Roberts) * [dvsim/verilator] Remove FUSESOC_IGNORE (Michael Schaffner) * [checklists] Update all checklists for consistency (Srikrishna Iyer) * [dv] Add integrity generation to backdoor memory loading (Greg Chadwick) * [prim_secded] Add C reference models for Hsiao encode (Greg Chadwick) * [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy Chen) * [dv/unr] Fix unr clk rst ports (Cindy Chen) * [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin) * [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>		2021-05-25 15:14:52 +01:00
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sv	Update lowrisc_ip to lowRISC/opentitan@ca950b43a	2021-05-11 18:28:56 +01:00
tools	Update lowrisc_ip to lowRISC/opentitan@7117c349d	2021-05-25 15:14:52 +01:00
verilator	Update lowrisc_ip to lowRISC/opentitan@7117c349d	2021-05-25 15:14:52 +01:00