Tom Roberts 42aa761c5d [rtl] Fix mtval for unaligned instr errors ... mtval should record which half of the instruction caused the error rather than just recording the PC. An extra signal is added in the IF stage to indicate when an error is caused by the second half of an unaligned instruction. This signal is then used to increment the PC by 2 for mtval capture on an error. Fixes #709		2020-03-18 12:53:35 +00:00
..
ibex_alu.sv	[rtl] Add multdiv_sel signal to decode	2020-01-31 09:32:20 +00:00
ibex_compressed_decoder.sv	[rtl] Introduce default clk/reset to prim_assert	2020-02-10 09:42:52 +00:00
ibex_controller.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_core.f	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
ibex_core.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_core_tracing.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_counters.sv	Use a syntax compatible with Verible	2020-03-13 10:34:12 +00:00
ibex_cs_registers.sv	[rtl/sw] Add multiply and divide wait counters	2020-03-13 14:48:29 +00:00
ibex_decoder.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_ex_block.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_fetch_fifo.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_icache.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_id_stage.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_if_stage.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_load_store_unit.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_multdiv_fast.sv	[rtl] Fixes for single-cycle mutiply	2020-03-11 11:53:54 +00:00
ibex_multdiv_slow.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_pkg.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00
ibex_pmp.sv	[RTL PMP] Fix address matching bugs	2019-10-03 10:41:29 +01:00
ibex_prefetch_buffer.sv	[rtl] Fix mtval for unaligned instr errors	2020-03-18 12:53:35 +00:00
ibex_register_file_ff.sv	Mention CREDITS.md in license header	2019-08-27 18:10:02 +01:00
ibex_register_file_fpga.sv	[rtl] Fix Typo in FPGA Register File	2020-01-20 17:01:30 +00:00
ibex_register_file_latch.sv	Register file: update comments	2019-08-29 15:24:18 +01:00
ibex_tracer.sv	Tracer: Mark all functions "automatic"	2020-02-21 10:31:05 +00:00
ibex_tracer_pkg.sv	Implement Verilator-compatible tracer, and use it	2019-10-02 18:28:26 +01:00
ibex_wb_stage.sv	[RTL] Add configurable third pipeline stage	2020-03-06 15:29:14 +00:00