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Instead of using copies of primitives from OpenTitan, vendor the files in directly from OpenTitan, and use them. Benefits: - Less potential for diverging code between OpenTitan and Ibex, causing problems when importing Ibex into OT. - Use of the abstract primitives instead of the generic ones. The abstract primitives are replaced during synthesis time with target-dependent implementations. For simulation, nothing changes. For synthesis for a given target technology (e.g. a specific ASIC or FPGA technology), the primitives system can be instructed to choose optimized versions (if available). This is most relevant for the icache, which hard-coded the generic SRAM primitive before. This primitive is always implemented as registers. By using the abstract primitive (prim_ram_1p) instead, the RAMs can be replaced with memory-compiler-generated ones if necessary. There are no real draw-backs, but a couple points to be aware of: - Our ram_1p and ram_2p implementations are kept as wrapper around the primitives, since their interface deviates slightly from the one in prim_ram*. This also includes a rather unfortunate naming confusion around rvalid, which means "read data valid" in the OpenTitan advanced RAM primitives (prim_ram_1p_adv for example), but means "ack" in PULP-derived IP and in our bus implementation. - The core_ibex UVM DV doesn't use FuseSoC to generate its file list, but uses a hard-coded list in `ibex_files.f` instead. Since the dynamic primitives system requires the use of FuseSoC we need to provide a stop-gap until this file is removed. Issue #893 tracks progress on that. - Dynamic primitives depend no a not-yet-merged feature of FuseSoC (https://github.com/olofk/fusesoc/pull/391). We depend on the same functionality in OpenTitan and have instructed users to use a patched branch of FuseSoC for a long time through `python-requirements.txt`, so no action is needed for users which are either successfully interacting with the OpenTitan source code, or have followed our instructions. All other users will see a reasonably descriptive error message during a FuseSoC run. - This commit is massive, but there are no good ways to split it into bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore all code in `vendor/lowrisc_ip`, it's an import from OpenTitan. - The check_tool_requirements tooling isn't easily vendor-able from OpenTitan at the moment. I've filed https://github.com/lowRISC/opentitan/issues/2309 to get that sorted. - The LFSR primitive doesn't have a own core file, forcing us to include the catch-all `lowrisc:prim:all` core. I've filed https://github.com/lowRISC/opentitan/issues/2310 to get that sorted.
173 lines
4.2 KiB
Text
173 lines
4.2 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core:0.1"
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description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr_Zifencei ISA"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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# TODO: Only lfsr is needed. Replace with a more specific dependency
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# once available.
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- lowrisc:prim:all
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- lowrisc:ibex:ibex_pkg
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- lowrisc:ibex:ibex_icache
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files:
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- rtl/ibex_alu.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_counters.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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- rtl/ibex_pmp.sv
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- rtl/ibex_wb_stage.sv
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- rtl/ibex_dummy_instr.sv
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# XXX: Figure out the best way to switch these two implementations
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# dynamically on the target.
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# - rtl/ibex_register_file_latch.sv # ASIC
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# - rtl/ibex_register_file_fpga.sv # FPGA
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- rtl/ibex_register_file_ff.sv # generic FF-based
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- rtl/ibex_core.sv
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file_type: systemVerilogSource
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files_lint:
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depend:
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- lowrisc:ibex:sim_shared
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_check_tool_requirements:
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depend:
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- lowrisc:tool:check_tool_requirements
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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RV32E:
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datatype: int
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default: 0
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paramtype: vlogparam
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RV32M:
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datatype: int
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default: 1
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paramtype: vlogparam
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RV32B:
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datatype: int
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default: 0
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paramtype: vlogparam
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MultiplierImplementation:
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datatype: str
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paramtype: vlogparam
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description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
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default: "fast"
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ICache:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable instruction cache"
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ICacheECC:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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BranchTargetALU:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
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WritebackStage:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
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SecureIbex:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
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PMPEnable:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable PMP"
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PMPGranularity:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
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PMPNumRegions:
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datatype: int
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default: 4
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paramtype: vlogparam
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description: "Number of PMP regions"
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targets:
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default:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_check_tool_requirements
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lint:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_lint
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- files_check_tool_requirements
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: verilator
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toplevel: ibex_core
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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veriblelint:
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ruleset: default
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rules:
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- "-parameter-name-style"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: ibex_core
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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