ibex/ibex_core.core
Philipp Wagner 8b42024cd5 Use vendored-in primitives from OpenTitan
Instead of using copies of primitives from OpenTitan, vendor the files
in directly from OpenTitan, and use them.

Benefits:

- Less potential for diverging code between OpenTitan and Ibex, causing
  problems when importing Ibex into OT.

- Use of the abstract primitives instead of the generic ones. The
  abstract primitives are replaced during synthesis time with
  target-dependent implementations. For simulation, nothing changes. For
  synthesis for a given target technology (e.g. a specific ASIC or FPGA
  technology), the primitives system can be instructed to choose
  optimized versions (if available).

  This is most relevant for the icache, which hard-coded the generic
  SRAM primitive before. This primitive is always implemented as
  registers. By using the abstract primitive (prim_ram_1p) instead, the
  RAMs can be replaced with memory-compiler-generated ones if necessary.

There are no real draw-backs, but a couple points to be aware of:

- Our ram_1p and ram_2p implementations are kept as wrapper around the
  primitives, since their interface deviates slightly from the one in
  prim_ram*. This also includes a rather unfortunate naming confusion
  around rvalid, which means "read data valid" in the OpenTitan advanced
  RAM primitives (prim_ram_1p_adv for example), but means "ack" in
  PULP-derived IP and in our bus implementation.

- The core_ibex UVM DV doesn't use FuseSoC to generate its file list,
  but uses a hard-coded list in `ibex_files.f` instead. Since the
  dynamic primitives system requires the use of FuseSoC we need to
  provide a stop-gap until this file is removed. Issue #893 tracks
  progress on that.

- Dynamic primitives depend no a not-yet-merged feature of FuseSoC
  (https://github.com/olofk/fusesoc/pull/391). We depend on the same
  functionality in OpenTitan and have instructed users to use a patched
  branch of FuseSoC for a long time through `python-requirements.txt`,
  so no action is needed for users which are either successfully
  interacting with the OpenTitan source code, or have followed our
  instructions. All other users will see a reasonably descriptive error
  message during a FuseSoC run.

- This commit is massive, but there are no good ways to split it into
  bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore
  all code in `vendor/lowrisc_ip`, it's an import from OpenTitan.

- The check_tool_requirements tooling isn't easily vendor-able from
  OpenTitan at the moment. I've filed
  https://github.com/lowRISC/opentitan/issues/2309 to get that sorted.

- The LFSR primitive doesn't have a own core file, forcing us to include
  the catch-all `lowrisc:prim:all` core. I've filed
  https://github.com/lowRISC/opentitan/issues/2310 to get that sorted.
2020-05-27 10:23:15 +01:00

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CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_core:0.1"
description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr_Zifencei ISA"
filesets:
files_rtl:
depend:
- lowrisc:prim:assert
# TODO: Only lfsr is needed. Replace with a more specific dependency
# once available.
- lowrisc:prim:all
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_icache
files:
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_cs_registers.sv
- rtl/ibex_counters.sv
- rtl/ibex_decoder.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_if_stage.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_pmp.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_dummy_instr.sv
# XXX: Figure out the best way to switch these two implementations
# dynamically on the target.
# - rtl/ibex_register_file_latch.sv # ASIC
# - rtl/ibex_register_file_fpga.sv # FPGA
- rtl/ibex_register_file_ff.sv # generic FF-based
- rtl/ibex_core.sv
file_type: systemVerilogSource
files_lint:
depend:
- lowrisc:ibex:sim_shared
files_lint_verilator:
files:
- lint/verilator_waiver.vlt: {file_type: vlt}
files_check_tool_requirements:
depend:
- lowrisc:tool:check_tool_requirements
parameters:
RVFI:
datatype: bool
paramtype: vlogdefine
SYNTHESIS:
datatype: bool
paramtype: vlogdefine
RV32E:
datatype: int
default: 0
paramtype: vlogparam
RV32M:
datatype: int
default: 1
paramtype: vlogparam
RV32B:
datatype: int
default: 0
paramtype: vlogparam
MultiplierImplementation:
datatype: str
paramtype: vlogparam
description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
default: "fast"
ICache:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable instruction cache"
ICacheECC:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
WritebackStage:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
SecureIbex:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
PMPEnable:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable PMP"
PMPGranularity:
datatype: int
default: 0
paramtype: vlogparam
description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
PMPNumRegions:
datatype: int
default: 4
paramtype: vlogparam
description: "Number of PMP regions"
targets:
default:
filesets:
- tool_verilator ? (files_lint_verilator)
- files_rtl
- files_check_tool_requirements
lint:
filesets:
- tool_verilator ? (files_lint_verilator)
- files_rtl
- files_lint
- files_check_tool_requirements
parameters:
- SYNTHESIS=true
- RVFI=true
default_tool: verilator
toplevel: ibex_core
tools:
verilator:
mode: lint-only
verilator_options:
- "-Wall"
# RAM primitives wider than 64bit (required for ECC) fail to build in
# Verilator without increasing the unroll count (see Verilator#1266)
- "--unroll-count 72"
veriblelint:
ruleset: default
rules:
- "-parameter-name-style"
format:
filesets:
- files_rtl
parameters:
- SYNTHESIS=true
- RVFI=true
default_tool: veribleformat
toplevel: ibex_core
tools:
veribleformat:
verible_format_args:
- "--inplace"