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https://github.com/lowRISC/ibex.git
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0e7117fbec
Certain synthesis tools like DC are very smart at optimizing away redundant logic. Hence, we have to insert an optimization barrier at the IOs of the lockstep Ibex. This is achieved by manually buffering each bit using prim_buf. Our Xilinx and DC synthesis flows make sure that these buffers cannot be optimized away using keep attributes (Vivado) and size_only constraints (DC). Signed-off-by: Michael Schaffner <msf@google.com>
162 lines
4 KiB
Text
162 lines
4 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_top:0.1"
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description: "Ibex, a small RV32 CPU core"
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filesets:
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files_rtl:
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depend:
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- lowrisc:ibex:ibex_pkg
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- lowrisc:ibex:ibex_core
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- lowrisc:prim:buf
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files:
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- rtl/ibex_register_file_ff.sv # generic FF-based
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- rtl/ibex_register_file_fpga.sv # FPGA
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- rtl/ibex_register_file_latch.sv # ASIC
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- rtl/ibex_lockstep.sv
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- rtl/ibex_top.sv
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file_type: systemVerilogSource
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_lint_verible:
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files:
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- lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
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files_check_tool_requirements:
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depend:
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- lowrisc:tool:check_tool_requirements
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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FPGA_XILINX:
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datatype: bool
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description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
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default: false
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paramtype: vlogdefine
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RV32E:
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datatype: int
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default: 0
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paramtype: vlogparam
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RV32M:
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datatype: str
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default: ibex_pkg::RV32MFast
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paramtype: vlogdefine
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description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
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RV32B:
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datatype: str
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default: ibex_pkg::RV32BNone
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paramtype: vlogdefine
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description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
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RegFile:
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datatype: str
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default: ibex_pkg::RegFileFF
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paramtype: vlogdefine
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description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
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ICache:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable instruction cache"
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ICacheECC:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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BranchTargetALU:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
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WritebackStage:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
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BranchPredictor:
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datatype: int
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paramtype: vlogparam
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default: 0
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description: "Enables static branch prediction (EXPERIMENTAL)"
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SecureIbex:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
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PMPEnable:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable PMP"
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PMPGranularity:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
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PMPNumRegions:
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datatype: int
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default: 4
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paramtype: vlogparam
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description: "Number of PMP regions"
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targets:
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default: &default_target
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- tool_veriblelint ? (files_lint_verible)
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- files_rtl
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- files_check_tool_requirements
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toplevel: ibex_top
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parameters:
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- tool_vivado ? (FPGA_XILINX=true)
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lint:
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<<: *default_target
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: verilator
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: ibex_top
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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