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98 lines
No EOL
3.3 KiB
VHDL
98 lines
No EOL
3.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.all;
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entity MEM_WB_DIV is
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port (
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--INPUTS
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clock, clear : in std_logic;
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--WB control signals
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mux0_sel_in : in std_logic_vector(1 downto 0);
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reg_file_write_in : in std_logic;
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reg_file_write_address_in : in std_logic_vector(4 downto 0);
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--Data
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ALU_output_in : in std_logic_vector(31 downto 0);
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datamem_output_in : in std_logic_vector(31 downto 0);
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instruction_address_in : in std_logic_vector(31 downto 0);
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--OUTPUTS
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--WB control signals
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mux0_sel_out : out std_logic_vector(1 downto 0);
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reg_file_write_out : out std_logic;
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reg_file_write_address_out : out std_logic_vector(4 downto 0);
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--Data
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ALU_output_out : out std_logic_vector(31 downto 0);
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datamem_output_out : out std_logic_vector(31 downto 0);
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instruction_address_out : out std_logic_vector(31 downto 0)
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);
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end MEM_WB_DIV;
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architecture behavioral of MEM_WB_DIV is
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--INTERNAL SIGNALS
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--WB control signals
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signal mux0_sel_input_signal : std_logic_vector(1 downto 0);
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signal reg_file_write_input_signal : std_logic;
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signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0);
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--Data
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signal ALU_output_input_signal : std_logic_vector(31 downto 0);
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signal datamem_output_input_signal : std_logic_vector(31 downto 0);
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signal instruction_address_input_signal : std_logic_vector(31 downto 0);
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--WB control signals
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signal mux0_sel_output_signal : std_logic_vector(1 downto 0);
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signal reg_file_write_output_signal : std_logic;
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signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0);
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--Data
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signal ALU_output_output_signal : std_logic_vector(31 downto 0);
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signal datamem_output_output_signal : std_logic_vector(31 downto 0);
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signal instruction_address_output_signal : std_logic_vector(31 downto 0);
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begin
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--INTERNAL REGISTERS
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--WB control signals
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mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal);
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reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal);
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reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal);
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--Data
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ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal);
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datamem_output_reg : reg32b port map(datamem_output_input_signal, '1', clock, clear, datamem_output_output_signal);
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instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
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--WIRING INPUT PORTS
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--WB control signals
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mux0_sel_input_signal <= mux0_sel_in;
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reg_file_write_input_signal <= reg_file_write_in;
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reg_file_write_address_input_signal <= reg_file_write_address_in;
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--Data
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ALU_output_input_signal <= ALU_output_in;
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datamem_output_input_signal <= datamem_output_in;
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instruction_address_input_signal <= instruction_address_in;
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--WIRING OUTPUT PORTS
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--WB control signals
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mux0_sel_out <= mux0_sel_output_signal;
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reg_file_write_out <= reg_file_write_output_signal;
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reg_file_write_address_out <= reg_file_write_address_output_signal;
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--Data
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ALU_output_out <= ALU_output_output_signal;
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datamem_output_out <= datamem_output_output_signal;
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instruction_address_out <= instruction_address_output_signal;
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end behavioral; |