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25 lines
No EOL
682 B
VHDL
25 lines
No EOL
682 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity datamem is
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port (
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clock : in std_logic;
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write_enable : in std_logic;
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address : in std_logic_vector(15 downto 0);
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input_data : in std_logic_vector(7 downto 0);
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output_data : out std_logic_vector(7 downto 0)
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);
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end datamem;
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architecture behavioural of datamem is
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type ram_type is array (65536 downto 0) of std_logic_vector (7 downto 0);
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signal RAM : ram_type;
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begin
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process (clock, write_enable)
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begin
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if falling_edge(clock) and write_enable = '1' then
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RAM(conv_integer(address)) <= input_data;
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end if;
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end process;
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output_data <= RAM(conv_integer(address));
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end behavioural; |