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18 lines
No EOL
354 B
VHDL
18 lines
No EOL
354 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity mux_2_1 is
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port (
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selection : in std_logic;
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input_0, input_1 : in std_logic_vector(31 downto 0);
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output_0 : out std_logic_vector(31 downto 0)
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);
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end mux_2_1;
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architecture behavioral of mux_2_1 is
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begin
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with selection select
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output_0 <=
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input_0 when '0',
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input_1 when '1';
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end behavioral; |