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22 lines
No EOL
497 B
VHDL
22 lines
No EOL
497 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity mux_5_1 is
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port (
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selection : in std_logic_vector(2 downto 0);
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input_0, input_1, input_2, input_3, input_4 : in std_logic_vector(31 downto 0);
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output_0 : out std_logic_vector(31 downto 0)
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);
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end mux_5_1;
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architecture behavioral of mux_5_1 is
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begin
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with selection select
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output_0 <=
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input_0 when "000",
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input_1 when "001",
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input_2 when "010",
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input_3 when "011",
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input_4 when "100",
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X"00000000" when others;
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end behavioral; |