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26 lines
No EOL
695 B
VHDL
26 lines
No EOL
695 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.all;
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entity progmem_interface is
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port (
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clock : in std_logic;
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byte_address : in std_logic_vector(31 downto 0);
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output_data : out std_logic_vector(31 downto 0)
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);
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end entity progmem_interface;
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architecture behavioural of progmem_interface is
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signal memory_address : std_logic_vector(31 downto 0) := X"00000000";
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begin
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address_acquirement : process (byte_address)
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begin
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memory_address <= std_logic_vector(shift_right(unsigned(byte_address), 2)); --Dividing by 4 since 32 = 4*8
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end process;
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progmem_0 : progmem port map(memory_address(15 downto 0), clock, output_data);
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end architecture behavioural; |