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129 lines
No EOL
4.2 KiB
VHDL
129 lines
No EOL
4.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ALU is
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port (
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input_0, input_1 : in std_logic_vector(31 downto 0);
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operation : in std_logic_vector(3 downto 0);
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branch : in std_logic;
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ALU_branch_control : in std_logic_vector(2 downto 0);
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ALU_branch_response : out std_logic;
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ALU_output : out std_logic_vector(31 downto 0)
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);
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end entity ALU;
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architecture Behavioral of ALU is
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signal result_temp : std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
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begin
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process (input_0, input_1, operation, result_temp, branch, ALU_branch_control) is
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begin
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result_temp <= "000000000000000000000000000000000";
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if (branch = '1') then
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case ALU_branch_control is
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when "000" => --BEQ (branch if equal)
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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if (result_temp = "000000000000000000000000000000000") then
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ALU_branch_response <= '1';
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else
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ALU_branch_response <= '0';
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end if;
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when "001" => --BNE (branch not equal)
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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if (result_temp = "000000000000000000000000000000000") then
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ALU_branch_response <= '0';
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else
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ALU_branch_response <= '1';
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end if;
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when "100" => --BLT (branch less than)
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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if (result_temp(32) = '1') then
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ALU_branch_response <= '1';
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else
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ALU_branch_response <= '0';
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end if;
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when "101" => --BGE (branch greater than equal)
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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if (result_temp(32) = '0') then
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ALU_branch_response <= '1';
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else
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ALU_branch_response <= '0';
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end if;
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when "110" => --BLTU (branch less than unsigned)
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result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
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if (result_temp(32) = '1') then
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ALU_branch_response <= '1';
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else
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ALU_branch_response <= '0';
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end if;
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when "111" => --BGEU (branch greater than equal unsigned)
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result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
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if (result_temp(32) = '0') then
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ALU_branch_response <= '1';
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else
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ALU_branch_response <= '0';
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end if;
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when others =>
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ALU_branch_response <= '0';
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end case;
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else
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ALU_branch_response <= '0';
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case operation is
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when "0000" => -- ALU_output = input_0 + input_1
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) + signed(input_1(31) & input_1));
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ALU_output <= result_temp(31 downto 0);
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when "1000" => -- ALU_output = input_0 - input_1
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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ALU_output <= result_temp(31 downto 0);
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when "0001" => -- shift left logical
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ALU_output <= std_logic_vector(shift_left(unsigned(input_0), to_integer(unsigned(input_1))));
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when "0010" => -- set less than (signed)
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result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
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if (result_temp(32) = '1') then
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ALU_output <= X"00000001";
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else
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ALU_output <= X"00000000";
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end if;
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when "0011" => -- set less than unsigned
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result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
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if (result_temp(32) = '1') then
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ALU_output <= X"00000001";
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else
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ALU_output <= X"00000000";
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end if;
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when "0100" => -- xor port
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ALU_output <= input_0 xor input_1;
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when "0101" => -- shift right logical
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ALU_output <= std_logic_vector(shift_right(unsigned(input_0), to_integer(unsigned(input_1))));
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when "1101" => --shift right arithmetic
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ALU_output <= std_logic_vector(shift_right(signed(input_0), to_integer(unsigned(input_1))));
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when "0110" => -- or port
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ALU_output <= input_0 or input_1;
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when "0111" => -- and port
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ALU_output <= input_0 and input_1;
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when others => --apenas zera tudo
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result_temp(32 downto 0) <= "000000000000000000000000000000000";
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ALU_output <= result_temp(31 downto 0);
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end case;
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end if;
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end process;
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end architecture Behavioral; |