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53 lines
No EOL
1.3 KiB
VHDL
53 lines
No EOL
1.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.all;
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entity IF_ID_DIV is
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port (
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--INPUTS
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clock, clear : in std_logic;
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--Data
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instruction_address_in : in std_logic_vector(31 downto 0);
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instruction_data_in : in std_logic_vector(31 downto 0);
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--OUTPUTS
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--Data
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instruction_address_out : out std_logic_vector(31 downto 0);
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instruction_data_out : out std_logic_vector(31 downto 0)
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);
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end IF_ID_DIV;
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architecture behavioral of IF_ID_DIV is
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--INTERNAL SIGNALS
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--Data
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signal instruction_address_input_signal : std_logic_vector(31 downto 0);
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signal instruction_data_input_signal : std_logic_vector(31 downto 0);
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--Data
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signal instruction_address_output_signal : std_logic_vector(31 downto 0);
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signal instruction_data_output_signal : std_logic_vector(31 downto 0);
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begin
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--INTERNAL REGISTERS
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--Data
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instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
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instruction_data_reg : reg32b port map(instruction_data_input_signal, '1', clock, clear, instruction_data_output_signal);
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--WIRING OUTPUT PORTS
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--Data
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instruction_address_out <= instruction_address_output_signal;
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instruction_data_out <= instruction_data_output_signal;
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instruction_address_input_signal <= instruction_address_in;
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instruction_data_input_signal <= instruction_data_in;
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end behavioral; |