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23 lines
No EOL
619 B
VHDL
23 lines
No EOL
619 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity adder is
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port (
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input_0 : in std_logic_vector(31 downto 0);
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input_1 : in std_logic_vector(31 downto 0);
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output_0 : out std_logic_vector(31 downto 0)
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);
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end adder;
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architecture behavioral of adder is
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signal internal_output : std_logic_vector (32 downto 0) := "000000000000000000000000000000000";
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begin
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process (input_0, input_1, internal_output) is
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begin
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internal_output <= std_logic_vector(signed(input_0(31) & input_0) + signed(input_1(31) & input_1));
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end process;
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output_0 <= internal_output(31 downto 0);
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end behavioral; |