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https://github.com/Artoriuz/maestro.git
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494 lines
No EOL
20 KiB
VHDL
494 lines
No EOL
20 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.all;
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entity controller is
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port (
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clock : in std_logic;
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reset : in std_logic;
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instruction : in std_logic_vector(31 downto 0);
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reg_file_read_address_0 : out std_logic_vector(4 downto 0);
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reg_file_read_address_1 : out std_logic_vector(4 downto 0);
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reg_file_write : out std_logic;
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reg_file_write_address : out std_logic_vector(4 downto 0);
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immediate : out std_logic_vector(31 downto 0);
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ALU_operation : out std_logic_vector(3 downto 0);
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ALU_branch : out std_logic;
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ALU_branch_control : out std_logic_vector(2 downto 0);
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JTU_mux_sel : out std_logic;
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data_format : out std_logic_vector(2 downto 0);
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datamem_write : out std_logic;
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jump_flag : out std_logic;
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mux0_sel : out std_logic_vector(1 downto 0);
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mux1_sel : out std_logic
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);
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end entity controller;
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architecture Behavioral of controller is
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type operational_states is (normal);
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signal current_state, next_state : operational_states := normal;
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type instruction_cluster is (INVALID, LOAD, STORE, MADD, BRANCH, LOAD_FP, STORE_FP, MSUB, JALR, NMSUB, MISC_MEM, AMO, NMADD, JAL, OP_IMM, OP, OP_FP, SYSTEM, AUIPC, LUI, OP_IMM_32, OP_32);
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signal decoded_cluster : instruction_cluster;
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type opcode is (INVALID, LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW,
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ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, inst_SLL, SLT, SLTU, inst_XOR, inst_SRL, inst_SRA, inst_OR, inst_AND, FENCE,
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FENCEI, EXALL, EBREAK, CSRRW, CSRRS, CSRRC, CSRRSI, CSRRCI);
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signal decoded_opcode : opcode;
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signal fetched_instruction : std_logic_vector (31 downto 0) := X"00000000";
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signal internal_immediate : std_logic_vector (31 downto 0) := X"00000000";
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signal internal_reg_file_read_address_0 : std_logic_vector(4 downto 0) := "00000";
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signal internal_reg_file_read_address_1 : std_logic_vector(4 downto 0) := "00000";
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signal internal_reg_file_write : std_logic := '0';
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signal internal_reg_file_write_address : std_logic_vector(4 downto 0) := "00000";
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signal internal_PC_operation : std_logic_vector(2 downto 0) := "000";
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signal internal_ALU_operation : std_logic_vector(3 downto 0) := "0000";
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signal internal_ALU_branch : std_logic := '0';
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signal internal_ALU_branch_control : std_logic_vector(2 downto 0) := "000";
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signal internal_JTU_mux_sel : std_logic;
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signal internal_data_format : std_logic_vector(2 downto 0) := "000";
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signal internal_datamem_write : std_logic := '0';
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signal internal_jump_flag : std_logic := '0';
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signal internal_mux0_sel : std_logic_vector(1 downto 0) := "00";
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signal internal_mux1_sel : std_logic := '0';
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begin
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synchronism : process (clock, reset)
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begin
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if (reset = '1') then
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current_state <= normal;
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elsif rising_edge(clock) then
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current_state <= next_state;
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end if;
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end process;
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logic : process (fetched_instruction, decoded_cluster, decoded_opcode, current_state)
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begin
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case (current_state) is
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-- when start => --This states exists to clean the existing mess and restart the processor
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-- internal_reg_file_read_address_0 <= "00000";
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-- internal_reg_file_read_address_1 <= "00000";
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-- internal_reg_file_write <= '0';
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-- internal_reg_file_write_address <= "00000";
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-- internal_immediate <= X"00000000";
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-- internal_PC_operation <= "000";
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-- internal_ALU_operation <= "0000"; --unused number to make the ALU output 0
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-- internal_ALU_branch <= '0';
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-- internal_ALU_branch_control <= "000";
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-- internal_data_format <= "000";
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-- internal_datamem_write <= '0';
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-- internal_mux0_sel <= "00";
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-- internal_mux1_sel <= '0';
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-- next_state <= normal;
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when normal =>
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if fetched_instruction(1 downto 0) = "00" then
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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else
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case (fetched_instruction(4 downto 2)) is
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when "000" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --LOAD
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decoded_cluster <= LOAD;
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case (fetched_instruction(14 downto 12)) is --funct3
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when "000" => --Load Byte
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decoded_opcode <= LB;
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when "001" => --Load Half-Word
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decoded_opcode <= LH;
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when "010" => --Load Word
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decoded_opcode <= LW;
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when "100" => --Load Byte Unsigned
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decoded_opcode <= LBU;
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when "101" => --Load Hald-Word Unsigned
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decoded_opcode <= LHU;
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when others =>
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decoded_opcode <= INVALID;
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end case;
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when "01" => --STORE
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decoded_cluster <= STORE;
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case (fetched_instruction(14 downto 12)) is --funct3
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when "000" => --Store Byte
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decoded_opcode <= SB;
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when "001" => --Store Half-Word
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decoded_opcode <= SH;
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when "010" => --Store Word
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decoded_opcode <= SW;
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when others =>
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decoded_opcode <= INVALID;
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end case;
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when "10" => --MADD
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --BRANCH
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decoded_cluster <= BRANCH;
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case (fetched_instruction(14 downto 12)) is --funct3
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when "000" => --Branch if equal
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decoded_opcode <= BEQ;
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when "001" => --Branch if not equal
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decoded_opcode <= BNE;
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when "100" => --Branch if lower than
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decoded_opcode <= BLT;
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when "101" => --Branch if greater or equal
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decoded_opcode <= BGE;
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when "110" => --Branch if lower than unsigned
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decoded_opcode <= BLTU;
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when "111" => --Branch if greater or equal unsigned
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decoded_opcode <= BGEU;
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when others =>
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decoded_opcode <= INVALID;
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end case;
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end case;
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when "001" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --LOAD-FP
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "01" => --STORE-FP
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "10" => --MSUB
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --JALR
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decoded_cluster <= JALR;
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decoded_opcode <= JALR;
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end case;
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when "010" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --Custom 0
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "01" => --Custom 1
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "10" => --NMSUB
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --Reserved
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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end case;
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when "011" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --MISC-MEM
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "01" => --AMO
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "10" => --NMADD
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --JAL
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decoded_cluster <= JAL;
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decoded_opcode <= JAL;
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end case;
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when "100" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --OP-IMM
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decoded_cluster <= OP_IMM;
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case (fetched_instruction(14 downto 12)) is --funct3
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when "000" => --Add immediate
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decoded_opcode <= ADDI;
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when "010" => --Set less than immediate
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decoded_opcode <= SLTI;
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when "011" => --Set less than immediate unsigned
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decoded_opcode <= SLTIU;
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when "100" => --XOR immediate
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decoded_opcode <= XORI;
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when "110" => --OR immediate
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decoded_opcode <= ORI;
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when "111" => --AND immediate
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decoded_opcode <= ANDI;
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when "001" => --Shift left logical immediate
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decoded_opcode <= SLLI;
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when "101" => --Shift right immediate
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case (fetched_instruction(30)) is
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when '0' => --Shift right logical immediate
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decoded_opcode <= SRLI;
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when '1' => --Shift right arithmetic immediate
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decoded_opcode <= SRAI;
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end case;
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when others =>
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decoded_opcode <= INVALID;
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end case;
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when "01" => --OP
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decoded_cluster <= OP;
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case (fetched_instruction(14 downto 12)) is --funct3
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when "000" => --ADD or SUB
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case (fetched_instruction(30)) is
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when '0' => --Add
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decoded_opcode <= ADD;
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when '1' => --Sub
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decoded_opcode <= SUB;
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end case;
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when "001" => --Shift left logical
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decoded_opcode <= inst_SLL;
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when "010" => --Set less than
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decoded_opcode <= SLT;
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when "011" => --Set less than unsigned
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decoded_opcode <= SLTU;
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when "100" => --XOR
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decoded_opcode <= inst_XOR;
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when "101" => --Shift right
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case (fetched_instruction(30)) is
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when '0' => --Shift right logical
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decoded_opcode <= inst_SRL;
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when '1' => --Shift right arithmetic
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decoded_opcode <= inst_SRA;
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end case;
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when "110" => --OR
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decoded_opcode <= inst_OR;
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when "111" => --AND
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decoded_opcode <= inst_AND;
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end case;
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when "10" => --OP-FP
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --SYSTEM
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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end case;
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when "101" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --AUIPC
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decoded_cluster <= AUIPC;
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decoded_opcode <= AUIPC;
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when "01" => --LUI
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decoded_cluster <= LUI;
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decoded_opcode <= LUI;
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when "10" => --Reserved
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --Reserved
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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end case;
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when "110" =>
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case (fetched_instruction(6 downto 5)) is
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when "00" => --OP-IMM-32
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "01" => --OP-32
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "10" => --rv128
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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when "11" => --rv128
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decoded_cluster <= INVALID;
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decoded_opcode <= INVALID;
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end case;
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when others =>
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end case;
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end if;
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case (decoded_cluster) is
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when INVALID =>
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internal_reg_file_read_address_0 <= "00000";
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internal_reg_file_read_address_1 <= "00000";
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internal_reg_file_write <= '0';
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internal_reg_file_write_address <= "00000";
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internal_immediate <= X"00000000";
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internal_ALU_operation <= "0000"; --random unused number to make the ALU output 0
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000";
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internal_JTU_mux_sel <= '0';
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internal_data_format <= "000";
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internal_datamem_write <= '0';
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internal_jump_flag <= '0';
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internal_mux0_sel <= "00";
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internal_mux1_sel <= '0';
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next_state <= normal;
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when LOAD =>
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internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
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internal_reg_file_read_address_1 <= "00000";
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internal_reg_file_write <= '1'; --regfile is only lodaded on write_back
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 20));
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internal_ALU_operation <= "0000";
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000"; --BEQ, BNE, BLT, BGE, BLTU, BGEU
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internal_JTU_mux_sel <= '0';
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internal_data_format <= std_logic_vector(fetched_instruction(14 downto 12)); --LB, LH, LW, LBU, LHU
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internal_datamem_write <= '0';
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internal_jump_flag <= '0';
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internal_mux0_sel <= "01";
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internal_mux1_sel <= '1';
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next_state <= normal;
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when STORE =>
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internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
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internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
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internal_reg_file_write <= '0';
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 25) & fetched_instruction(11 downto 7));
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internal_ALU_operation <= "0000";
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000"; --BEQ, BNE, BLT, BGE, BLTU, BGEU
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internal_JTU_mux_sel <= '0';
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internal_data_format <= std_logic_vector(fetched_instruction(14 downto 12)); --SB, SH, SW
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internal_datamem_write <= '1'; --memory is only written on memory_access
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internal_jump_flag <= '0';
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internal_mux0_sel <= "00";
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internal_mux1_sel <= '1';
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next_state <= normal;
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when BRANCH =>
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internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
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internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
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internal_reg_file_write <= '0';
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_immediate <= std_logic_vector("00000000000000000" & fetched_instruction(31) & fetched_instruction(7) & fetched_instruction(30 downto 25) & fetched_instruction(11 downto 6) & '0');
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internal_ALU_operation <= "0000";
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internal_ALU_branch <= '1';
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internal_ALU_branch_control <= std_logic_vector(fetched_instruction(14 downto 12)); --BEQ, BNE, BLT, BGE, BLTU, BGEU
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internal_JTU_mux_sel <= '0';
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internal_data_format <= "000";
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internal_datamem_write <= '0';
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internal_jump_flag <= '0';
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internal_mux0_sel <= "00";
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internal_mux1_sel <= '0';
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next_state <= normal;
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when JALR =>
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internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
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internal_reg_file_read_address_1 <= "00000";
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internal_reg_file_write <= '1';
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31 downto 20) & "00000000000000000000"), 20));
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internal_ALU_operation <= "0000";
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000";
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internal_JTU_mux_sel <= '1';
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internal_data_format <= "000";
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internal_datamem_write <= '0';
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internal_jump_flag <= '1';
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internal_mux0_sel <= "10";
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internal_mux1_sel <= '0';
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next_state <= normal;
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when JAL =>
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internal_reg_file_read_address_0 <= "00000";
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internal_reg_file_read_address_1 <= "00000";
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internal_reg_file_write <= '1';
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31) & fetched_instruction(19 downto 12) & fetched_instruction(20) & fetched_instruction(30 downto 21) & '0' & "00000000000"), 11));
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internal_ALU_operation <= "0000";
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000";
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internal_JTU_mux_sel <= '0';
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internal_data_format <= "000";
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internal_datamem_write <= '0';
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internal_jump_flag <= '1';
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internal_mux0_sel <= "10";
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internal_mux1_sel <= '0';
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next_state <= normal;
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when OP_IMM => --ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
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internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
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internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
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internal_reg_file_write <= '1';
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internal_reg_file_write_address <= fetched_instruction(11 downto 7);
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internal_ALU_branch <= '0';
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internal_ALU_branch_control <= "000";
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internal_JTU_mux_sel <= '0';
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internal_data_format <= "000";
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internal_datamem_write <= '0';
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internal_jump_flag <= '0';
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internal_mux0_sel <= "00";
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internal_mux1_sel <= '1';
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case (decoded_opcode) is
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when ADDI | SLTI | SLTIU =>
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internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
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internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31 downto 20) & "00000000000000000000"), 20));
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when XORI | ORI | ANDI =>
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internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
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internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 20));
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when SLLI =>
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internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
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internal_immediate <= std_logic_vector("000000000000000000000000000" & fetched_instruction(24 downto 20));
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when SRLI | SRAI =>
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internal_ALU_operation <= std_logic_vector(fetched_instruction(30) & fetched_instruction(14 downto 12));
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internal_immediate <= std_logic_vector("000000000000000000000000000" & fetched_instruction(24 downto 20));
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when others =>
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end case;
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next_state <= normal;
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when OP =>
|
|
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
|
|
internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
|
|
internal_reg_file_write <= '1';
|
|
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
|
|
internal_immediate <= X"00000000";
|
|
internal_ALU_operation <= std_logic_vector(fetched_instruction(30) & fetched_instruction(14 downto 12));
|
|
internal_ALU_branch <= '0';
|
|
internal_ALU_branch_control <= "000";
|
|
internal_JTU_mux_sel <= '0';
|
|
internal_data_format <= "000";
|
|
internal_datamem_write <= '0';
|
|
internal_jump_flag <= '0';
|
|
internal_mux0_sel <= "00";
|
|
internal_mux1_sel <= '0';
|
|
next_state <= normal;
|
|
|
|
when AUIPC =>
|
|
internal_reg_file_read_address_0 <= "00000";
|
|
internal_reg_file_read_address_1 <= "00000";
|
|
internal_reg_file_write <= '1';
|
|
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
|
|
internal_immediate <= std_logic_vector(fetched_instruction(31 downto 12) & "000000000000");
|
|
internal_ALU_operation <= "0000";
|
|
internal_ALU_branch <= '0';
|
|
internal_ALU_branch_control <= "000";
|
|
internal_JTU_mux_sel <= '0';
|
|
internal_data_format <= "000";
|
|
internal_datamem_write <= '0';
|
|
internal_jump_flag <= '0';
|
|
internal_mux0_sel <= "00";
|
|
internal_mux1_sel <= '0';
|
|
next_state <= normal;
|
|
|
|
when LUI =>
|
|
internal_reg_file_read_address_0 <= "00000";
|
|
internal_reg_file_read_address_1 <= "00000";
|
|
internal_reg_file_write <= '1';
|
|
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
|
|
internal_immediate <= std_logic_vector(fetched_instruction(31 downto 12) & "000000000000");
|
|
internal_ALU_operation <= "0000";
|
|
internal_ALU_branch <= '0';
|
|
internal_ALU_branch_control <= "000";
|
|
internal_JTU_mux_sel <= '0';
|
|
internal_data_format <= "000";
|
|
internal_datamem_write <= '0';
|
|
internal_jump_flag <= '0';
|
|
internal_mux0_sel <= "00";
|
|
internal_mux1_sel <= '1';
|
|
next_state <= normal;
|
|
when others =>
|
|
end case;
|
|
end case;
|
|
end process;
|
|
fetched_instruction <= instruction;
|
|
reg_file_read_address_0 <= internal_reg_file_read_address_0;
|
|
reg_file_read_address_1 <= internal_reg_file_read_address_1;
|
|
reg_file_write <= internal_reg_file_write;
|
|
reg_file_write_address <= internal_reg_file_write_address;
|
|
immediate <= internal_immediate;
|
|
ALU_operation <= internal_ALU_operation;
|
|
ALU_branch <= internal_ALU_branch;
|
|
ALU_branch_control <= internal_ALU_branch_control;
|
|
JTU_mux_sel <= internal_JTU_mux_sel;
|
|
data_format <= internal_data_format;
|
|
datamem_write <= internal_datamem_write;
|
|
jump_flag <= internal_jump_flag;
|
|
mux0_sel <= internal_mux0_sel;
|
|
mux1_sel <= internal_mux1_sel;
|
|
|
|
end architecture Behavioral; |