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21 lines
No EOL
703 B
VHDL
21 lines
No EOL
703 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.all;
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entity jump_target_unit is
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port (
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mux_sel : in std_logic;
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current_instruction_address : in std_logic_vector(31 downto 0);
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regfile_address : in std_logic_vector(31 downto 0);
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immediate : in std_logic_vector(31 downto 0);
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target_address : out std_logic_vector(31 downto 0)
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);
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end jump_target_unit;
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architecture behavioral of jump_target_unit is
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signal mux_output : std_logic_vector (31 downto 0) := X"00000000";
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begin
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internal_mux : mux_2_1 port map(mux_sel, current_instruction_address, regfile_address, mux_output);
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internal_adder : adder port map(mux_output, immediate, target_address);
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end behavioral; |