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25 lines
No EOL
978 B
VHDL
25 lines
No EOL
978 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.all;
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entity program_counter is
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port (
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clear, clock : in std_logic;
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mux_sel : in std_logic;
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address_in_0 : in std_logic_vector(31 downto 0);
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address_in_1 : in std_logic_vector(31 downto 0);
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next_address : out std_logic_vector(31 downto 0); --THIS OUTPUT IS ONLY REQUIRED WHEN USING REGISTERED INPUT ALTERA MEMORY, SO THE INPUT REG CAN MIRROR THE PC'S INTERNAL REG.
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address_out : out std_logic_vector(31 downto 0) --THIS IS THE REAL PC OUTPUT, USE THIS IF YOUR MEMORY DOES NOT HAVE A REGISTER IN ITS INPUT.
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);
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end program_counter;
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architecture behavioral of program_counter is
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signal internal_address : std_logic_vector (31 downto 0) := X"00000000";
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begin
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internal_mux : mux_2_1 port map(mux_sel, address_in_0, address_in_1, internal_address);
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internal_register : reg32b port map(internal_address, '1', clock, clear, address_out);
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next_address <= internal_address;
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end behavioral; |