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180 lines
No EOL
10 KiB
VHDL
180 lines
No EOL
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity register_file is
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port (
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write_data : in std_logic_vector(31 downto 0);
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write_address : in std_logic_vector(4 downto 0);
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read_address_0 : in std_logic_vector(4 downto 0);
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read_address_1 : in std_logic_vector(4 downto 0);
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write_control, clock, clear : in std_logic;
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output_data_0 : out std_logic_vector(31 downto 0);
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output_data_1 : out std_logic_vector(31 downto 0);
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debug_x31_output : out std_logic_vector(31 downto 0);
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debug_x1_output : out std_logic_vector(31 downto 0);
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debug_x2_output : out std_logic_vector(31 downto 0)
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);
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end entity register_file;
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architecture Behavioral of register_file is
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signal internal_reg_load : std_logic_vector(31 downto 0) := X"00000000";
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signal x0_to_muxes : std_logic_vector(31 downto 0);
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signal x1_to_muxes : std_logic_vector(31 downto 0);
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signal x2_to_muxes : std_logic_vector(31 downto 0);
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signal x3_to_muxes : std_logic_vector(31 downto 0);
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signal x4_to_muxes : std_logic_vector(31 downto 0);
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signal x5_to_muxes : std_logic_vector(31 downto 0);
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signal x6_to_muxes : std_logic_vector(31 downto 0);
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signal x7_to_muxes : std_logic_vector(31 downto 0);
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signal x8_to_muxes : std_logic_vector(31 downto 0);
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signal x9_to_muxes : std_logic_vector(31 downto 0);
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signal x10_to_muxes : std_logic_vector(31 downto 0);
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signal x11_to_muxes : std_logic_vector(31 downto 0);
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signal x12_to_muxes : std_logic_vector(31 downto 0);
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signal x13_to_muxes : std_logic_vector(31 downto 0);
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signal x14_to_muxes : std_logic_vector(31 downto 0);
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signal x15_to_muxes : std_logic_vector(31 downto 0);
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signal x16_to_muxes : std_logic_vector(31 downto 0);
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signal x17_to_muxes : std_logic_vector(31 downto 0);
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signal x18_to_muxes : std_logic_vector(31 downto 0);
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signal x19_to_muxes : std_logic_vector(31 downto 0);
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signal x20_to_muxes : std_logic_vector(31 downto 0);
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signal x21_to_muxes : std_logic_vector(31 downto 0);
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signal x22_to_muxes : std_logic_vector(31 downto 0);
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signal x23_to_muxes : std_logic_vector(31 downto 0);
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signal x24_to_muxes : std_logic_vector(31 downto 0);
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signal x25_to_muxes : std_logic_vector(31 downto 0);
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signal x26_to_muxes : std_logic_vector(31 downto 0);
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signal x27_to_muxes : std_logic_vector(31 downto 0);
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signal x28_to_muxes : std_logic_vector(31 downto 0);
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signal x29_to_muxes : std_logic_vector(31 downto 0);
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signal x30_to_muxes : std_logic_vector(31 downto 0);
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signal x31_to_muxes : std_logic_vector(31 downto 0);
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begin
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register_load_decouple : process (write_address)
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begin
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if (write_control = '1') then
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case write_address is
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when "00000" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000000001";
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when "00001" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000000010";
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when "00010" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000000100";
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when "00011" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000001000";
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when "00100" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000010000";
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when "00101" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000000100000";
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when "00110" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000001000000";
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when "00111" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000010000000";
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when "01000" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000000100000000";
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when "01001" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000001000000000";
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when "01010" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000010000000000";
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when "01011" =>
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internal_reg_load(31 downto 0) <= "00000000000000000000100000000000";
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when "01100" =>
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internal_reg_load(31 downto 0) <= "00000000000000000001000000000000";
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when "01101" =>
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internal_reg_load(31 downto 0) <= "00000000000000000010000000000000";
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when "01110" =>
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internal_reg_load(31 downto 0) <= "00000000000000000100000000000000";
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when "01111" =>
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internal_reg_load(31 downto 0) <= "00000000000000001000000000000000";
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when "10000" =>
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internal_reg_load(31 downto 0) <= "00000000000000010000000000000000";
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when "10001" =>
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internal_reg_load(31 downto 0) <= "00000000000000100000000000000000";
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when "10010" =>
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internal_reg_load(31 downto 0) <= "00000000000001000000000000000000";
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when "10011" =>
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internal_reg_load(31 downto 0) <= "00000000000010000000000000000000";
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when "10100" =>
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internal_reg_load(31 downto 0) <= "00000000000100000000000000000000";
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when "10101" =>
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internal_reg_load(31 downto 0) <= "00000000001000000000000000000000";
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when "10110" =>
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internal_reg_load(31 downto 0) <= "00000000010000000000000000000000";
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when "10111" =>
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internal_reg_load(31 downto 0) <= "00000000100000000000000000000000";
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when "11000" =>
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internal_reg_load(31 downto 0) <= "00000001000000000000000000000000";
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when "11001" =>
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internal_reg_load(31 downto 0) <= "00000010000000000000000000000000";
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when "11010" =>
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internal_reg_load(31 downto 0) <= "00000100000000000000000000000000";
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when "11011" =>
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internal_reg_load(31 downto 0) <= "00001000000000000000000000000000";
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when "11100" =>
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internal_reg_load(31 downto 0) <= "00010000000000000000000000000000";
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when "11101" =>
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internal_reg_load(31 downto 0) <= "00100000000000000000000000000000";
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when "11110" =>
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internal_reg_load(31 downto 0) <= "01000000000000000000000000000000";
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when "11111" =>
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internal_reg_load(31 downto 0) <= "10000000000000000000000000000000";
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end case;
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else
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internal_reg_load(31 downto 0) <= "00000000000000000000000000000000";
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end if;
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end process;
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reg_x0 : reg32b_falling_edge port map(X"00000000", '1', clock, clear, x0_to_muxes);
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reg_x1 : reg32b_falling_edge port map(write_data, internal_reg_load(1), clock, clear, x1_to_muxes);
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reg_x2 : reg32b_falling_edge port map(write_data, internal_reg_load(2), clock, clear, x2_to_muxes);
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reg_x3 : reg32b_falling_edge port map(write_data, internal_reg_load(3), clock, clear, x3_to_muxes);
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reg_x4 : reg32b_falling_edge port map(write_data, internal_reg_load(4), clock, clear, x4_to_muxes);
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reg_x5 : reg32b_falling_edge port map(write_data, internal_reg_load(5), clock, clear, x5_to_muxes);
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reg_x6 : reg32b_falling_edge port map(write_data, internal_reg_load(6), clock, clear, x6_to_muxes);
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reg_x7 : reg32b_falling_edge port map(write_data, internal_reg_load(7), clock, clear, x7_to_muxes);
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reg_x8 : reg32b_falling_edge port map(write_data, internal_reg_load(8), clock, clear, x8_to_muxes);
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reg_x9 : reg32b_falling_edge port map(write_data, internal_reg_load(9), clock, clear, x9_to_muxes);
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reg_x10 : reg32b_falling_edge port map(write_data, internal_reg_load(10), clock, clear, x10_to_muxes);
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reg_x11 : reg32b_falling_edge port map(write_data, internal_reg_load(11), clock, clear, x11_to_muxes);
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reg_x12 : reg32b_falling_edge port map(write_data, internal_reg_load(12), clock, clear, x12_to_muxes);
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reg_x13 : reg32b_falling_edge port map(write_data, internal_reg_load(13), clock, clear, x13_to_muxes);
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reg_x14 : reg32b_falling_edge port map(write_data, internal_reg_load(14), clock, clear, x14_to_muxes);
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reg_x15 : reg32b_falling_edge port map(write_data, internal_reg_load(15), clock, clear, x15_to_muxes);
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reg_x16 : reg32b_falling_edge port map(write_data, internal_reg_load(16), clock, clear, x16_to_muxes);
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reg_x17 : reg32b_falling_edge port map(write_data, internal_reg_load(17), clock, clear, x17_to_muxes);
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reg_x18 : reg32b_falling_edge port map(write_data, internal_reg_load(18), clock, clear, x18_to_muxes);
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reg_x19 : reg32b_falling_edge port map(write_data, internal_reg_load(19), clock, clear, x19_to_muxes);
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reg_x20 : reg32b_falling_edge port map(write_data, internal_reg_load(20), clock, clear, x20_to_muxes);
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reg_x21 : reg32b_falling_edge port map(write_data, internal_reg_load(21), clock, clear, x21_to_muxes);
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reg_x22 : reg32b_falling_edge port map(write_data, internal_reg_load(22), clock, clear, x22_to_muxes);
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reg_x23 : reg32b_falling_edge port map(write_data, internal_reg_load(23), clock, clear, x23_to_muxes);
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reg_x24 : reg32b_falling_edge port map(write_data, internal_reg_load(24), clock, clear, x24_to_muxes);
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reg_x25 : reg32b_falling_edge port map(write_data, internal_reg_load(25), clock, clear, x25_to_muxes);
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reg_x26 : reg32b_falling_edge port map(write_data, internal_reg_load(26), clock, clear, x26_to_muxes);
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reg_x27 : reg32b_falling_edge port map(write_data, internal_reg_load(27), clock, clear, x27_to_muxes);
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reg_x28 : reg32b_falling_edge port map(write_data, internal_reg_load(28), clock, clear, x28_to_muxes);
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reg_x29 : reg32b_falling_edge port map(write_data, internal_reg_load(29), clock, clear, x29_to_muxes);
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reg_x30 : reg32b_falling_edge port map(write_data, internal_reg_load(30), clock, clear, x30_to_muxes);
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reg_x31 : reg32b_falling_edge port map(write_data, internal_reg_load(31), clock, clear, x31_to_muxes);
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output_1_mux : mux_32_1 port map(
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read_address_0, x0_to_muxes, x1_to_muxes, x2_to_muxes, x3_to_muxes, x4_to_muxes, x5_to_muxes, x6_to_muxes, x7_to_muxes,
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x8_to_muxes, x9_to_muxes, x10_to_muxes, x11_to_muxes, x12_to_muxes, x13_to_muxes, x14_to_muxes, x15_to_muxes, x16_to_muxes,
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x17_to_muxes, x18_to_muxes, x19_to_muxes, x20_to_muxes, x21_to_muxes, x22_to_muxes, x23_to_muxes, x24_to_muxes, x25_to_muxes,
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x26_to_muxes, x27_to_muxes, x28_to_muxes, x29_to_muxes, x30_to_muxes, x31_to_muxes, output_data_0);
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output_2_mux : mux_32_1 port map(
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read_address_1, x0_to_muxes, x1_to_muxes, x2_to_muxes, x3_to_muxes, x4_to_muxes, x5_to_muxes, x6_to_muxes, x7_to_muxes,
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x8_to_muxes, x9_to_muxes, x10_to_muxes, x11_to_muxes, x12_to_muxes, x13_to_muxes, x14_to_muxes, x15_to_muxes, x16_to_muxes,
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x17_to_muxes, x18_to_muxes, x19_to_muxes, x20_to_muxes, x21_to_muxes, x22_to_muxes, x23_to_muxes, x24_to_muxes, x25_to_muxes,
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x26_to_muxes, x27_to_muxes, x28_to_muxes, x29_to_muxes, x30_to_muxes, x31_to_muxes, output_data_1);
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debug_x31_output <= x31_to_muxes;
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debug_x1_output <= x1_to_muxes;
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debug_x2_output <= x2_to_muxes;
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end architecture Behavioral; |