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54 lines
3.1 KiB
Text
54 lines
3.1 KiB
Text
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV GX" LPM_DECODES=8 LPM_WIDTH=3 data eq
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--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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--synthesis_resources = lut 8
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SUBDESIGN decode_eca
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(
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data[2..0] : input;
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eq[7..0] : output;
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)
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VARIABLE
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data_wire[2..0] : WIRE;
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eq_node[7..0] : WIRE;
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eq_wire[7..0] : WIRE;
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w_anode1046w[3..0] : WIRE;
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w_anode1064w[3..0] : WIRE;
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w_anode1075w[3..0] : WIRE;
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w_anode1086w[3..0] : WIRE;
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w_anode1097w[3..0] : WIRE;
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w_anode1108w[3..0] : WIRE;
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w_anode1119w[3..0] : WIRE;
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w_anode1130w[3..0] : WIRE;
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BEGIN
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data_wire[] = data[];
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eq[] = eq_node[];
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eq_node[7..0] = eq_wire[7..0];
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eq_wire[] = ( w_anode1130w[3..3], w_anode1119w[3..3], w_anode1108w[3..3], w_anode1097w[3..3], w_anode1086w[3..3], w_anode1075w[3..3], w_anode1064w[3..3], w_anode1046w[3..3]);
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w_anode1046w[] = ( (w_anode1046w[2..2] & (! data_wire[2..2])), (w_anode1046w[1..1] & (! data_wire[1..1])), (w_anode1046w[0..0] & (! data_wire[0..0])), B"1");
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w_anode1064w[] = ( (w_anode1064w[2..2] & (! data_wire[2..2])), (w_anode1064w[1..1] & (! data_wire[1..1])), (w_anode1064w[0..0] & data_wire[0..0]), B"1");
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w_anode1075w[] = ( (w_anode1075w[2..2] & (! data_wire[2..2])), (w_anode1075w[1..1] & data_wire[1..1]), (w_anode1075w[0..0] & (! data_wire[0..0])), B"1");
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w_anode1086w[] = ( (w_anode1086w[2..2] & (! data_wire[2..2])), (w_anode1086w[1..1] & data_wire[1..1]), (w_anode1086w[0..0] & data_wire[0..0]), B"1");
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w_anode1097w[] = ( (w_anode1097w[2..2] & data_wire[2..2]), (w_anode1097w[1..1] & (! data_wire[1..1])), (w_anode1097w[0..0] & (! data_wire[0..0])), B"1");
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w_anode1108w[] = ( (w_anode1108w[2..2] & data_wire[2..2]), (w_anode1108w[1..1] & (! data_wire[1..1])), (w_anode1108w[0..0] & data_wire[0..0]), B"1");
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w_anode1119w[] = ( (w_anode1119w[2..2] & data_wire[2..2]), (w_anode1119w[1..1] & data_wire[1..1]), (w_anode1119w[0..0] & (! data_wire[0..0])), B"1");
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w_anode1130w[] = ( (w_anode1130w[2..2] & data_wire[2..2]), (w_anode1130w[1..1] & data_wire[1..1]), (w_anode1130w[0..0] & data_wire[0..0]), B"1");
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END;
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--VALID FILE
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