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maestro/Quartus/riscv_microcontroller/db/prev_cmp_riscv_microcontroller.qmsg
João Vitor Rafael Chrisóstomo d9ee52826d Adding all the files
2019-09-11 21:17:07 -03:00

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1565809784069 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1565809784069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 14 16:09:43 2019 " "Processing started: Wed Aug 14 16:09:43 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1565809784069 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809784069 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off riscv_microcontroller -c riscv_microcontroller " "Command: quartus_map --read_settings_files=on --write_settings_files=off riscv_microcontroller -c riscv_microcontroller" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809784069 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1565809784523 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1565809784523 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datamem.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datamem.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 datamem-behavioural " "Found design unit 1: datamem-behavioural" { } { { "../../Project/Components/datamem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795192 ""} { "Info" "ISGN_ENTITY_NAME" "1 datamem " "Found entity 1: datamem" { } { { "../../Project/Components/datamem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795192 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795192 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_5_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_5_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_5_1-behavioral " "Found design unit 1: mux_5_1-behavioral" { } { { "../../Project/Components/mux_5_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_5_1.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795192 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux_5_1 " "Found entity 1: mux_5_1" { } { { "../../Project/Components/mux_5_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_5_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795192 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795192 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/jump_target_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/jump_target_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jump_target_unit-behavioral " "Found design unit 1: jump_target_unit-behavioral" { } { { "../../Project/Components/jump_target_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/jump_target_unit.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795200 ""} { "Info" "ISGN_ENTITY_NAME" "1 jump_target_unit " "Found entity 1: jump_target_unit" { } { { "../../Project/Components/jump_target_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/jump_target_unit.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795200 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795200 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/flushing_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/flushing_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 flushing_unit-behavioural " "Found design unit 1: flushing_unit-behavioural" { } { { "../../Project/Components/flushing_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/flushing_unit.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} { "Info" "ISGN_ENTITY_NAME" "1 flushing_unit " "Found entity 1: flushing_unit" { } { { "../../Project/Components/flushing_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/flushing_unit.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795202 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/adder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder-behavioral " "Found design unit 1: adder-behavioral" { } { { "../../Project/Components/adder.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/adder.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} { "Info" "ISGN_ENTITY_NAME" "1 adder " "Found entity 1: adder" { } { { "../../Project/Components/adder.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/adder.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795202 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg32b_falling_edge.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg32b_falling_edge.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg32b_falling_edge-description " "Found design unit 1: reg32b_falling_edge-description" { } { { "../../Project/Components/reg32b_falling_edge.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b_falling_edge.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg32b_falling_edge " "Found entity 1: reg32b_falling_edge" { } { { "../../Project/Components/reg32b_falling_edge.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b_falling_edge.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795202 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/if_id_div.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/if_id_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IF_ID_DIV-behavioral " "Found design unit 1: IF_ID_DIV-behavioral" { } { { "../../Project/Components/IF_ID_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/IF_ID_DIV.vhd" 24 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795210 ""} { "Info" "ISGN_ENTITY_NAME" "1 IF_ID_DIV " "Found entity 1: IF_ID_DIV" { } { { "../../Project/Components/IF_ID_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/IF_ID_DIV.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795210 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795210 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/forwarding_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/forwarding_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 forwarding_unit-structural " "Found design unit 1: forwarding_unit-structural" { } { { "../../Project/Components/forwarding_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/forwarding_unit.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} { "Info" "ISGN_ENTITY_NAME" "1 forwarding_unit " "Found entity 1: forwarding_unit" { } { { "../../Project/Components/forwarding_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/forwarding_unit.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795212 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg4b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg4b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg4b-description " "Found design unit 1: reg4b-description" { } { { "../../Project/Components/reg4b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg4b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg4b " "Found entity 1: reg4b" { } { { "../../Project/Components/reg4b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg4b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795212 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg3b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg3b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg3b-description " "Found design unit 1: reg3b-description" { } { { "../../Project/Components/reg3b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg3b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg3b " "Found entity 1: reg3b" { } { { "../../Project/Components/reg3b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg3b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795212 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg2b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg2b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg2b-description " "Found design unit 1: reg2b-description" { } { { "../../Project/Components/reg2b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg2b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg2b " "Found entity 1: reg2b" { } { { "../../Project/Components/reg2b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg2b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795212 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795212 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg1b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg1b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg1b-description " "Found design unit 1: reg1b-description" { } { { "../../Project/Components/reg1b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg1b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795220 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg1b " "Found entity 1: reg1b" { } { { "../../Project/Components/reg1b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg1b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795220 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795220 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mem_wb_div.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mem_wb_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MEM_WB_DIV-behavioral " "Found design unit 1: MEM_WB_DIV-behavioral" { } { { "../../Project/Components/MEM_WB_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/MEM_WB_DIV.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} { "Info" "ISGN_ENTITY_NAME" "1 MEM_WB_DIV " "Found entity 1: MEM_WB_DIV" { } { { "../../Project/Components/MEM_WB_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/MEM_WB_DIV.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795222 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/id_ex_div.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/id_ex_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ID_EX_DIV-behavioral " "Found design unit 1: ID_EX_DIV-behavioral" { } { { "../../Project/Components/ID_EX_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 70 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} { "Info" "ISGN_ENTITY_NAME" "1 ID_EX_DIV " "Found entity 1: ID_EX_DIV" { } { { "../../Project/Components/ID_EX_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795222 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/ex_mem_div.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/ex_mem_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 EX_MEM_DIV-behavioral " "Found design unit 1: EX_MEM_DIV-behavioral" { } { { "../../Project/Components/EX_MEM_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/EX_MEM_DIV.vhd" 48 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} { "Info" "ISGN_ENTITY_NAME" "1 EX_MEM_DIV " "Found entity 1: EX_MEM_DIV" { } { { "../../Project/Components/EX_MEM_DIV.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/EX_MEM_DIV.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795222 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/register_file.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/register_file.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 register_file-Behavioral " "Found design unit 1: register_file-Behavioral" { } { { "../../Project/Components/register_file.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/register_file.vhd" 20 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} { "Info" "ISGN_ENTITY_NAME" "1 register_file " "Found entity 1: register_file" { } { { "../../Project/Components/register_file.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/register_file.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795232 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg32b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg32b-description " "Found design unit 1: reg32b-description" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg32b " "Found entity 1: reg32b" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795232 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/program_counter.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/program_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 program_counter-behavioral " "Found design unit 1: program_counter-behavioral" { } { { "../../Project/Components/program_counter.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/program_counter.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} { "Info" "ISGN_ENTITY_NAME" "1 program_counter " "Found entity 1: program_counter" { } { { "../../Project/Components/program_counter.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/program_counter.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795232 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/progmem_interface.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/progmem_interface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 progmem_interface-behavioural " "Found design unit 1: progmem_interface-behavioural" { } { { "../../Project/Components/progmem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/progmem_interface.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} { "Info" "ISGN_ENTITY_NAME" "1 progmem_interface " "Found entity 1: progmem_interface" { } { { "../../Project/Components/progmem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/progmem_interface.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795232 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_32_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_32_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_32_1-behavioral " "Found design unit 1: mux_32_1-behavioral" { } { { "../../Project/Components/mux_32_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_32_1.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795240 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux_32_1 " "Found entity 1: mux_32_1" { } { { "../../Project/Components/mux_32_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_32_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795240 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795240 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_2_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_2_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_2_1-behavioral " "Found design unit 1: mux_2_1-behavioral" { } { { "../../Project/Components/mux_2_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_2_1.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux_2_1 " "Found entity 1: mux_2_1" { } { { "../../Project/Components/mux_2_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_2_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795242 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/microcontroller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/microcontroller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 microcontroller-structural " "Found design unit 1: microcontroller-structural" { } { { "../../Project/Components/microcontroller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/microcontroller.vhd" 39 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} { "Info" "ISGN_ENTITY_NAME" "1 microcontroller " "Found entity 1: microcontroller" { } { { "../../Project/Components/microcontroller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/microcontroller.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795242 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datapath.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datapath.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 datapath-structural " "Found design unit 1: datapath-structural" { } { { "../../Project/Components/datapath.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 50 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} { "Info" "ISGN_ENTITY_NAME" "1 datapath " "Found entity 1: datapath" { } { { "../../Project/Components/datapath.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795242 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datamem_interface.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/datamem_interface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 datamem_interface-behavioural " "Found design unit 1: datamem_interface-behavioural" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795250 ""} { "Info" "ISGN_ENTITY_NAME" "1 datamem_interface " "Found entity 1: datamem_interface" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795250 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-Behavioral " "Found design unit 1: controller-Behavioral" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Found entity 1: controller" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/alu.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/alu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU-Behavioral " "Found design unit 1: ALU-Behavioral" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_3_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/mux_3_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_3_1-behavioral " "Found design unit 1: mux_3_1-behavioral" { } { { "../../Project/Components/mux_3_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_3_1.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux_3_1 " "Found entity 1: mux_3_1" { } { { "../../Project/Components/mux_3_1.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/mux_3_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg5b.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /documents-bkp/ufrn/tcc - with debug signals - copy/project/components/reg5b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg5b-description " "Found design unit 1: reg5b-description" { } { { "../../Project/Components/reg5b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg5b.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795261 ""} { "Info" "ISGN_ENTITY_NAME" "1 reg5b " "Found entity 1: reg5b" { } { { "../../Project/Components/reg5b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg5b.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795261 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795261 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "progmem.vhd 2 1 " "Found 2 design units, including 1 entities, in source file progmem.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 progmem-SYN " "Found design unit 1: progmem-SYN" { } { { "progmem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/progmem.vhd" 52 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795263 ""} { "Info" "ISGN_ENTITY_NAME" "1 progmem " "Found entity 1: progmem" { } { { "progmem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/progmem.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809795263 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795263 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "microcontroller " "Elaborating entity \"microcontroller\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1565809795818 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller controller:controller_0 " "Elaborating entity \"controller\" for hierarchy \"controller:controller_0\"" { } { { "../../Project/Components/microcontroller.vhd" "controller_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/microcontroller.vhd" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 ""}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "decoded_cluster controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"decoded_cluster\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "decoded_opcode controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"decoded_opcode\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_reg_file_read_address_0 controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_reg_file_read_address_0\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_reg_file_read_address_1 controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_reg_file_read_address_1\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_reg_file_write controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_reg_file_write\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_reg_file_write_address controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_reg_file_write_address\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_immediate controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_immediate\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_ALU_operation controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_ALU_operation\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_ALU_branch controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_ALU_branch\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_ALU_branch_control controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_ALU_branch_control\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_JTU_mux_sel controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_JTU_mux_sel\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_data_format controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_data_format\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_datamem_write controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_datamem_write\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_jump_flag controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_jump_flag\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_mux0_sel controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_mux0_sel\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_mux1_sel controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"internal_mux1_sel\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "next_state controller.vhd(68) " "VHDL Process Statement warning at controller.vhd(68): inferring latch(es) for signal or variable \"next_state\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_mux1_sel controller.vhd(68) " "Inferred latch for \"internal_mux1_sel\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_mux0_sel\[0\] controller.vhd(68) " "Inferred latch for \"internal_mux0_sel\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_mux0_sel\[1\] controller.vhd(68) " "Inferred latch for \"internal_mux0_sel\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_jump_flag controller.vhd(68) " "Inferred latch for \"internal_jump_flag\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_datamem_write controller.vhd(68) " "Inferred latch for \"internal_datamem_write\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_data_format\[0\] controller.vhd(68) " "Inferred latch for \"internal_data_format\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_data_format\[1\] controller.vhd(68) " "Inferred latch for \"internal_data_format\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_data_format\[2\] controller.vhd(68) " "Inferred latch for \"internal_data_format\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_JTU_mux_sel controller.vhd(68) " "Inferred latch for \"internal_JTU_mux_sel\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_branch_control\[0\] controller.vhd(68) " "Inferred latch for \"internal_ALU_branch_control\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_branch_control\[1\] controller.vhd(68) " "Inferred latch for \"internal_ALU_branch_control\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_branch_control\[2\] controller.vhd(68) " "Inferred latch for \"internal_ALU_branch_control\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_branch controller.vhd(68) " "Inferred latch for \"internal_ALU_branch\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_operation\[0\] controller.vhd(68) " "Inferred latch for \"internal_ALU_operation\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_operation\[1\] controller.vhd(68) " "Inferred latch for \"internal_ALU_operation\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_operation\[2\] controller.vhd(68) " "Inferred latch for \"internal_ALU_operation\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_ALU_operation\[3\] controller.vhd(68) " "Inferred latch for \"internal_ALU_operation\[3\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[0\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[1\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[2\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[3\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[3\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[4\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[4\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[5\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[5\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[6\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[6\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[7\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[7\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[8\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[8\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[9\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[9\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[10\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[10\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[11\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[11\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[12\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[12\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[13\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[13\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[14\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[14\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[15\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[15\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[16\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[16\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[17\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[17\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[18\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[18\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[19\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[19\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[20\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[20\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[21\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[21\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[22\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[22\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[23\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[23\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[24\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[24\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[25\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[25\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[26\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[26\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[27\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[27\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[28\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[28\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[29\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[29\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[30\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[30\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_immediate\[31\] controller.vhd(68) " "Inferred latch for \"internal_immediate\[31\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write_address\[0\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_write_address\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write_address\[1\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_write_address\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write_address\[2\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_write_address\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write_address\[3\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_write_address\[3\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write_address\[4\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_write_address\[4\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_write controller.vhd(68) " "Inferred latch for \"internal_reg_file_write\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_1\[0\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_1\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_1\[1\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_1\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_1\[2\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_1\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_1\[3\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_1\[3\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_1\[4\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_1\[4\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_0\[0\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_0\[0\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_0\[1\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_0\[1\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_0\[2\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_0\[2\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_0\[3\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_0\[3\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_reg_file_read_address_0\[4\] controller.vhd(68) " "Inferred latch for \"internal_reg_file_read_address_0\[4\]\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.CSRRCI controller.vhd(68) " "Inferred latch for \"decoded_opcode.CSRRCI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.CSRRSI controller.vhd(68) " "Inferred latch for \"decoded_opcode.CSRRSI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.CSRRC controller.vhd(68) " "Inferred latch for \"decoded_opcode.CSRRC\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.CSRRS controller.vhd(68) " "Inferred latch for \"decoded_opcode.CSRRS\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.CSRRW controller.vhd(68) " "Inferred latch for \"decoded_opcode.CSRRW\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.EBREAK controller.vhd(68) " "Inferred latch for \"decoded_opcode.EBREAK\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.EXALL controller.vhd(68) " "Inferred latch for \"decoded_opcode.EXALL\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.FENCEI controller.vhd(68) " "Inferred latch for \"decoded_opcode.FENCEI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.FENCE controller.vhd(68) " "Inferred latch for \"decoded_opcode.FENCE\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_AND controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_AND\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_OR controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_OR\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795856 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_SRA controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_SRA\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_SRL controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_SRL\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_XOR controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_XOR\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SLTU controller.vhd(68) " "Inferred latch for \"decoded_opcode.SLTU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SLT controller.vhd(68) " "Inferred latch for \"decoded_opcode.SLT\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.inst_SLL controller.vhd(68) " "Inferred latch for \"decoded_opcode.inst_SLL\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SUB controller.vhd(68) " "Inferred latch for \"decoded_opcode.SUB\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.ADD controller.vhd(68) " "Inferred latch for \"decoded_opcode.ADD\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SRAI controller.vhd(68) " "Inferred latch for \"decoded_opcode.SRAI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SRLI controller.vhd(68) " "Inferred latch for \"decoded_opcode.SRLI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SLLI controller.vhd(68) " "Inferred latch for \"decoded_opcode.SLLI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.ANDI controller.vhd(68) " "Inferred latch for \"decoded_opcode.ANDI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.ORI controller.vhd(68) " "Inferred latch for \"decoded_opcode.ORI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.XORI controller.vhd(68) " "Inferred latch for \"decoded_opcode.XORI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SLTIU controller.vhd(68) " "Inferred latch for \"decoded_opcode.SLTIU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SLTI controller.vhd(68) " "Inferred latch for \"decoded_opcode.SLTI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.ADDI controller.vhd(68) " "Inferred latch for \"decoded_opcode.ADDI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SW controller.vhd(68) " "Inferred latch for \"decoded_opcode.SW\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SH controller.vhd(68) " "Inferred latch for \"decoded_opcode.SH\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.SB controller.vhd(68) " "Inferred latch for \"decoded_opcode.SB\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LHU controller.vhd(68) " "Inferred latch for \"decoded_opcode.LHU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LBU controller.vhd(68) " "Inferred latch for \"decoded_opcode.LBU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LW controller.vhd(68) " "Inferred latch for \"decoded_opcode.LW\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LH controller.vhd(68) " "Inferred latch for \"decoded_opcode.LH\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LB controller.vhd(68) " "Inferred latch for \"decoded_opcode.LB\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BGEU controller.vhd(68) " "Inferred latch for \"decoded_opcode.BGEU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BLTU controller.vhd(68) " "Inferred latch for \"decoded_opcode.BLTU\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BGE controller.vhd(68) " "Inferred latch for \"decoded_opcode.BGE\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BLT controller.vhd(68) " "Inferred latch for \"decoded_opcode.BLT\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BNE controller.vhd(68) " "Inferred latch for \"decoded_opcode.BNE\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.BEQ controller.vhd(68) " "Inferred latch for \"decoded_opcode.BEQ\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.JALR controller.vhd(68) " "Inferred latch for \"decoded_opcode.JALR\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.JAL controller.vhd(68) " "Inferred latch for \"decoded_opcode.JAL\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.AUIPC controller.vhd(68) " "Inferred latch for \"decoded_opcode.AUIPC\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.LUI controller.vhd(68) " "Inferred latch for \"decoded_opcode.LUI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_opcode.INVALID controller.vhd(68) " "Inferred latch for \"decoded_opcode.INVALID\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.OP_32 controller.vhd(68) " "Inferred latch for \"decoded_cluster.OP_32\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.OP_IMM_32 controller.vhd(68) " "Inferred latch for \"decoded_cluster.OP_IMM_32\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.LUI controller.vhd(68) " "Inferred latch for \"decoded_cluster.LUI\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.AUIPC controller.vhd(68) " "Inferred latch for \"decoded_cluster.AUIPC\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.SYSTEM controller.vhd(68) " "Inferred latch for \"decoded_cluster.SYSTEM\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.OP_FP controller.vhd(68) " "Inferred latch for \"decoded_cluster.OP_FP\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.OP controller.vhd(68) " "Inferred latch for \"decoded_cluster.OP\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.OP_IMM controller.vhd(68) " "Inferred latch for \"decoded_cluster.OP_IMM\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.JAL controller.vhd(68) " "Inferred latch for \"decoded_cluster.JAL\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.NMADD controller.vhd(68) " "Inferred latch for \"decoded_cluster.NMADD\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.AMO controller.vhd(68) " "Inferred latch for \"decoded_cluster.AMO\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.MISC_MEM controller.vhd(68) " "Inferred latch for \"decoded_cluster.MISC_MEM\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.NMSUB controller.vhd(68) " "Inferred latch for \"decoded_cluster.NMSUB\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.JALR controller.vhd(68) " "Inferred latch for \"decoded_cluster.JALR\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.MSUB controller.vhd(68) " "Inferred latch for \"decoded_cluster.MSUB\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.STORE_FP controller.vhd(68) " "Inferred latch for \"decoded_cluster.STORE_FP\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.LOAD_FP controller.vhd(68) " "Inferred latch for \"decoded_cluster.LOAD_FP\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.BRANCH controller.vhd(68) " "Inferred latch for \"decoded_cluster.BRANCH\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.MADD controller.vhd(68) " "Inferred latch for \"decoded_cluster.MADD\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.STORE controller.vhd(68) " "Inferred latch for \"decoded_cluster.STORE\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.LOAD controller.vhd(68) " "Inferred latch for \"decoded_cluster.LOAD\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "decoded_cluster.INVALID controller.vhd(68) " "Inferred latch for \"decoded_cluster.INVALID\" at controller.vhd(68)" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809795872 "|microcontroller|controller:controller_0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datapath datapath:datapath_0 " "Elaborating entity \"datapath\" for hierarchy \"datapath:datapath_0\"" { } { { "../../Project/Components/microcontroller.vhd" "datapath_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/microcontroller.vhd" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809795919 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "program_counter datapath:datapath_0\|program_counter:program_counter_0 " "Elaborating entity \"program_counter\" for hierarchy \"datapath:datapath_0\|program_counter:program_counter_0\"" { } { { "../../Project/Components/datapath.vhd" "program_counter_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809795972 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2_1 datapath:datapath_0\|program_counter:program_counter_0\|mux_2_1:internal_mux " "Elaborating entity \"mux_2_1\" for hierarchy \"datapath:datapath_0\|program_counter:program_counter_0\|mux_2_1:internal_mux\"" { } { { "../../Project/Components/program_counter.vhd" "internal_mux" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/program_counter.vhd" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796003 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg32b datapath:datapath_0\|program_counter:program_counter_0\|reg32b:internal_register " "Elaborating entity \"reg32b\" for hierarchy \"datapath:datapath_0\|program_counter:program_counter_0\|reg32b:internal_register\"" { } { { "../../Project/Components/program_counter.vhd" "internal_register" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/program_counter.vhd" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796003 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "progmem_interface datapath:datapath_0\|progmem_interface:progmem_module_0 " "Elaborating entity \"progmem_interface\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\"" { } { { "../../Project/Components/datapath.vhd" "progmem_module_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796019 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "progmem datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0 " "Elaborating entity \"progmem\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\"" { } { { "../../Project/Components/progmem_interface.vhd" "progmem_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/progmem_interface.vhd" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796050 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\"" { } { { "progmem.vhd" "altsyncram_component" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/progmem.vhd" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796103 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\"" { } { { "progmem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/progmem.vhd" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796135 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component " "Instantiated megafunction \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK1 " "Parameter \"byteena_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV GX " "Parameter \"intended_device_family\" = \"Cyclone IV GX\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK1 " "Parameter \"indata_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file progmem.mif " "Parameter \"init_file\" = \"progmem.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 8192 " "Parameter \"maximum_depth\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 65536 " "Parameter \"numwords_a\" = \"65536\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 0 " "Parameter \"numwords_b\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK1 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 1 " "Parameter \"width_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 1 " "Parameter \"widthad_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK1 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809796135 ""} } { { "progmem.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/progmem.vhd" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1565809796135 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5gs3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_5gs3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5gs3 " "Found entity 1: altsyncram_5gs3" { } { { "db/altsyncram_5gs3.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/altsyncram_5gs3.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809796219 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796219 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5gs3 datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated " "Elaborating entity \"altsyncram_5gs3\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/programs/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796219 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_eca.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_eca.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_eca " "Found entity 1: decode_eca" { } { { "db/decode_eca.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/decode_eca.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809796273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796273 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_eca datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated\|decode_eca:rden_decode " "Elaborating entity \"decode_eca\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated\|decode_eca:rden_decode\"" { } { { "db/altsyncram_5gs3.tdf" "rden_decode" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/altsyncram_5gs3.tdf" 39 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796273 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_isb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_isb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_isb " "Found entity 1: mux_isb" { } { { "db/mux_isb.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/mux_isb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809796335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796335 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_isb datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated\|mux_isb:mux2 " "Elaborating entity \"mux_isb\" for hierarchy \"datapath:datapath_0\|progmem_interface:progmem_module_0\|progmem:progmem_0\|altsyncram:altsyncram_component\|altsyncram_5gs3:auto_generated\|mux_isb:mux2\"" { } { { "db/altsyncram_5gs3.tdf" "mux2" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/altsyncram_5gs3.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796335 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IF_ID_DIV datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR " "Elaborating entity \"IF_ID_DIV\" for hierarchy \"datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\"" { } { { "../../Project/Components/datapath.vhd" "IF_ID_PLR" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 131 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796357 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3_1 datapath:datapath_0\|mux_3_1:mux_0 " "Elaborating entity \"mux_3_1\" for hierarchy \"datapath:datapath_0\|mux_3_1:mux_0\"" { } { { "../../Project/Components/datapath.vhd" "mux_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 133 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796404 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file datapath:datapath_0\|register_file:register_file_0 " "Elaborating entity \"register_file\" for hierarchy \"datapath:datapath_0\|register_file:register_file_0\"" { } { { "../../Project/Components/datapath.vhd" "register_file_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796404 ""}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "write_control register_file.vhd(60) " "VHDL Process Statement warning at register_file.vhd(60): signal \"write_control\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "../../Project/Components/register_file.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/register_file.vhd" 60 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1565809796404 "|microcontroller|datapath:datapath_0|register_file:register_file_0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg32b_falling_edge datapath:datapath_0\|register_file:register_file_0\|reg32b_falling_edge:reg_x0 " "Elaborating entity \"reg32b_falling_edge\" for hierarchy \"datapath:datapath_0\|register_file:register_file_0\|reg32b_falling_edge:reg_x0\"" { } { { "../../Project/Components/register_file.vhd" "reg_x0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/register_file.vhd" 132 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796504 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_32_1 datapath:datapath_0\|register_file:register_file_0\|mux_32_1:output_1_mux " "Elaborating entity \"mux_32_1\" for hierarchy \"datapath:datapath_0\|register_file:register_file_0\|mux_32_1:output_1_mux\"" { } { { "../../Project/Components/register_file.vhd" "output_1_mux" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/register_file.vhd" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796536 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ID_EX_DIV datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR " "Elaborating entity \"ID_EX_DIV\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\"" { } { { "../../Project/Components/datapath.vhd" "ID_EX_PLR" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796558 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg4b datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg4b:ALU_operation_reg " "Elaborating entity \"reg4b\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg4b:ALU_operation_reg\"" { } { { "../../Project/Components/ID_EX_DIV.vhd" "ALU_operation_reg" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 133 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796589 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg1b datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg1b:ALU_branch_reg " "Elaborating entity \"reg1b\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg1b:ALU_branch_reg\"" { } { { "../../Project/Components/ID_EX_DIV.vhd" "ALU_branch_reg" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796589 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg3b datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg3b:ALU_branch_control_reg " "Elaborating entity \"reg3b\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg3b:ALU_branch_control_reg\"" { } { { "../../Project/Components/ID_EX_DIV.vhd" "ALU_branch_control_reg" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796589 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg2b datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg2b:mux0_sel_reg " "Elaborating entity \"reg2b\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg2b:mux0_sel_reg\"" { } { { "../../Project/Components/ID_EX_DIV.vhd" "mux0_sel_reg" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796589 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg5b datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg5b:reg_file_write_address_reg " "Elaborating entity \"reg5b\" for hierarchy \"datapath:datapath_0\|ID_EX_DIV:ID_EX_PLR\|reg5b:reg_file_write_address_reg\"" { } { { "../../Project/Components/ID_EX_DIV.vhd" "reg_file_write_address_reg" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ID_EX_DIV.vhd" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796605 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "forwarding_unit datapath:datapath_0\|forwarding_unit:FU_0 " "Elaborating entity \"forwarding_unit\" for hierarchy \"datapath:datapath_0\|forwarding_unit:FU_0\"" { } { { "../../Project/Components/datapath.vhd" "FU_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796620 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_5_1 datapath:datapath_0\|mux_5_1:forward_mux_0 " "Elaborating entity \"mux_5_1\" for hierarchy \"datapath:datapath_0\|mux_5_1:forward_mux_0\"" { } { { "../../Project/Components/datapath.vhd" "forward_mux_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 139 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU datapath:datapath_0\|ALU:ALU_0 " "Elaborating entity \"ALU\" for hierarchy \"datapath:datapath_0\|ALU:ALU_0\"" { } { { "../../Project/Components/datapath.vhd" "ALU_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 143 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 ""}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ALU_output ALU.vhd(21) " "VHDL Process Statement warning at ALU.vhd(21): inferring latch(es) for signal or variable \"ALU_output\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[0\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[0\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[1\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[1\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[2\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[2\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[3\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[3\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[4\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[4\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[5\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[5\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[6\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[6\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[7\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[7\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[8\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[8\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[9\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[9\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[10\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[10\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[11\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[11\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[12\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[12\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[13\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[13\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[14\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[14\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[15\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[15\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[16\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[16\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[17\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[17\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[18\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[18\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[19\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[19\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[20\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[20\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[21\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[21\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[22\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[22\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[23\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[23\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[24\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[24\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[25\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[25\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[26\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[26\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[27\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[27\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[28\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[28\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[29\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[29\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[30\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[30\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALU_output\[31\] ALU.vhd(21) " "Inferred latch for \"ALU_output\[31\]\" at ALU.vhd(21)" { } { { "../../Project/Components/ALU.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/ALU.vhd" 21 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 "|microcontroller|datapath:datapath_0|ALU:ALU_0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jump_target_unit datapath:datapath_0\|jump_target_unit:JTU_0 " "Elaborating entity \"jump_target_unit\" for hierarchy \"datapath:datapath_0\|jump_target_unit:JTU_0\"" { } { { "../../Project/Components/datapath.vhd" "JTU_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796658 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder datapath:datapath_0\|jump_target_unit:JTU_0\|adder:internal_adder " "Elaborating entity \"adder\" for hierarchy \"datapath:datapath_0\|jump_target_unit:JTU_0\|adder:internal_adder\"" { } { { "../../Project/Components/jump_target_unit.vhd" "internal_adder" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/jump_target_unit.vhd" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796689 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EX_MEM_DIV datapath:datapath_0\|EX_MEM_DIV:EX_MEM_PLR " "Elaborating entity \"EX_MEM_DIV\" for hierarchy \"datapath:datapath_0\|EX_MEM_DIV:EX_MEM_PLR\"" { } { { "../../Project/Components/datapath.vhd" "EX_MEM_PLR" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796705 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "flushing_unit datapath:datapath_0\|flushing_unit:FLUSH " "Elaborating entity \"flushing_unit\" for hierarchy \"datapath:datapath_0\|flushing_unit:FLUSH\"" { } { { "../../Project/Components/datapath.vhd" "FLUSH" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796758 ""}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_flushing_output flushing_unit.vhd(19) " "VHDL Process Statement warning at flushing_unit.vhd(19): inferring latch(es) for signal or variable \"internal_flushing_output\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/flushing_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/flushing_unit.vhd" 19 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796758 "|microcontroller|datapath:datapath_0|flushing_unit:FLUSH"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_flushing_output flushing_unit.vhd(19) " "Inferred latch for \"internal_flushing_output\" at flushing_unit.vhd(19)" { } { { "../../Project/Components/flushing_unit.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/flushing_unit.vhd" 19 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796758 "|microcontroller|datapath:datapath_0|flushing_unit:FLUSH"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datamem_interface datapath:datapath_0\|datamem_interface:datamem_module_0 " "Elaborating entity \"datamem_interface\" for hierarchy \"datapath:datapath_0\|datamem_interface:datamem_module_0\"" { } { { "../../Project/Components/datapath.vhd" "datamem_module_0" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796774 ""}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "internal_load datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"internal_load\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "memory_input_3 datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"memory_input_3\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "memory_input_2 datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"memory_input_2\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "memory_input_1 datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"memory_input_1\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "memory_input_0 datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"memory_input_0\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "output_data datamem_interface.vhd(34) " "VHDL Process Statement warning at datamem_interface.vhd(34): inferring latch(es) for signal or variable \"output_data\", which holds its previous value in one or more paths through the process" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[0\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[1\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[2\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[3\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[4\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[4\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[5\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[5\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[6\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[6\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[7\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[7\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[8\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[8\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[9\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[9\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[10\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[10\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[11\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[11\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[12\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[12\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[13\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[13\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[14\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[14\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[15\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[15\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[16\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[16\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[17\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[17\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[18\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[18\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[19\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[19\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[20\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[20\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[21\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[21\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[22\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[22\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[23\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[23\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[24\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[24\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[25\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[25\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[26\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[26\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[27\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[27\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[28\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[28\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[29\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[29\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[30\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[30\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "output_data\[31\] datamem_interface.vhd(34) " "Inferred latch for \"output_data\[31\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[0\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[1\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[2\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[3\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[4\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[4\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[5\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[5\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[6\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[6\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_0\[7\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_0\[7\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[0\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[1\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[2\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[3\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[4\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[4\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[5\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[5\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[6\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[6\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_1\[7\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_1\[7\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[0\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[1\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[2\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[3\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[4\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[4\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[5\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[5\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[6\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[6\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_2\[7\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_2\[7\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[0\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796790 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[1\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[2\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[3\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[4\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[4\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[5\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[5\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[6\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[6\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "memory_input_3\[7\] datamem_interface.vhd(34) " "Inferred latch for \"memory_input_3\[7\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_load\[0\] datamem_interface.vhd(34) " "Inferred latch for \"internal_load\[0\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_load\[1\] datamem_interface.vhd(34) " "Inferred latch for \"internal_load\[1\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_load\[2\] datamem_interface.vhd(34) " "Inferred latch for \"internal_load\[2\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "internal_load\[3\] datamem_interface.vhd(34) " "Inferred latch for \"internal_load\[3\]\" at datamem_interface.vhd(34)" { } { { "../../Project/Components/datamem_interface.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 34 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809796805 "|microcontroller|datapath:datapath_0|datamem_interface:datamem_module_0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datamem datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3 " "Elaborating entity \"datamem\" for hierarchy \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3\"" { } { { "../../Project/Components/datamem_interface.vhd" "datamem_3" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datamem_interface.vhd" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796836 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MEM_WB_DIV datapath:datapath_0\|MEM_WB_DIV:MEM_WB_PLR " "Elaborating entity \"MEM_WB_DIV\" for hierarchy \"datapath:datapath_0\|MEM_WB_DIV:MEM_WB_PLR\"" { } { { "../../Project/Components/datapath.vhd" "MEM_WB_PLR" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/datapath.vhd" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809796975 ""}
{ "Warning" "WINFER_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|RAM_rtl_0 " "Inferred dual-clock RAM node \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|RAM_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "Inferred dual-clock RAM node \"%1!s!\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1565809798124 ""}
{ "Warning" "WINFER_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_2\|RAM_rtl_0 " "Inferred dual-clock RAM node \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_2\|RAM_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "Inferred dual-clock RAM node \"%1!s!\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1565809798124 ""}
{ "Warning" "WINFER_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_1\|RAM_rtl_0 " "Inferred dual-clock RAM node \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_1\|RAM_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "Inferred dual-clock RAM node \"%1!s!\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1565809798124 ""}
{ "Warning" "WINFER_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3\|RAM_rtl_0 " "Inferred dual-clock RAM node \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3\|RAM_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "Inferred dual-clock RAM node \"%1!s!\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1565809798124 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|RAM_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|RAM_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 16 " "Parameter WIDTHAD_A set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 65536 " "Parameter NUMWORDS_A set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 16 " "Parameter WIDTHAD_B set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 65536 " "Parameter NUMWORDS_B set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK1 " "Parameter ADDRESS_REG_B set to CLOCK1" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_2\|RAM_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_2\|RAM_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 16 " "Parameter WIDTHAD_A set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 65536 " "Parameter NUMWORDS_A set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 16 " "Parameter WIDTHAD_B set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 65536 " "Parameter NUMWORDS_B set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK1 " "Parameter ADDRESS_REG_B set to CLOCK1" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_1\|RAM_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_1\|RAM_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 16 " "Parameter WIDTHAD_A set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 65536 " "Parameter NUMWORDS_A set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 16 " "Parameter WIDTHAD_B set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 65536 " "Parameter NUMWORDS_B set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK1 " "Parameter ADDRESS_REG_B set to CLOCK1" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3\|RAM_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_3\|RAM_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 16 " "Parameter WIDTHAD_A set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 65536 " "Parameter NUMWORDS_A set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 16 " "Parameter WIDTHAD_B set to 16" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 65536 " "Parameter NUMWORDS_B set to 65536" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK1 " "Parameter ADDRESS_REG_B set to CLOCK1" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1565809799929 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1565809799929 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1565809799929 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|altsyncram:RAM_rtl_0 " "Elaborated megafunction instantiation \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|altsyncram:RAM_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809799961 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|altsyncram:RAM_rtl_0 " "Instantiated megafunction \"datapath:datapath_0\|datamem_interface:datamem_module_0\|datamem:datamem_0\|altsyncram:RAM_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 16 " "Parameter \"WIDTHAD_A\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 65536 " "Parameter \"NUMWORDS_A\" = \"65536\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 16 " "Parameter \"WIDTHAD_B\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 65536 " "Parameter \"NUMWORDS_B\" = \"65536\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809799961 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1565809799961 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0ed1 " "Found entity 1: altsyncram_0ed1" { } { { "db/altsyncram_0ed1.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/altsyncram_0ed1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809800030 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809800030 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_l0b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_l0b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_l0b " "Found entity 1: decode_l0b" { } { { "db/decode_l0b.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/decode_l0b.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809800077 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809800077 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_5rb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_5rb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_5rb " "Found entity 1: mux_5rb" { } { { "db/mux_5rb.tdf" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/db/mux_5rb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1565809800130 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809800130 ""}
{ "Info" "IMLS_MLS_DUP_LATCH_INFO_HDR" "" "Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IMLS_MLS_DUP_LATCH_INFO" "controller:controller_0\|internal_jump_flag controller:controller_0\|internal_mux0_sel\[1\] " "Duplicate LATCH primitive \"controller:controller_0\|internal_jump_flag\" merged with LATCH primitive \"controller:controller_0\|internal_mux0_sel\[1\]\"" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13026 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "Design Software" 0 -1 1565809800985 ""} } { } 0 13025 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "Analysis & Synthesis" 0 -1 1565809800985 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write " "Latch controller:controller_0\|internal_reg_file_write has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_0\[0\] " "Latch controller:controller_0\|internal_reg_file_read_address_0\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_0\[1\] " "Latch controller:controller_0\|internal_reg_file_read_address_0\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_0\[2\] " "Latch controller:controller_0\|internal_reg_file_read_address_0\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_0\[3\] " "Latch controller:controller_0\|internal_reg_file_read_address_0\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_0\[4\] " "Latch controller:controller_0\|internal_reg_file_read_address_0\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_1\[0\] " "Latch controller:controller_0\|internal_reg_file_read_address_1\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_1\[1\] " "Latch controller:controller_0\|internal_reg_file_read_address_1\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_1\[2\] " "Latch controller:controller_0\|internal_reg_file_read_address_1\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_1\[3\] " "Latch controller:controller_0\|internal_reg_file_read_address_1\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_read_address_1\[4\] " "Latch controller:controller_0\|internal_reg_file_read_address_1\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_mux0_sel\[0\] " "Latch controller:controller_0\|internal_mux0_sel\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LOAD_1918 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LOAD_1918" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_mux0_sel\[1\] " "Latch controller:controller_0\|internal_mux0_sel\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.JAL_1846 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.JAL_1846" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[0\] " "Latch controller:controller_0\|internal_immediate\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[1\] " "Latch controller:controller_0\|internal_immediate\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[2\] " "Latch controller:controller_0\|internal_immediate\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[3\] " "Latch controller:controller_0\|internal_immediate\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[4\] " "Latch controller:controller_0\|internal_immediate\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[5\] " "Latch controller:controller_0\|internal_immediate\[5\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[6\] " "Latch controller:controller_0\|internal_immediate\[6\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[7\] " "Latch controller:controller_0\|internal_immediate\[7\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[8\] " "Latch controller:controller_0\|internal_immediate\[8\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[9\] " "Latch controller:controller_0\|internal_immediate\[9\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[10\] " "Latch controller:controller_0\|internal_immediate\[10\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[11\] " "Latch controller:controller_0\|internal_immediate\[11\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[12\] " "Latch controller:controller_0\|internal_immediate\[12\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[13\] " "Latch controller:controller_0\|internal_immediate\[13\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[14\] " "Latch controller:controller_0\|internal_immediate\[14\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[15\] " "Latch controller:controller_0\|internal_immediate\[15\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[16\] " "Latch controller:controller_0\|internal_immediate\[16\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[17\] " "Latch controller:controller_0\|internal_immediate\[17\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[18\] " "Latch controller:controller_0\|internal_immediate\[18\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[19\] " "Latch controller:controller_0\|internal_immediate\[19\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[20\] " "Latch controller:controller_0\|internal_immediate\[20\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[21\] " "Latch controller:controller_0\|internal_immediate\[21\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[22\] " "Latch controller:controller_0\|internal_immediate\[22\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[23\] " "Latch controller:controller_0\|internal_immediate\[23\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[24\] " "Latch controller:controller_0\|internal_immediate\[24\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[25\] " "Latch controller:controller_0\|internal_immediate\[25\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[26\] " "Latch controller:controller_0\|internal_immediate\[26\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[27\] " "Latch controller:controller_0\|internal_immediate\[27\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[28\] " "Latch controller:controller_0\|internal_immediate\[28\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[29\] " "Latch controller:controller_0\|internal_immediate\[29\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[30\] " "Latch controller:controller_0\|internal_immediate\[30\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_immediate\[31\] " "Latch controller:controller_0\|internal_immediate\[31\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_IMM_1840" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_operation\[0\] " "Latch controller:controller_0\|internal_ALU_operation\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_operation\[1\] " "Latch controller:controller_0\|internal_ALU_operation\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_operation\[2\] " "Latch controller:controller_0\|internal_ALU_operation\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_operation\[3\] " "Latch controller:controller_0\|internal_ALU_operation\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.OP_1834 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.OP_1834" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.LUI_1810 " "Latch controller:controller_0\|decoded_cluster.LUI_1810 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.AUIPC_1816 " "Latch controller:controller_0\|decoded_cluster.AUIPC_1816 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.OP_1834 " "Latch controller:controller_0\|decoded_cluster.OP_1834 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.OP_IMM_1840 " "Latch controller:controller_0\|decoded_cluster.OP_IMM_1840 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.JAL_1846 " "Latch controller:controller_0\|decoded_cluster.JAL_1846 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.JALR_1876 " "Latch controller:controller_0\|decoded_cluster.JALR_1876 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.LOAD_1918 " "Latch controller:controller_0\|decoded_cluster.LOAD_1918 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.BRANCH_1900 " "Latch controller:controller_0\|decoded_cluster.BRANCH_1900 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.STORE_1912 " "Latch controller:controller_0\|decoded_cluster.STORE_1912 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_cluster.INVALID_1924 " "Latch controller:controller_0\|decoded_cluster.INVALID_1924 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_mux1_sel " "Latch controller:controller_0\|internal_mux1_sel has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.SRAI_1630 " "Latch controller:controller_0\|decoded_opcode.SRAI_1630 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.SRLI_1636 " "Latch controller:controller_0\|decoded_opcode.SRLI_1636 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.SLLI_1642 " "Latch controller:controller_0\|decoded_opcode.SLLI_1642 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.ANDI_1648 " "Latch controller:controller_0\|decoded_opcode.ANDI_1648 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801005 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801005 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.ORI_1654 " "Latch controller:controller_0\|decoded_opcode.ORI_1654 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.XORI_1660 " "Latch controller:controller_0\|decoded_opcode.XORI_1660 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.SLTIU_1666 " "Latch controller:controller_0\|decoded_opcode.SLTIU_1666 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.SLTI_1672 " "Latch controller:controller_0\|decoded_opcode.SLTI_1672 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|decoded_opcode.ADDI_1678 " "Latch controller:controller_0\|decoded_opcode.ADDI_1678 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\] " "Ports D and ENA on the latch are fed by the same signal datapath:datapath_0\|IF_ID_DIV:IF_ID_PLR\|reg32b:instruction_data_reg\|internal_value\[4\]" { } { { "../../Project/Components/reg32b.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/reg32b.vhd" 17 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_JTU_mux_sel " "Latch controller:controller_0\|internal_JTU_mux_sel has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.JALR_1876 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.JALR_1876" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_branch " "Latch controller:controller_0\|internal_ALU_branch has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_branch_control\[1\] " "Latch controller:controller_0\|internal_ALU_branch_control\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_branch_control\[0\] " "Latch controller:controller_0\|internal_ALU_branch_control\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_ALU_branch_control\[2\] " "Latch controller:controller_0\|internal_ALU_branch_control\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.BRANCH_1900 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.BRANCH_1900" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write_address\[0\] " "Latch controller:controller_0\|internal_reg_file_write_address\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write_address\[1\] " "Latch controller:controller_0\|internal_reg_file_write_address\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write_address\[2\] " "Latch controller:controller_0\|internal_reg_file_write_address\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write_address\[3\] " "Latch controller:controller_0\|internal_reg_file_write_address\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_reg_file_write_address\[4\] " "Latch controller:controller_0\|internal_reg_file_write_address\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.LUI_1810 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.LUI_1810" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_data_format\[1\] " "Latch controller:controller_0\|internal_data_format\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.STORE_1912 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.STORE_1912" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801013 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801013 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_data_format\[0\] " "Latch controller:controller_0\|internal_data_format\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.STORE_1912 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.STORE_1912" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801015 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801015 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_data_format\[2\] " "Latch controller:controller_0\|internal_data_format\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.STORE_1912 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.STORE_1912" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801015 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801015 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "controller:controller_0\|internal_datamem_write " "Latch controller:controller_0\|internal_datamem_write has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA controller:controller_0\|decoded_cluster.STORE_1912 " "Ports D and ENA on the latch are fed by the same signal controller:controller_0\|decoded_cluster.STORE_1912" { } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 0 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1565809801015 ""} } { { "../../Project/Components/controller.vhd" "" { Text "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Project/Components/controller.vhd" 68 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1565809801015 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1565809803633 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1565809812747 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1565809812747 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "5881 " "Implemented 5881 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1565809813186 ""} { "Info" "ICUT_CUT_TM_OPINS" "521 " "Implemented 521 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1565809813186 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4846 " "Implemented 4846 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1565809813186 ""} { "Info" "ICUT_CUT_TM_RAMS" "512 " "Implemented 512 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1565809813186 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1565809813186 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 197 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 197 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4919 " "Peak virtual memory: 4919 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1565809813255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 14 16:10:13 2019 " "Processing ended: Wed Aug 14 16:10:13 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1565809813255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1565809813255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1565809813255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1565809813255 ""}
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