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130 lines
6.3 KiB
Text
130 lines
6.3 KiB
Text
# Reading D:/Programs/Altera/Quartus/modelsim_ase/tcl/vsim/pref.tcl
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# do riscv_microcontroller_run_msim_rtl_vhdl.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Copying D:\Programs\Altera\Quartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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# ** Warning: Copied D:\Programs\Altera\Quartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
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# Updated modelsim.ini.
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#
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg32b_falling_edge
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# -- Compiling architecture description of reg32b_falling_edge
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg4b
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# -- Compiling architecture description of reg4b
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg3b
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# -- Compiling architecture description of reg3b
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg2b
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# -- Compiling architecture description of reg2b
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg1b
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# -- Compiling architecture description of reg1b
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity progmem
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# -- Compiling architecture SYN of progmem
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity datamem
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# -- Compiling architecture SYN of datamem
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity reg32b
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# -- Compiling architecture description of reg32b
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package NUMERIC_STD
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# -- Compiling entity program_counter
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# -- Compiling architecture behavioral of program_counter
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# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
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# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity mux_32_1
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# -- Compiling architecture behavioral of mux_32_1
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# ** Error: E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd(15): (vcom-1339) Selected signal assignment choices cover only 32 out of 59049 cases.
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#
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# ** Error: E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd(49): VHDL Compiler exiting
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# ** Error: D:/Programs/Altera/Quartus/modelsim_ase/win32aloem/vcom failed.
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# Error in macro ./riscv_microcontroller_run_msim_rtl_vhdl.do line 17
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# D:/Programs/Altera/Quartus/modelsim_ase/win32aloem/vcom failed.
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# while executing
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# "vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}"
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do E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.do
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# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
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# -- Compiling module microcontroller_vlg_sample_tst
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# -- Compiling module microcontroller_vlg_check_tst
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# -- Compiling module microcontroller_vlg_vec_tst
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#
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# Top level modules:
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# microcontroller_vlg_vec_tst
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# vsim -L cycloneiv_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.microcontroller_vlg_vec_tst
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# Loading work.microcontroller_vlg_vec_tst
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# ** Error: (vsim-3033) E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.vt(9883): Instantiation of 'microcontroller' failed. The design unit was not found.
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#
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# Region: /microcontroller_vlg_vec_tst
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# Searched libraries:
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# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/cycloneiv
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# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/altera
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# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/altera_mf
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# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/220model
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# D:/Programs/Altera/Quartus/modelsim_ase/altera/vhdl/sgate
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# E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/rtl_work
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# Loading work.microcontroller_vlg_sample_tst
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# Loading work.microcontroller_vlg_check_tst
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# Error loading design
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# Error: Error loading design
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# Pausing macro execution
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# MACRO E:\Documents-bkp\UFRN\TCC\Quartus\riscv_microcontroller\simulation\modelsim\microcontroller.vwf.do PAUSED at line 2
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vlib tcc
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vmap tcc tcc
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# Modifying modelsim.ini
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vmap -del tcc
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# Removing reference to logical library tcc
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# Modifying modelsim.ini
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vsim rtl_work.microcontroller_vlg_check_tst
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# vsim rtl_work.microcontroller_vlg_check_tst
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# Loading work.microcontroller_vlg_check_tst
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# Load canceled
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vsim rtl_work.microcontroller_vlg_check_tst
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# vsim rtl_work.microcontroller_vlg_check_tst
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# Loading rtl_work.microcontroller_vlg_check_tst
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