maestro/Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller.vo

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"

// DATE "07/14/2019 23:22:04"

// 
// Device: Altera EP4CGX150CF23C7 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module microcontroller (
	clock,
	reset,
	debug_pc_output,
	debug_regfile_x31_output,
	debug_regfile_x1_output,
	debug_regfile_x2_output,
	debug_ALU_output,
	debug_regfile_write,
	debug_ALU_input_0,
	debug_ALU_input_1,
	debug_reg_file_read_address_0,
	debug_reg_file_read_address_1,
	debug_mux0_sel,
	debug_immediate,
	debug_ALU_operation,
	debug_forward_mux_0,
	debug_forward_mux_1,
	debug_reg_file_read_address_0_ID_EXE,
	debug_reg_file_write_address_EX_MEM,
	debug_mux0_sel_MEM_WB,
	debug_reg_file_write_MEM_WB,
	debug_reg_file_write_address_MEM_WB,
	debug_ALU_output_MEM_WB,
	debug_ALU_output_EX_MEM,
	debug_register_file_output_0,
	debug_register_file_output_1,
	debug_register_file_output_0_ID_EX,
	debug_register_file_output_1_ID_EX,
	debug_instruction);
input 	clock;
input 	reset;
output 	[31:0] debug_pc_output;
output 	[31:0] debug_regfile_x31_output;
output 	[31:0] debug_regfile_x1_output;
output 	[31:0] debug_regfile_x2_output;
output 	[31:0] debug_ALU_output;
output 	debug_regfile_write;
output 	[31:0] debug_ALU_input_0;
output 	[31:0] debug_ALU_input_1;
output 	[4:0] debug_reg_file_read_address_0;
output 	[4:0] debug_reg_file_read_address_1;
output 	[1:0] debug_mux0_sel;
output 	[31:0] debug_immediate;
output 	[3:0] debug_ALU_operation;
output 	[2:0] debug_forward_mux_0;
output 	[2:0] debug_forward_mux_1;
output 	[4:0] debug_reg_file_read_address_0_ID_EXE;
output 	[4:0] debug_reg_file_write_address_EX_MEM;
output 	[1:0] debug_mux0_sel_MEM_WB;
output 	debug_reg_file_write_MEM_WB;
output 	[4:0] debug_reg_file_write_address_MEM_WB;
output 	[31:0] debug_ALU_output_MEM_WB;
output 	[31:0] debug_ALU_output_EX_MEM;
output 	[31:0] debug_register_file_output_0;
output 	[31:0] debug_register_file_output_1;
output 	[31:0] debug_register_file_output_0_ID_EX;
output 	[31:0] debug_register_file_output_1_ID_EX;
output 	[31:0] debug_instruction;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \datapath_0|register_file_0|internal_reg_load[3]~0_combout ;
wire \datapath_0|FU_0|Equal2~0_combout ;
wire \datapath_0|forward_mux_0|Mux31~2_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux31~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux30~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux29~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux28~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux27~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux26~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux25~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux24~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux23~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux22~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux21~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux20~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux19~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux18~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux17~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux16~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux15~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux14~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux13~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux12~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux11~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux10~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux9~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux8~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux7~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux6~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux5~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux4~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux3~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux2~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux1~0_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux0~0_combout ;
wire \datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ;
wire \datapath_0|JTU_0|internal_mux|output_0[0]~0_combout ;
wire \datapath_0|ALU_0|Add0~0_combout ;
wire \datapath_0|ALU_0|Add0~1_combout ;
wire \datapath_0|ALU_0|Add0~2_combout ;
wire \datapath_0|ALU_0|Add0~3_combout ;
wire \datapath_0|ALU_0|Add0~4_combout ;
wire \datapath_0|ALU_0|Add0~5_combout ;
wire \datapath_0|ALU_0|Add0~6_combout ;
wire \datapath_0|ALU_0|Add0~7_combout ;
wire \datapath_0|ALU_0|Add0~8_combout ;
wire \datapath_0|ALU_0|Add0~9_combout ;
wire \datapath_0|ALU_0|Add0~10_combout ;
wire \datapath_0|ALU_0|Add0~11_combout ;
wire \datapath_0|ALU_0|Add0~12_combout ;
wire \datapath_0|ALU_0|Add0~13_combout ;
wire \datapath_0|ALU_0|Add0~14_combout ;
wire \datapath_0|ALU_0|Add0~15_combout ;
wire \datapath_0|ALU_0|Add0~16_combout ;
wire \datapath_0|ALU_0|Add0~17_combout ;
wire \datapath_0|ALU_0|Add0~18_combout ;
wire \datapath_0|ALU_0|Add0~19_combout ;
wire \datapath_0|ALU_0|Add0~20_combout ;
wire \datapath_0|ALU_0|Add0~21_combout ;
wire \datapath_0|ALU_0|Add0~22_combout ;
wire \datapath_0|ALU_0|Add0~23_combout ;
wire \datapath_0|ALU_0|Add0~24_combout ;
wire \datapath_0|ALU_0|Add0~25_combout ;
wire \datapath_0|ALU_0|Add0~26_combout ;
wire \datapath_0|ALU_0|Add0~27_combout ;
wire \datapath_0|ALU_0|Add0~28_combout ;
wire \datapath_0|ALU_0|Add0~29_combout ;
wire \datapath_0|ALU_0|Add0~30_combout ;
wire \datapath_0|ALU_0|Add0~31_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~2_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[1]~1_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[2]~2_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[3]~3_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[4]~4_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[5]~5_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[6]~6_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[7]~7_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[8]~8_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[9]~9_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[10]~10_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[11]~11_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[12]~12_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[13]~13_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[14]~14_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[15]~15_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[16]~16_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[17]~17_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[18]~18_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[19]~19_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[20]~20_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[21]~21_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[22]~22_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[23]~23_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[24]~24_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[25]~25_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[26]~26_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[27]~27_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[28]~28_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[29]~29_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[30]~30_combout ;
wire \datapath_0|JTU_0|internal_mux|output_0[31]~31_combout ;
wire \datapath_0|mux_0|Mux31~0_combout ;
wire \datapath_0|mux_0|Mux30~0_combout ;
wire \datapath_0|mux_0|Mux29~0_combout ;
wire \datapath_0|mux_0|Mux28~0_combout ;
wire \datapath_0|mux_0|Mux27~0_combout ;
wire \datapath_0|mux_0|Mux26~0_combout ;
wire \datapath_0|mux_0|Mux25~0_combout ;
wire \datapath_0|mux_0|Mux24~0_combout ;
wire \datapath_0|mux_0|Mux23~0_combout ;
wire \datapath_0|mux_0|Mux22~0_combout ;
wire \datapath_0|mux_0|Mux21~0_combout ;
wire \datapath_0|mux_0|Mux20~0_combout ;
wire \datapath_0|mux_0|Mux19~0_combout ;
wire \datapath_0|mux_0|Mux18~0_combout ;
wire \datapath_0|mux_0|Mux17~0_combout ;
wire \datapath_0|mux_0|Mux16~0_combout ;
wire \datapath_0|mux_0|Mux15~0_combout ;
wire \datapath_0|mux_0|Mux14~0_combout ;
wire \datapath_0|mux_0|Mux13~0_combout ;
wire \datapath_0|mux_0|Mux12~0_combout ;
wire \datapath_0|mux_0|Mux11~0_combout ;
wire \datapath_0|mux_0|Mux10~0_combout ;
wire \datapath_0|mux_0|Mux9~0_combout ;
wire \datapath_0|mux_0|Mux8~0_combout ;
wire \datapath_0|mux_0|Mux7~0_combout ;
wire \datapath_0|mux_0|Mux6~0_combout ;
wire \datapath_0|mux_0|Mux5~0_combout ;
wire \datapath_0|mux_0|Mux4~0_combout ;
wire \datapath_0|mux_0|Mux3~0_combout ;
wire \datapath_0|mux_0|Mux2~0_combout ;
wire \datapath_0|mux_0|Mux1~0_combout ;
wire \datapath_0|mux_0|Mux0~0_combout ;
wire \datapath_0|datamem_module_0|output_data~0_combout ;
wire \datapath_0|datamem_module_0|output_data~1_combout ;
wire \datapath_0|datamem_module_0|output_data~2_combout ;
wire \datapath_0|datamem_module_0|output_data~3_combout ;
wire \datapath_0|datamem_module_0|output_data~4_combout ;
wire \datapath_0|datamem_module_0|output_data~5_combout ;
wire \datapath_0|datamem_module_0|output_data~6_combout ;
wire \datapath_0|datamem_module_0|output_data~7_combout ;
wire \datapath_0|datamem_module_0|output_data~8_combout ;
wire \datapath_0|datamem_module_0|output_data~9_combout ;
wire \datapath_0|datamem_module_0|output_data~10_combout ;
wire \datapath_0|datamem_module_0|output_data~11_combout ;
wire \datapath_0|datamem_module_0|output_data~12_combout ;
wire \datapath_0|datamem_module_0|output_data~13_combout ;
wire \datapath_0|datamem_module_0|output_data~14_combout ;
wire \datapath_0|datamem_module_0|output_data~15_combout ;
wire \datapath_0|datamem_module_0|output_data~16_combout ;
wire \datapath_0|datamem_module_0|output_data~17_combout ;
wire \datapath_0|datamem_module_0|output_data~18_combout ;
wire \datapath_0|datamem_module_0|output_data~19_combout ;
wire \datapath_0|datamem_module_0|output_data~20_combout ;
wire \datapath_0|datamem_module_0|output_data~21_combout ;
wire \datapath_0|datamem_module_0|output_data~22_combout ;
wire \datapath_0|datamem_module_0|output_data~23_combout ;
wire \datapath_0|datamem_module_0|output_data~24_combout ;
wire \datapath_0|datamem_module_0|output_data~25_combout ;
wire \datapath_0|datamem_module_0|output_data~26_combout ;
wire \datapath_0|datamem_module_0|output_data~27_combout ;
wire \datapath_0|datamem_module_0|output_data~28_combout ;
wire \datapath_0|datamem_module_0|output_data~29_combout ;
wire \datapath_0|datamem_module_0|output_data~30_combout ;
wire \datapath_0|datamem_module_0|output_data~31_combout ;
wire \datapath_0|datamem_module_0|output_data~32_combout ;
wire \datapath_0|datamem_module_0|output_data~42_combout ;
wire \datapath_0|datamem_module_0|output_data~43_combout ;
wire \datapath_0|datamem_module_0|output_data~44_combout ;
wire \datapath_0|datamem_module_0|output_data~45_combout ;
wire \datapath_0|datamem_module_0|output_data~46_combout ;
wire \datapath_0|datamem_module_0|output_data~47_combout ;
wire \datapath_0|datamem_module_0|output_data~48_combout ;
wire \datapath_0|datamem_module_0|output_data~49_combout ;
wire \datapath_0|datamem_module_0|output_data~50_combout ;
wire \datapath_0|datamem_module_0|output_data~51_combout ;
wire \datapath_0|datamem_module_0|output_data~52_combout ;
wire \datapath_0|datamem_module_0|output_data~53_combout ;
wire \datapath_0|datamem_module_0|output_data~54_combout ;
wire \datapath_0|datamem_module_0|output_data~55_combout ;
wire \datapath_0|datamem_module_0|output_data~56_combout ;
wire \datapath_0|datamem_module_0|output_data~57_combout ;
wire \datapath_0|datamem_module_0|output_data~58_combout ;
wire \datapath_0|datamem_module_0|output_data~59_combout ;
wire \datapath_0|datamem_module_0|output_data~60_combout ;
wire \datapath_0|datamem_module_0|output_data~61_combout ;
wire \datapath_0|datamem_module_0|output_data~62_combout ;
wire \datapath_0|datamem_module_0|output_data~63_combout ;
wire \datapath_0|datamem_module_0|output_data~64_combout ;
wire \datapath_0|datamem_module_0|output_data~65_combout ;
wire \datapath_0|datamem_module_0|output_data~66_combout ;
wire \datapath_0|datamem_module_0|output_data~67_combout ;
wire \datapath_0|datamem_module_0|output_data~68_combout ;
wire \datapath_0|datamem_module_0|output_data~69_combout ;
wire \datapath_0|datamem_module_0|output_data~70_combout ;
wire \datapath_0|datamem_module_0|output_data~71_combout ;
wire \datapath_0|datamem_module_0|output_data~72_combout ;
wire \datapath_0|datamem_module_0|output_data~73_combout ;
wire \datapath_0|datamem_module_0|output_data~74_combout ;
wire \datapath_0|datamem_module_0|output_data~84_combout ;
wire \datapath_0|datamem_module_0|output_data~85_combout ;
wire \datapath_0|datamem_module_0|output_data~86_combout ;
wire \datapath_0|datamem_module_0|output_data~87_combout ;
wire \datapath_0|datamem_module_0|output_data~88_combout ;
wire \datapath_0|datamem_module_0|output_data~89_combout ;
wire \datapath_0|datamem_module_0|output_data~90_combout ;
wire \datapath_0|datamem_module_0|output_data~91_combout ;
wire \datapath_0|datamem_module_0|output_data~92_combout ;
wire \datapath_0|datamem_module_0|output_data~93_combout ;
wire \datapath_0|datamem_module_0|output_data~94_combout ;
wire \datapath_0|datamem_module_0|output_data~95_combout ;
wire \datapath_0|datamem_module_0|output_data~96_combout ;
wire \datapath_0|datamem_module_0|output_data~97_combout ;
wire \datapath_0|datamem_module_0|output_data~98_combout ;
wire \datapath_0|datamem_module_0|output_data~99_combout ;
wire \datapath_0|datamem_module_0|output_data~100_combout ;
wire \datapath_0|datamem_module_0|output_data~101_combout ;
wire \datapath_0|datamem_module_0|output_data~102_combout ;
wire \datapath_0|datamem_module_0|output_data~103_combout ;
wire \datapath_0|datamem_module_0|output_data~104_combout ;
wire \datapath_0|datamem_module_0|output_data~105_combout ;
wire \datapath_0|datamem_module_0|output_data~106_combout ;
wire \datapath_0|datamem_module_0|output_data~107_combout ;
wire \datapath_0|datamem_module_0|output_data~108_combout ;
wire \datapath_0|datamem_module_0|output_data~109_combout ;
wire \datapath_0|datamem_module_0|output_data~110_combout ;
wire \datapath_0|datamem_module_0|output_data~111_combout ;
wire \datapath_0|datamem_module_0|output_data~112_combout ;
wire \datapath_0|datamem_module_0|output_data~113_combout ;
wire \datapath_0|datamem_module_0|output_data~114_combout ;
wire \datapath_0|datamem_module_0|output_data~115_combout ;
wire \datapath_0|datamem_module_0|output_data~116_combout ;
wire \datapath_0|datamem_module_0|output_data~126_combout ;
wire \datapath_0|datamem_module_0|output_data~127_combout ;
wire \datapath_0|datamem_module_0|output_data~128_combout ;
wire \datapath_0|datamem_module_0|output_data~129_combout ;
wire \datapath_0|datamem_module_0|output_data~130_combout ;
wire \datapath_0|datamem_module_0|output_data~131_combout ;
wire \datapath_0|datamem_module_0|output_data~132_combout ;
wire \datapath_0|datamem_module_0|output_data~133_combout ;
wire \datapath_0|datamem_module_0|output_data~134_combout ;
wire \datapath_0|datamem_module_0|output_data~135_combout ;
wire \datapath_0|datamem_module_0|output_data~136_combout ;
wire \datapath_0|datamem_module_0|output_data~137_combout ;
wire \datapath_0|datamem_module_0|output_data~138_combout ;
wire \datapath_0|datamem_module_0|output_data~139_combout ;
wire \datapath_0|datamem_module_0|output_data~140_combout ;
wire \datapath_0|datamem_module_0|output_data~141_combout ;
wire \datapath_0|datamem_module_0|output_data~142_combout ;
wire \datapath_0|datamem_module_0|output_data~143_combout ;
wire \datapath_0|datamem_module_0|output_data~144_combout ;
wire \datapath_0|datamem_module_0|output_data~145_combout ;
wire \datapath_0|datamem_module_0|output_data~146_combout ;
wire \datapath_0|datamem_module_0|output_data~147_combout ;
wire \datapath_0|datamem_module_0|output_data~148_combout ;
wire \datapath_0|datamem_module_0|output_data~149_combout ;
wire \datapath_0|datamem_module_0|output_data~150_combout ;
wire \datapath_0|datamem_module_0|output_data~151_combout ;
wire \datapath_0|datamem_module_0|output_data~152_combout ;
wire \datapath_0|datamem_module_0|output_data~153_combout ;
wire \datapath_0|datamem_module_0|output_data~154_combout ;
wire \datapath_0|datamem_module_0|output_data~155_combout ;
wire \datapath_0|datamem_module_0|output_data~156_combout ;
wire \datapath_0|datamem_module_0|output_data~157_combout ;
wire \datapath_0|datamem_module_0|output_data~158_combout ;
wire \datapath_0|datamem_module_0|output_data~168_combout ;
wire \datapath_0|datamem_module_0|output_data~169_combout ;
wire \datapath_0|datamem_module_0|output_data~170_combout ;
wire \datapath_0|datamem_module_0|output_data~171_combout ;
wire \datapath_0|datamem_module_0|output_data~172_combout ;
wire \datapath_0|datamem_module_0|output_data~173_combout ;
wire \datapath_0|datamem_module_0|output_data~174_combout ;
wire \datapath_0|datamem_module_0|output_data~175_combout ;
wire \datapath_0|datamem_module_0|output_data~176_combout ;
wire \datapath_0|datamem_module_0|output_data~177_combout ;
wire \datapath_0|datamem_module_0|output_data~178_combout ;
wire \datapath_0|datamem_module_0|output_data~179_combout ;
wire \datapath_0|datamem_module_0|output_data~189_combout ;
wire \datapath_0|datamem_module_0|output_data~190_combout ;
wire \datapath_0|datamem_module_0|output_data~191_combout ;
wire \datapath_0|datamem_module_0|output_data~192_combout ;
wire \datapath_0|datamem_module_0|output_data~193_combout ;
wire \datapath_0|datamem_module_0|output_data~194_combout ;
wire \datapath_0|datamem_module_0|output_data~195_combout ;
wire \datapath_0|datamem_module_0|output_data~196_combout ;
wire \datapath_0|datamem_module_0|output_data~197_combout ;
wire \datapath_0|datamem_module_0|output_data~198_combout ;
wire \datapath_0|datamem_module_0|output_data~199_combout ;
wire \datapath_0|datamem_module_0|output_data~200_combout ;
wire \datapath_0|datamem_module_0|output_data~210_combout ;
wire \datapath_0|datamem_module_0|output_data~211_combout ;
wire \datapath_0|datamem_module_0|output_data~212_combout ;
wire \datapath_0|datamem_module_0|output_data~213_combout ;
wire \datapath_0|datamem_module_0|output_data~214_combout ;
wire \datapath_0|datamem_module_0|output_data~215_combout ;
wire \datapath_0|datamem_module_0|output_data~216_combout ;
wire \datapath_0|datamem_module_0|output_data~217_combout ;
wire \datapath_0|datamem_module_0|output_data~218_combout ;
wire \datapath_0|datamem_module_0|output_data~219_combout ;
wire \datapath_0|datamem_module_0|output_data~220_combout ;
wire \datapath_0|datamem_module_0|output_data~221_combout ;
wire \datapath_0|datamem_module_0|output_data~231_combout ;
wire \datapath_0|datamem_module_0|output_data~232_combout ;
wire \datapath_0|datamem_module_0|output_data~233_combout ;
wire \datapath_0|datamem_module_0|output_data~234_combout ;
wire \datapath_0|datamem_module_0|output_data~235_combout ;
wire \datapath_0|datamem_module_0|output_data~236_combout ;
wire \datapath_0|datamem_module_0|output_data~237_combout ;
wire \datapath_0|datamem_module_0|output_data~238_combout ;
wire \datapath_0|datamem_module_0|output_data~239_combout ;
wire \datapath_0|datamem_module_0|output_data~240_combout ;
wire \datapath_0|datamem_module_0|output_data~241_combout ;
wire \datapath_0|datamem_module_0|output_data~242_combout ;
wire \datapath_0|datamem_module_0|output_data~252_combout ;
wire \datapath_0|datamem_module_0|output_data~253_combout ;
wire \datapath_0|datamem_module_0|output_data~254_combout ;
wire \datapath_0|datamem_module_0|output_data~255_combout ;
wire \datapath_0|datamem_module_0|output_data~256_combout ;
wire \datapath_0|datamem_module_0|output_data~257_combout ;
wire \datapath_0|datamem_module_0|output_data~258_combout ;
wire \datapath_0|datamem_module_0|output_data~259_combout ;
wire \datapath_0|datamem_module_0|output_data~260_combout ;
wire \datapath_0|datamem_module_0|output_data~261_combout ;
wire \datapath_0|datamem_module_0|output_data~262_combout ;
wire \datapath_0|datamem_module_0|output_data~263_combout ;
wire \datapath_0|datamem_module_0|output_data~273_combout ;
wire \datapath_0|datamem_module_0|output_data~274_combout ;
wire \datapath_0|datamem_module_0|output_data~275_combout ;
wire \datapath_0|datamem_module_0|output_data~276_combout ;
wire \datapath_0|datamem_module_0|output_data~277_combout ;
wire \datapath_0|datamem_module_0|output_data~278_combout ;
wire \datapath_0|datamem_module_0|output_data~279_combout ;
wire \datapath_0|datamem_module_0|output_data~280_combout ;
wire \datapath_0|datamem_module_0|output_data~281_combout ;
wire \datapath_0|datamem_module_0|output_data~282_combout ;
wire \datapath_0|datamem_module_0|output_data~283_combout ;
wire \datapath_0|datamem_module_0|output_data~284_combout ;
wire \datapath_0|datamem_module_0|output_data~294_combout ;
wire \datapath_0|datamem_module_0|output_data~295_combout ;
wire \datapath_0|datamem_module_0|output_data~296_combout ;
wire \datapath_0|datamem_module_0|output_data~297_combout ;
wire \datapath_0|datamem_module_0|output_data~298_combout ;
wire \datapath_0|datamem_module_0|output_data~299_combout ;
wire \datapath_0|datamem_module_0|output_data~300_combout ;
wire \datapath_0|datamem_module_0|output_data~301_combout ;
wire \datapath_0|datamem_module_0|output_data~302_combout ;
wire \datapath_0|datamem_module_0|output_data~303_combout ;
wire \datapath_0|datamem_module_0|output_data~304_combout ;
wire \datapath_0|datamem_module_0|output_data~305_combout ;
wire \datapath_0|datamem_module_0|output_data~315_combout ;
wire \datapath_0|datamem_module_0|output_data~316_combout ;
wire \datapath_0|datamem_module_0|output_data~317_combout ;
wire \datapath_0|datamem_module_0|output_data~318_combout ;
wire \datapath_0|datamem_module_0|output_data~319_combout ;
wire \datapath_0|datamem_module_0|output_data~320_combout ;
wire \datapath_0|datamem_module_0|output_data~321_combout ;
wire \datapath_0|datamem_module_0|output_data~322_combout ;
wire \datapath_0|datamem_module_0|output_data~323_combout ;
wire \datapath_0|datamem_module_0|output_data~324_combout ;
wire \datapath_0|datamem_module_0|output_data~325_combout ;
wire \datapath_0|datamem_module_0|output_data~326_combout ;
wire \datapath_0|datamem_module_0|output_data~336_combout ;
wire \datapath_0|datamem_module_0|output_data~337_combout ;
wire \datapath_0|datamem_module_0|output_data~338_combout ;
wire \datapath_0|datamem_module_0|output_data~339_combout ;
wire \datapath_0|datamem_module_0|output_data~340_combout ;
wire \datapath_0|datamem_module_0|output_data~341_combout ;
wire \datapath_0|datamem_module_0|output_data~342_combout ;
wire \datapath_0|datamem_module_0|output_data~343_combout ;
wire \datapath_0|datamem_module_0|output_data~344_combout ;
wire \datapath_0|datamem_module_0|output_data~345_combout ;
wire \datapath_0|datamem_module_0|output_data~346_combout ;
wire \datapath_0|datamem_module_0|output_data~347_combout ;
wire \datapath_0|datamem_module_0|output_data~348_combout ;
wire \datapath_0|datamem_module_0|output_data~349_combout ;
wire \datapath_0|datamem_module_0|output_data~350_combout ;
wire \datapath_0|datamem_module_0|output_data~351_combout ;
wire \datapath_0|datamem_module_0|output_data~352_combout ;
wire \datapath_0|datamem_module_0|output_data~353_combout ;
wire \datapath_0|datamem_module_0|output_data~354_combout ;
wire \datapath_0|datamem_module_0|output_data~355_combout ;
wire \datapath_0|datamem_module_0|output_data~356_combout ;
wire \datapath_0|datamem_module_0|output_data~357_combout ;
wire \datapath_0|datamem_module_0|output_data~358_combout ;
wire \datapath_0|datamem_module_0|output_data~359_combout ;
wire \datapath_0|datamem_module_0|output_data~360_combout ;
wire \datapath_0|datamem_module_0|output_data~361_combout ;
wire \datapath_0|datamem_module_0|output_data~362_combout ;
wire \datapath_0|datamem_module_0|output_data~363_combout ;
wire \datapath_0|datamem_module_0|output_data~364_combout ;
wire \datapath_0|datamem_module_0|output_data~365_combout ;
wire \datapath_0|datamem_module_0|output_data~366_combout ;
wire \datapath_0|datamem_module_0|output_data~367_combout ;
wire \datapath_0|datamem_module_0|output_data~368_combout ;
wire \datapath_0|datamem_module_0|output_data~378_combout ;
wire \datapath_0|datamem_module_0|output_data~379_combout ;
wire \datapath_0|datamem_module_0|output_data~380_combout ;
wire \datapath_0|datamem_module_0|output_data~381_combout ;
wire \datapath_0|datamem_module_0|output_data~382_combout ;
wire \datapath_0|datamem_module_0|output_data~383_combout ;
wire \datapath_0|datamem_module_0|output_data~384_combout ;
wire \datapath_0|datamem_module_0|output_data~385_combout ;
wire \datapath_0|datamem_module_0|output_data~386_combout ;
wire \datapath_0|datamem_module_0|output_data~387_combout ;
wire \datapath_0|datamem_module_0|output_data~388_combout ;
wire \datapath_0|datamem_module_0|output_data~389_combout ;
wire \datapath_0|datamem_module_0|output_data~399_combout ;
wire \datapath_0|datamem_module_0|output_data~400_combout ;
wire \datapath_0|datamem_module_0|output_data~401_combout ;
wire \datapath_0|datamem_module_0|output_data~402_combout ;
wire \datapath_0|datamem_module_0|output_data~403_combout ;
wire \datapath_0|datamem_module_0|output_data~404_combout ;
wire \datapath_0|datamem_module_0|output_data~405_combout ;
wire \datapath_0|datamem_module_0|output_data~406_combout ;
wire \datapath_0|datamem_module_0|output_data~407_combout ;
wire \datapath_0|datamem_module_0|output_data~408_combout ;
wire \datapath_0|datamem_module_0|output_data~409_combout ;
wire \datapath_0|datamem_module_0|output_data~410_combout ;
wire \datapath_0|datamem_module_0|output_data~420_combout ;
wire \datapath_0|datamem_module_0|output_data~421_combout ;
wire \datapath_0|datamem_module_0|output_data~422_combout ;
wire \datapath_0|datamem_module_0|output_data~423_combout ;
wire \datapath_0|datamem_module_0|output_data~424_combout ;
wire \datapath_0|datamem_module_0|output_data~425_combout ;
wire \datapath_0|datamem_module_0|output_data~426_combout ;
wire \datapath_0|datamem_module_0|output_data~427_combout ;
wire \datapath_0|datamem_module_0|output_data~428_combout ;
wire \datapath_0|datamem_module_0|output_data~429_combout ;
wire \datapath_0|datamem_module_0|output_data~430_combout ;
wire \datapath_0|datamem_module_0|output_data~431_combout ;
wire \datapath_0|datamem_module_0|output_data~432_combout ;
wire \datapath_0|datamem_module_0|output_data~433_combout ;
wire \datapath_0|datamem_module_0|output_data~434_combout ;
wire \datapath_0|datamem_module_0|output_data~435_combout ;
wire \datapath_0|datamem_module_0|output_data~436_combout ;
wire \datapath_0|datamem_module_0|output_data~437_combout ;
wire \datapath_0|datamem_module_0|output_data~438_combout ;
wire \datapath_0|datamem_module_0|output_data~439_combout ;
wire \datapath_0|datamem_module_0|output_data~440_combout ;
wire \datapath_0|datamem_module_0|output_data~441_combout ;
wire \datapath_0|datamem_module_0|output_data~442_combout ;
wire \datapath_0|datamem_module_0|output_data~443_combout ;
wire \datapath_0|datamem_module_0|output_data~444_combout ;
wire \datapath_0|datamem_module_0|output_data~445_combout ;
wire \datapath_0|datamem_module_0|output_data~446_combout ;
wire \datapath_0|datamem_module_0|output_data~447_combout ;
wire \datapath_0|datamem_module_0|output_data~448_combout ;
wire \datapath_0|datamem_module_0|output_data~449_combout ;
wire \datapath_0|datamem_module_0|output_data~450_combout ;
wire \datapath_0|datamem_module_0|output_data~451_combout ;
wire \datapath_0|datamem_module_0|output_data~452_combout ;
wire \datapath_0|datamem_module_0|output_data~462_combout ;
wire \datapath_0|datamem_module_0|output_data~463_combout ;
wire \datapath_0|datamem_module_0|output_data~464_combout ;
wire \datapath_0|datamem_module_0|output_data~465_combout ;
wire \datapath_0|datamem_module_0|output_data~466_combout ;
wire \datapath_0|datamem_module_0|output_data~467_combout ;
wire \datapath_0|datamem_module_0|output_data~468_combout ;
wire \datapath_0|datamem_module_0|output_data~469_combout ;
wire \datapath_0|datamem_module_0|output_data~470_combout ;
wire \datapath_0|datamem_module_0|output_data~471_combout ;
wire \datapath_0|datamem_module_0|output_data~472_combout ;
wire \datapath_0|datamem_module_0|output_data~473_combout ;
wire \datapath_0|datamem_module_0|output_data~483_combout ;
wire \datapath_0|datamem_module_0|output_data~484_combout ;
wire \datapath_0|datamem_module_0|output_data~485_combout ;
wire \datapath_0|datamem_module_0|output_data~486_combout ;
wire \datapath_0|datamem_module_0|output_data~487_combout ;
wire \datapath_0|datamem_module_0|output_data~488_combout ;
wire \datapath_0|datamem_module_0|output_data~489_combout ;
wire \datapath_0|datamem_module_0|output_data~490_combout ;
wire \datapath_0|datamem_module_0|output_data~491_combout ;
wire \datapath_0|datamem_module_0|output_data~492_combout ;
wire \datapath_0|datamem_module_0|output_data~493_combout ;
wire \datapath_0|datamem_module_0|output_data~494_combout ;
wire \datapath_0|datamem_module_0|output_data~504_combout ;
wire \datapath_0|datamem_module_0|output_data~505_combout ;
wire \datapath_0|datamem_module_0|output_data~506_combout ;
wire \datapath_0|datamem_module_0|output_data~507_combout ;
wire \datapath_0|datamem_module_0|output_data~508_combout ;
wire \datapath_0|datamem_module_0|output_data~509_combout ;
wire \datapath_0|datamem_module_0|output_data~510_combout ;
wire \datapath_0|datamem_module_0|output_data~511_combout ;
wire \datapath_0|datamem_module_0|output_data~512_combout ;
wire \datapath_0|datamem_module_0|output_data~513_combout ;
wire \datapath_0|datamem_module_0|output_data~514_combout ;
wire \datapath_0|datamem_module_0|output_data~515_combout ;
wire \datapath_0|datamem_module_0|output_data~525_combout ;
wire \datapath_0|datamem_module_0|output_data~526_combout ;
wire \datapath_0|datamem_module_0|output_data~527_combout ;
wire \datapath_0|datamem_module_0|output_data~528_combout ;
wire \datapath_0|datamem_module_0|output_data~529_combout ;
wire \datapath_0|datamem_module_0|output_data~530_combout ;
wire \datapath_0|datamem_module_0|output_data~531_combout ;
wire \datapath_0|datamem_module_0|output_data~532_combout ;
wire \datapath_0|datamem_module_0|output_data~533_combout ;
wire \datapath_0|datamem_module_0|output_data~534_combout ;
wire \datapath_0|datamem_module_0|output_data~535_combout ;
wire \datapath_0|datamem_module_0|output_data~536_combout ;
wire \datapath_0|datamem_module_0|output_data~546_combout ;
wire \datapath_0|datamem_module_0|output_data~547_combout ;
wire \datapath_0|datamem_module_0|output_data~548_combout ;
wire \datapath_0|datamem_module_0|output_data~549_combout ;
wire \datapath_0|datamem_module_0|output_data~550_combout ;
wire \datapath_0|datamem_module_0|output_data~551_combout ;
wire \datapath_0|datamem_module_0|output_data~552_combout ;
wire \datapath_0|datamem_module_0|output_data~553_combout ;
wire \datapath_0|datamem_module_0|output_data~554_combout ;
wire \datapath_0|datamem_module_0|output_data~555_combout ;
wire \datapath_0|datamem_module_0|output_data~556_combout ;
wire \datapath_0|datamem_module_0|output_data~557_combout ;
wire \datapath_0|datamem_module_0|output_data~567_combout ;
wire \datapath_0|datamem_module_0|output_data~568_combout ;
wire \datapath_0|datamem_module_0|output_data~569_combout ;
wire \datapath_0|datamem_module_0|output_data~570_combout ;
wire \datapath_0|datamem_module_0|output_data~571_combout ;
wire \datapath_0|datamem_module_0|output_data~572_combout ;
wire \datapath_0|datamem_module_0|output_data~573_combout ;
wire \datapath_0|datamem_module_0|output_data~574_combout ;
wire \datapath_0|datamem_module_0|output_data~575_combout ;
wire \datapath_0|datamem_module_0|output_data~576_combout ;
wire \datapath_0|datamem_module_0|output_data~577_combout ;
wire \datapath_0|datamem_module_0|output_data~578_combout ;
wire \datapath_0|datamem_module_0|output_data~588_combout ;
wire \datapath_0|datamem_module_0|output_data~589_combout ;
wire \datapath_0|datamem_module_0|output_data~590_combout ;
wire \datapath_0|datamem_module_0|output_data~591_combout ;
wire \datapath_0|datamem_module_0|output_data~592_combout ;
wire \datapath_0|datamem_module_0|output_data~593_combout ;
wire \datapath_0|datamem_module_0|output_data~594_combout ;
wire \datapath_0|datamem_module_0|output_data~595_combout ;
wire \datapath_0|datamem_module_0|output_data~596_combout ;
wire \datapath_0|datamem_module_0|output_data~597_combout ;
wire \datapath_0|datamem_module_0|output_data~598_combout ;
wire \datapath_0|datamem_module_0|output_data~599_combout ;
wire \datapath_0|datamem_module_0|output_data~609_combout ;
wire \datapath_0|datamem_module_0|output_data~610_combout ;
wire \datapath_0|datamem_module_0|output_data~611_combout ;
wire \datapath_0|datamem_module_0|output_data~612_combout ;
wire \datapath_0|datamem_module_0|output_data~613_combout ;
wire \datapath_0|datamem_module_0|output_data~614_combout ;
wire \datapath_0|datamem_module_0|output_data~615_combout ;
wire \datapath_0|datamem_module_0|output_data~616_combout ;
wire \datapath_0|datamem_module_0|output_data~617_combout ;
wire \datapath_0|datamem_module_0|output_data~618_combout ;
wire \datapath_0|datamem_module_0|output_data~619_combout ;
wire \datapath_0|datamem_module_0|output_data~620_combout ;
wire \datapath_0|datamem_module_0|output_data~630_combout ;
wire \datapath_0|datamem_module_0|output_data~631_combout ;
wire \datapath_0|datamem_module_0|output_data~632_combout ;
wire \datapath_0|datamem_module_0|output_data~633_combout ;
wire \datapath_0|datamem_module_0|output_data~634_combout ;
wire \datapath_0|datamem_module_0|output_data~635_combout ;
wire \datapath_0|datamem_module_0|output_data~636_combout ;
wire \datapath_0|datamem_module_0|output_data~637_combout ;
wire \datapath_0|datamem_module_0|output_data~638_combout ;
wire \datapath_0|datamem_module_0|output_data~639_combout ;
wire \datapath_0|datamem_module_0|output_data~640_combout ;
wire \datapath_0|datamem_module_0|output_data~641_combout ;
wire \datapath_0|datamem_module_0|output_data~651_combout ;
wire \datapath_0|datamem_module_0|output_data~652_combout ;
wire \datapath_0|datamem_module_0|output_data~653_combout ;
wire \datapath_0|datamem_module_0|output_data~654_combout ;
wire \datapath_0|datamem_module_0|output_data~655_combout ;
wire \datapath_0|datamem_module_0|output_data~656_combout ;
wire \datapath_0|datamem_module_0|output_data~657_combout ;
wire \datapath_0|datamem_module_0|output_data~658_combout ;
wire \datapath_0|datamem_module_0|output_data~659_combout ;
wire \datapath_0|datamem_module_0|output_data~660_combout ;
wire \datapath_0|datamem_module_0|output_data~661_combout ;
wire \datapath_0|datamem_module_0|output_data~662_combout ;
wire \controller_0|Mux26~0_combout ;
wire \controller_0|Mux26~1_combout ;
wire \controller_0|Mux32~0_combout ;
wire \controller_0|Mux30~0_combout ;
wire \controller_0|Mux31~0_combout ;
wire \controller_0|Mux31~1_combout ;
wire \controller_0|Mux27~0_combout ;
wire \controller_0|Mux33~0_combout ;
wire \controller_0|Mux25~0_combout ;
wire \controller_0|Mux29~0_combout ;
wire \controller_0|Mux29~1_combout ;
wire \controller_0|Mux24~0_combout ;
wire \controller_0|Mux24~1_combout ;
wire \controller_0|Mux23~0_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~4_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~5_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[0]~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[2]~2_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[4]~4_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[6]~6_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~4_combout ;
wire \datapath_0|forward_mux_1|Mux24~2_combout ;
wire \datapath_0|forward_mux_1|Mux23~2_combout ;
wire \datapath_0|forward_mux_1|Mux22~2_combout ;
wire \datapath_0|forward_mux_1|Mux21~2_combout ;
wire \datapath_0|forward_mux_1|Mux19~2_combout ;
wire \datapath_0|forward_mux_1|Mux17~2_combout ;
wire \datapath_0|forward_mux_1|Mux14~2_combout ;
wire \datapath_0|forward_mux_1|Mux13~2_combout ;
wire \datapath_0|forward_mux_1|Mux12~2_combout ;
wire \datapath_0|forward_mux_1|Mux9~2_combout ;
wire \datapath_0|forward_mux_1|Mux7~2_combout ;
wire \datapath_0|forward_mux_1|Mux6~2_combout ;
wire \datapath_0|forward_mux_1|Mux5~2_combout ;
wire \datapath_0|forward_mux_1|Mux4~2_combout ;
wire \datapath_0|forward_mux_1|Mux3~2_combout ;
wire \datapath_0|forward_mux_1|Mux2~2_combout ;
wire \datapath_0|forward_mux_1|Mux1~2_combout ;
wire \datapath_0|forward_mux_1|Mux0~2_combout ;
wire \controller_0|internal_JTU_mux_sel~combout ;
wire \debug_pc_output[0]~output_o ;
wire \debug_pc_output[1]~output_o ;
wire \debug_pc_output[2]~output_o ;
wire \debug_pc_output[3]~output_o ;
wire \debug_pc_output[4]~output_o ;
wire \debug_pc_output[5]~output_o ;
wire \debug_pc_output[6]~output_o ;
wire \debug_pc_output[7]~output_o ;
wire \debug_pc_output[8]~output_o ;
wire \debug_pc_output[9]~output_o ;
wire \debug_pc_output[10]~output_o ;
wire \debug_pc_output[11]~output_o ;
wire \debug_pc_output[12]~output_o ;
wire \debug_pc_output[13]~output_o ;
wire \debug_pc_output[14]~output_o ;
wire \debug_pc_output[15]~output_o ;
wire \debug_pc_output[16]~output_o ;
wire \debug_pc_output[17]~output_o ;
wire \debug_pc_output[18]~output_o ;
wire \debug_pc_output[19]~output_o ;
wire \debug_pc_output[20]~output_o ;
wire \debug_pc_output[21]~output_o ;
wire \debug_pc_output[22]~output_o ;
wire \debug_pc_output[23]~output_o ;
wire \debug_pc_output[24]~output_o ;
wire \debug_pc_output[25]~output_o ;
wire \debug_pc_output[26]~output_o ;
wire \debug_pc_output[27]~output_o ;
wire \debug_pc_output[28]~output_o ;
wire \debug_pc_output[29]~output_o ;
wire \debug_pc_output[30]~output_o ;
wire \debug_pc_output[31]~output_o ;
wire \debug_regfile_x31_output[0]~output_o ;
wire \debug_regfile_x31_output[1]~output_o ;
wire \debug_regfile_x31_output[2]~output_o ;
wire \debug_regfile_x31_output[3]~output_o ;
wire \debug_regfile_x31_output[4]~output_o ;
wire \debug_regfile_x31_output[5]~output_o ;
wire \debug_regfile_x31_output[6]~output_o ;
wire \debug_regfile_x31_output[7]~output_o ;
wire \debug_regfile_x31_output[8]~output_o ;
wire \debug_regfile_x31_output[9]~output_o ;
wire \debug_regfile_x31_output[10]~output_o ;
wire \debug_regfile_x31_output[11]~output_o ;
wire \debug_regfile_x31_output[12]~output_o ;
wire \debug_regfile_x31_output[13]~output_o ;
wire \debug_regfile_x31_output[14]~output_o ;
wire \debug_regfile_x31_output[15]~output_o ;
wire \debug_regfile_x31_output[16]~output_o ;
wire \debug_regfile_x31_output[17]~output_o ;
wire \debug_regfile_x31_output[18]~output_o ;
wire \debug_regfile_x31_output[19]~output_o ;
wire \debug_regfile_x31_output[20]~output_o ;
wire \debug_regfile_x31_output[21]~output_o ;
wire \debug_regfile_x31_output[22]~output_o ;
wire \debug_regfile_x31_output[23]~output_o ;
wire \debug_regfile_x31_output[24]~output_o ;
wire \debug_regfile_x31_output[25]~output_o ;
wire \debug_regfile_x31_output[26]~output_o ;
wire \debug_regfile_x31_output[27]~output_o ;
wire \debug_regfile_x31_output[28]~output_o ;
wire \debug_regfile_x31_output[29]~output_o ;
wire \debug_regfile_x31_output[30]~output_o ;
wire \debug_regfile_x31_output[31]~output_o ;
wire \debug_regfile_x1_output[0]~output_o ;
wire \debug_regfile_x1_output[1]~output_o ;
wire \debug_regfile_x1_output[2]~output_o ;
wire \debug_regfile_x1_output[3]~output_o ;
wire \debug_regfile_x1_output[4]~output_o ;
wire \debug_regfile_x1_output[5]~output_o ;
wire \debug_regfile_x1_output[6]~output_o ;
wire \debug_regfile_x1_output[7]~output_o ;
wire \debug_regfile_x1_output[8]~output_o ;
wire \debug_regfile_x1_output[9]~output_o ;
wire \debug_regfile_x1_output[10]~output_o ;
wire \debug_regfile_x1_output[11]~output_o ;
wire \debug_regfile_x1_output[12]~output_o ;
wire \debug_regfile_x1_output[13]~output_o ;
wire \debug_regfile_x1_output[14]~output_o ;
wire \debug_regfile_x1_output[15]~output_o ;
wire \debug_regfile_x1_output[16]~output_o ;
wire \debug_regfile_x1_output[17]~output_o ;
wire \debug_regfile_x1_output[18]~output_o ;
wire \debug_regfile_x1_output[19]~output_o ;
wire \debug_regfile_x1_output[20]~output_o ;
wire \debug_regfile_x1_output[21]~output_o ;
wire \debug_regfile_x1_output[22]~output_o ;
wire \debug_regfile_x1_output[23]~output_o ;
wire \debug_regfile_x1_output[24]~output_o ;
wire \debug_regfile_x1_output[25]~output_o ;
wire \debug_regfile_x1_output[26]~output_o ;
wire \debug_regfile_x1_output[27]~output_o ;
wire \debug_regfile_x1_output[28]~output_o ;
wire \debug_regfile_x1_output[29]~output_o ;
wire \debug_regfile_x1_output[30]~output_o ;
wire \debug_regfile_x1_output[31]~output_o ;
wire \debug_regfile_x2_output[0]~output_o ;
wire \debug_regfile_x2_output[1]~output_o ;
wire \debug_regfile_x2_output[2]~output_o ;
wire \debug_regfile_x2_output[3]~output_o ;
wire \debug_regfile_x2_output[4]~output_o ;
wire \debug_regfile_x2_output[5]~output_o ;
wire \debug_regfile_x2_output[6]~output_o ;
wire \debug_regfile_x2_output[7]~output_o ;
wire \debug_regfile_x2_output[8]~output_o ;
wire \debug_regfile_x2_output[9]~output_o ;
wire \debug_regfile_x2_output[10]~output_o ;
wire \debug_regfile_x2_output[11]~output_o ;
wire \debug_regfile_x2_output[12]~output_o ;
wire \debug_regfile_x2_output[13]~output_o ;
wire \debug_regfile_x2_output[14]~output_o ;
wire \debug_regfile_x2_output[15]~output_o ;
wire \debug_regfile_x2_output[16]~output_o ;
wire \debug_regfile_x2_output[17]~output_o ;
wire \debug_regfile_x2_output[18]~output_o ;
wire \debug_regfile_x2_output[19]~output_o ;
wire \debug_regfile_x2_output[20]~output_o ;
wire \debug_regfile_x2_output[21]~output_o ;
wire \debug_regfile_x2_output[22]~output_o ;
wire \debug_regfile_x2_output[23]~output_o ;
wire \debug_regfile_x2_output[24]~output_o ;
wire \debug_regfile_x2_output[25]~output_o ;
wire \debug_regfile_x2_output[26]~output_o ;
wire \debug_regfile_x2_output[27]~output_o ;
wire \debug_regfile_x2_output[28]~output_o ;
wire \debug_regfile_x2_output[29]~output_o ;
wire \debug_regfile_x2_output[30]~output_o ;
wire \debug_regfile_x2_output[31]~output_o ;
wire \debug_ALU_output[0]~output_o ;
wire \debug_ALU_output[1]~output_o ;
wire \debug_ALU_output[2]~output_o ;
wire \debug_ALU_output[3]~output_o ;
wire \debug_ALU_output[4]~output_o ;
wire \debug_ALU_output[5]~output_o ;
wire \debug_ALU_output[6]~output_o ;
wire \debug_ALU_output[7]~output_o ;
wire \debug_ALU_output[8]~output_o ;
wire \debug_ALU_output[9]~output_o ;
wire \debug_ALU_output[10]~output_o ;
wire \debug_ALU_output[11]~output_o ;
wire \debug_ALU_output[12]~output_o ;
wire \debug_ALU_output[13]~output_o ;
wire \debug_ALU_output[14]~output_o ;
wire \debug_ALU_output[15]~output_o ;
wire \debug_ALU_output[16]~output_o ;
wire \debug_ALU_output[17]~output_o ;
wire \debug_ALU_output[18]~output_o ;
wire \debug_ALU_output[19]~output_o ;
wire \debug_ALU_output[20]~output_o ;
wire \debug_ALU_output[21]~output_o ;
wire \debug_ALU_output[22]~output_o ;
wire \debug_ALU_output[23]~output_o ;
wire \debug_ALU_output[24]~output_o ;
wire \debug_ALU_output[25]~output_o ;
wire \debug_ALU_output[26]~output_o ;
wire \debug_ALU_output[27]~output_o ;
wire \debug_ALU_output[28]~output_o ;
wire \debug_ALU_output[29]~output_o ;
wire \debug_ALU_output[30]~output_o ;
wire \debug_ALU_output[31]~output_o ;
wire \debug_regfile_write~output_o ;
wire \debug_ALU_input_0[0]~output_o ;
wire \debug_ALU_input_0[1]~output_o ;
wire \debug_ALU_input_0[2]~output_o ;
wire \debug_ALU_input_0[3]~output_o ;
wire \debug_ALU_input_0[4]~output_o ;
wire \debug_ALU_input_0[5]~output_o ;
wire \debug_ALU_input_0[6]~output_o ;
wire \debug_ALU_input_0[7]~output_o ;
wire \debug_ALU_input_0[8]~output_o ;
wire \debug_ALU_input_0[9]~output_o ;
wire \debug_ALU_input_0[10]~output_o ;
wire \debug_ALU_input_0[11]~output_o ;
wire \debug_ALU_input_0[12]~output_o ;
wire \debug_ALU_input_0[13]~output_o ;
wire \debug_ALU_input_0[14]~output_o ;
wire \debug_ALU_input_0[15]~output_o ;
wire \debug_ALU_input_0[16]~output_o ;
wire \debug_ALU_input_0[17]~output_o ;
wire \debug_ALU_input_0[18]~output_o ;
wire \debug_ALU_input_0[19]~output_o ;
wire \debug_ALU_input_0[20]~output_o ;
wire \debug_ALU_input_0[21]~output_o ;
wire \debug_ALU_input_0[22]~output_o ;
wire \debug_ALU_input_0[23]~output_o ;
wire \debug_ALU_input_0[24]~output_o ;
wire \debug_ALU_input_0[25]~output_o ;
wire \debug_ALU_input_0[26]~output_o ;
wire \debug_ALU_input_0[27]~output_o ;
wire \debug_ALU_input_0[28]~output_o ;
wire \debug_ALU_input_0[29]~output_o ;
wire \debug_ALU_input_0[30]~output_o ;
wire \debug_ALU_input_0[31]~output_o ;
wire \debug_ALU_input_1[0]~output_o ;
wire \debug_ALU_input_1[1]~output_o ;
wire \debug_ALU_input_1[2]~output_o ;
wire \debug_ALU_input_1[3]~output_o ;
wire \debug_ALU_input_1[4]~output_o ;
wire \debug_ALU_input_1[5]~output_o ;
wire \debug_ALU_input_1[6]~output_o ;
wire \debug_ALU_input_1[7]~output_o ;
wire \debug_ALU_input_1[8]~output_o ;
wire \debug_ALU_input_1[9]~output_o ;
wire \debug_ALU_input_1[10]~output_o ;
wire \debug_ALU_input_1[11]~output_o ;
wire \debug_ALU_input_1[12]~output_o ;
wire \debug_ALU_input_1[13]~output_o ;
wire \debug_ALU_input_1[14]~output_o ;
wire \debug_ALU_input_1[15]~output_o ;
wire \debug_ALU_input_1[16]~output_o ;
wire \debug_ALU_input_1[17]~output_o ;
wire \debug_ALU_input_1[18]~output_o ;
wire \debug_ALU_input_1[19]~output_o ;
wire \debug_ALU_input_1[20]~output_o ;
wire \debug_ALU_input_1[21]~output_o ;
wire \debug_ALU_input_1[22]~output_o ;
wire \debug_ALU_input_1[23]~output_o ;
wire \debug_ALU_input_1[24]~output_o ;
wire \debug_ALU_input_1[25]~output_o ;
wire \debug_ALU_input_1[26]~output_o ;
wire \debug_ALU_input_1[27]~output_o ;
wire \debug_ALU_input_1[28]~output_o ;
wire \debug_ALU_input_1[29]~output_o ;
wire \debug_ALU_input_1[30]~output_o ;
wire \debug_ALU_input_1[31]~output_o ;
wire \debug_reg_file_read_address_0[0]~output_o ;
wire \debug_reg_file_read_address_0[1]~output_o ;
wire \debug_reg_file_read_address_0[2]~output_o ;
wire \debug_reg_file_read_address_0[3]~output_o ;
wire \debug_reg_file_read_address_0[4]~output_o ;
wire \debug_reg_file_read_address_1[0]~output_o ;
wire \debug_reg_file_read_address_1[1]~output_o ;
wire \debug_reg_file_read_address_1[2]~output_o ;
wire \debug_reg_file_read_address_1[3]~output_o ;
wire \debug_reg_file_read_address_1[4]~output_o ;
wire \debug_mux0_sel[0]~output_o ;
wire \debug_mux0_sel[1]~output_o ;
wire \debug_immediate[0]~output_o ;
wire \debug_immediate[1]~output_o ;
wire \debug_immediate[2]~output_o ;
wire \debug_immediate[3]~output_o ;
wire \debug_immediate[4]~output_o ;
wire \debug_immediate[5]~output_o ;
wire \debug_immediate[6]~output_o ;
wire \debug_immediate[7]~output_o ;
wire \debug_immediate[8]~output_o ;
wire \debug_immediate[9]~output_o ;
wire \debug_immediate[10]~output_o ;
wire \debug_immediate[11]~output_o ;
wire \debug_immediate[12]~output_o ;
wire \debug_immediate[13]~output_o ;
wire \debug_immediate[14]~output_o ;
wire \debug_immediate[15]~output_o ;
wire \debug_immediate[16]~output_o ;
wire \debug_immediate[17]~output_o ;
wire \debug_immediate[18]~output_o ;
wire \debug_immediate[19]~output_o ;
wire \debug_immediate[20]~output_o ;
wire \debug_immediate[21]~output_o ;
wire \debug_immediate[22]~output_o ;
wire \debug_immediate[23]~output_o ;
wire \debug_immediate[24]~output_o ;
wire \debug_immediate[25]~output_o ;
wire \debug_immediate[26]~output_o ;
wire \debug_immediate[27]~output_o ;
wire \debug_immediate[28]~output_o ;
wire \debug_immediate[29]~output_o ;
wire \debug_immediate[30]~output_o ;
wire \debug_immediate[31]~output_o ;
wire \debug_ALU_operation[0]~output_o ;
wire \debug_ALU_operation[1]~output_o ;
wire \debug_ALU_operation[2]~output_o ;
wire \debug_ALU_operation[3]~output_o ;
wire \debug_forward_mux_0[0]~output_o ;
wire \debug_forward_mux_0[1]~output_o ;
wire \debug_forward_mux_0[2]~output_o ;
wire \debug_forward_mux_1[0]~output_o ;
wire \debug_forward_mux_1[1]~output_o ;
wire \debug_forward_mux_1[2]~output_o ;
wire \debug_reg_file_read_address_0_ID_EXE[0]~output_o ;
wire \debug_reg_file_read_address_0_ID_EXE[1]~output_o ;
wire \debug_reg_file_read_address_0_ID_EXE[2]~output_o ;
wire \debug_reg_file_read_address_0_ID_EXE[3]~output_o ;
wire \debug_reg_file_read_address_0_ID_EXE[4]~output_o ;
wire \debug_reg_file_write_address_EX_MEM[0]~output_o ;
wire \debug_reg_file_write_address_EX_MEM[1]~output_o ;
wire \debug_reg_file_write_address_EX_MEM[2]~output_o ;
wire \debug_reg_file_write_address_EX_MEM[3]~output_o ;
wire \debug_reg_file_write_address_EX_MEM[4]~output_o ;
wire \debug_mux0_sel_MEM_WB[0]~output_o ;
wire \debug_mux0_sel_MEM_WB[1]~output_o ;
wire \debug_reg_file_write_MEM_WB~output_o ;
wire \debug_reg_file_write_address_MEM_WB[0]~output_o ;
wire \debug_reg_file_write_address_MEM_WB[1]~output_o ;
wire \debug_reg_file_write_address_MEM_WB[2]~output_o ;
wire \debug_reg_file_write_address_MEM_WB[3]~output_o ;
wire \debug_reg_file_write_address_MEM_WB[4]~output_o ;
wire \debug_ALU_output_MEM_WB[0]~output_o ;
wire \debug_ALU_output_MEM_WB[1]~output_o ;
wire \debug_ALU_output_MEM_WB[2]~output_o ;
wire \debug_ALU_output_MEM_WB[3]~output_o ;
wire \debug_ALU_output_MEM_WB[4]~output_o ;
wire \debug_ALU_output_MEM_WB[5]~output_o ;
wire \debug_ALU_output_MEM_WB[6]~output_o ;
wire \debug_ALU_output_MEM_WB[7]~output_o ;
wire \debug_ALU_output_MEM_WB[8]~output_o ;
wire \debug_ALU_output_MEM_WB[9]~output_o ;
wire \debug_ALU_output_MEM_WB[10]~output_o ;
wire \debug_ALU_output_MEM_WB[11]~output_o ;
wire \debug_ALU_output_MEM_WB[12]~output_o ;
wire \debug_ALU_output_MEM_WB[13]~output_o ;
wire \debug_ALU_output_MEM_WB[14]~output_o ;
wire \debug_ALU_output_MEM_WB[15]~output_o ;
wire \debug_ALU_output_MEM_WB[16]~output_o ;
wire \debug_ALU_output_MEM_WB[17]~output_o ;
wire \debug_ALU_output_MEM_WB[18]~output_o ;
wire \debug_ALU_output_MEM_WB[19]~output_o ;
wire \debug_ALU_output_MEM_WB[20]~output_o ;
wire \debug_ALU_output_MEM_WB[21]~output_o ;
wire \debug_ALU_output_MEM_WB[22]~output_o ;
wire \debug_ALU_output_MEM_WB[23]~output_o ;
wire \debug_ALU_output_MEM_WB[24]~output_o ;
wire \debug_ALU_output_MEM_WB[25]~output_o ;
wire \debug_ALU_output_MEM_WB[26]~output_o ;
wire \debug_ALU_output_MEM_WB[27]~output_o ;
wire \debug_ALU_output_MEM_WB[28]~output_o ;
wire \debug_ALU_output_MEM_WB[29]~output_o ;
wire \debug_ALU_output_MEM_WB[30]~output_o ;
wire \debug_ALU_output_MEM_WB[31]~output_o ;
wire \debug_ALU_output_EX_MEM[0]~output_o ;
wire \debug_ALU_output_EX_MEM[1]~output_o ;
wire \debug_ALU_output_EX_MEM[2]~output_o ;
wire \debug_ALU_output_EX_MEM[3]~output_o ;
wire \debug_ALU_output_EX_MEM[4]~output_o ;
wire \debug_ALU_output_EX_MEM[5]~output_o ;
wire \debug_ALU_output_EX_MEM[6]~output_o ;
wire \debug_ALU_output_EX_MEM[7]~output_o ;
wire \debug_ALU_output_EX_MEM[8]~output_o ;
wire \debug_ALU_output_EX_MEM[9]~output_o ;
wire \debug_ALU_output_EX_MEM[10]~output_o ;
wire \debug_ALU_output_EX_MEM[11]~output_o ;
wire \debug_ALU_output_EX_MEM[12]~output_o ;
wire \debug_ALU_output_EX_MEM[13]~output_o ;
wire \debug_ALU_output_EX_MEM[14]~output_o ;
wire \debug_ALU_output_EX_MEM[15]~output_o ;
wire \debug_ALU_output_EX_MEM[16]~output_o ;
wire \debug_ALU_output_EX_MEM[17]~output_o ;
wire \debug_ALU_output_EX_MEM[18]~output_o ;
wire \debug_ALU_output_EX_MEM[19]~output_o ;
wire \debug_ALU_output_EX_MEM[20]~output_o ;
wire \debug_ALU_output_EX_MEM[21]~output_o ;
wire \debug_ALU_output_EX_MEM[22]~output_o ;
wire \debug_ALU_output_EX_MEM[23]~output_o ;
wire \debug_ALU_output_EX_MEM[24]~output_o ;
wire \debug_ALU_output_EX_MEM[25]~output_o ;
wire \debug_ALU_output_EX_MEM[26]~output_o ;
wire \debug_ALU_output_EX_MEM[27]~output_o ;
wire \debug_ALU_output_EX_MEM[28]~output_o ;
wire \debug_ALU_output_EX_MEM[29]~output_o ;
wire \debug_ALU_output_EX_MEM[30]~output_o ;
wire \debug_ALU_output_EX_MEM[31]~output_o ;
wire \debug_register_file_output_0[0]~output_o ;
wire \debug_register_file_output_0[1]~output_o ;
wire \debug_register_file_output_0[2]~output_o ;
wire \debug_register_file_output_0[3]~output_o ;
wire \debug_register_file_output_0[4]~output_o ;
wire \debug_register_file_output_0[5]~output_o ;
wire \debug_register_file_output_0[6]~output_o ;
wire \debug_register_file_output_0[7]~output_o ;
wire \debug_register_file_output_0[8]~output_o ;
wire \debug_register_file_output_0[9]~output_o ;
wire \debug_register_file_output_0[10]~output_o ;
wire \debug_register_file_output_0[11]~output_o ;
wire \debug_register_file_output_0[12]~output_o ;
wire \debug_register_file_output_0[13]~output_o ;
wire \debug_register_file_output_0[14]~output_o ;
wire \debug_register_file_output_0[15]~output_o ;
wire \debug_register_file_output_0[16]~output_o ;
wire \debug_register_file_output_0[17]~output_o ;
wire \debug_register_file_output_0[18]~output_o ;
wire \debug_register_file_output_0[19]~output_o ;
wire \debug_register_file_output_0[20]~output_o ;
wire \debug_register_file_output_0[21]~output_o ;
wire \debug_register_file_output_0[22]~output_o ;
wire \debug_register_file_output_0[23]~output_o ;
wire \debug_register_file_output_0[24]~output_o ;
wire \debug_register_file_output_0[25]~output_o ;
wire \debug_register_file_output_0[26]~output_o ;
wire \debug_register_file_output_0[27]~output_o ;
wire \debug_register_file_output_0[28]~output_o ;
wire \debug_register_file_output_0[29]~output_o ;
wire \debug_register_file_output_0[30]~output_o ;
wire \debug_register_file_output_0[31]~output_o ;
wire \debug_register_file_output_1[0]~output_o ;
wire \debug_register_file_output_1[1]~output_o ;
wire \debug_register_file_output_1[2]~output_o ;
wire \debug_register_file_output_1[3]~output_o ;
wire \debug_register_file_output_1[4]~output_o ;
wire \debug_register_file_output_1[5]~output_o ;
wire \debug_register_file_output_1[6]~output_o ;
wire \debug_register_file_output_1[7]~output_o ;
wire \debug_register_file_output_1[8]~output_o ;
wire \debug_register_file_output_1[9]~output_o ;
wire \debug_register_file_output_1[10]~output_o ;
wire \debug_register_file_output_1[11]~output_o ;
wire \debug_register_file_output_1[12]~output_o ;
wire \debug_register_file_output_1[13]~output_o ;
wire \debug_register_file_output_1[14]~output_o ;
wire \debug_register_file_output_1[15]~output_o ;
wire \debug_register_file_output_1[16]~output_o ;
wire \debug_register_file_output_1[17]~output_o ;
wire \debug_register_file_output_1[18]~output_o ;
wire \debug_register_file_output_1[19]~output_o ;
wire \debug_register_file_output_1[20]~output_o ;
wire \debug_register_file_output_1[21]~output_o ;
wire \debug_register_file_output_1[22]~output_o ;
wire \debug_register_file_output_1[23]~output_o ;
wire \debug_register_file_output_1[24]~output_o ;
wire \debug_register_file_output_1[25]~output_o ;
wire \debug_register_file_output_1[26]~output_o ;
wire \debug_register_file_output_1[27]~output_o ;
wire \debug_register_file_output_1[28]~output_o ;
wire \debug_register_file_output_1[29]~output_o ;
wire \debug_register_file_output_1[30]~output_o ;
wire \debug_register_file_output_1[31]~output_o ;
wire \debug_register_file_output_0_ID_EX[0]~output_o ;
wire \debug_register_file_output_0_ID_EX[1]~output_o ;
wire \debug_register_file_output_0_ID_EX[2]~output_o ;
wire \debug_register_file_output_0_ID_EX[3]~output_o ;
wire \debug_register_file_output_0_ID_EX[4]~output_o ;
wire \debug_register_file_output_0_ID_EX[5]~output_o ;
wire \debug_register_file_output_0_ID_EX[6]~output_o ;
wire \debug_register_file_output_0_ID_EX[7]~output_o ;
wire \debug_register_file_output_0_ID_EX[8]~output_o ;
wire \debug_register_file_output_0_ID_EX[9]~output_o ;
wire \debug_register_file_output_0_ID_EX[10]~output_o ;
wire \debug_register_file_output_0_ID_EX[11]~output_o ;
wire \debug_register_file_output_0_ID_EX[12]~output_o ;
wire \debug_register_file_output_0_ID_EX[13]~output_o ;
wire \debug_register_file_output_0_ID_EX[14]~output_o ;
wire \debug_register_file_output_0_ID_EX[15]~output_o ;
wire \debug_register_file_output_0_ID_EX[16]~output_o ;
wire \debug_register_file_output_0_ID_EX[17]~output_o ;
wire \debug_register_file_output_0_ID_EX[18]~output_o ;
wire \debug_register_file_output_0_ID_EX[19]~output_o ;
wire \debug_register_file_output_0_ID_EX[20]~output_o ;
wire \debug_register_file_output_0_ID_EX[21]~output_o ;
wire \debug_register_file_output_0_ID_EX[22]~output_o ;
wire \debug_register_file_output_0_ID_EX[23]~output_o ;
wire \debug_register_file_output_0_ID_EX[24]~output_o ;
wire \debug_register_file_output_0_ID_EX[25]~output_o ;
wire \debug_register_file_output_0_ID_EX[26]~output_o ;
wire \debug_register_file_output_0_ID_EX[27]~output_o ;
wire \debug_register_file_output_0_ID_EX[28]~output_o ;
wire \debug_register_file_output_0_ID_EX[29]~output_o ;
wire \debug_register_file_output_0_ID_EX[30]~output_o ;
wire \debug_register_file_output_0_ID_EX[31]~output_o ;
wire \debug_register_file_output_1_ID_EX[0]~output_o ;
wire \debug_register_file_output_1_ID_EX[1]~output_o ;
wire \debug_register_file_output_1_ID_EX[2]~output_o ;
wire \debug_register_file_output_1_ID_EX[3]~output_o ;
wire \debug_register_file_output_1_ID_EX[4]~output_o ;
wire \debug_register_file_output_1_ID_EX[5]~output_o ;
wire \debug_register_file_output_1_ID_EX[6]~output_o ;
wire \debug_register_file_output_1_ID_EX[7]~output_o ;
wire \debug_register_file_output_1_ID_EX[8]~output_o ;
wire \debug_register_file_output_1_ID_EX[9]~output_o ;
wire \debug_register_file_output_1_ID_EX[10]~output_o ;
wire \debug_register_file_output_1_ID_EX[11]~output_o ;
wire \debug_register_file_output_1_ID_EX[12]~output_o ;
wire \debug_register_file_output_1_ID_EX[13]~output_o ;
wire \debug_register_file_output_1_ID_EX[14]~output_o ;
wire \debug_register_file_output_1_ID_EX[15]~output_o ;
wire \debug_register_file_output_1_ID_EX[16]~output_o ;
wire \debug_register_file_output_1_ID_EX[17]~output_o ;
wire \debug_register_file_output_1_ID_EX[18]~output_o ;
wire \debug_register_file_output_1_ID_EX[19]~output_o ;
wire \debug_register_file_output_1_ID_EX[20]~output_o ;
wire \debug_register_file_output_1_ID_EX[21]~output_o ;
wire \debug_register_file_output_1_ID_EX[22]~output_o ;
wire \debug_register_file_output_1_ID_EX[23]~output_o ;
wire \debug_register_file_output_1_ID_EX[24]~output_o ;
wire \debug_register_file_output_1_ID_EX[25]~output_o ;
wire \debug_register_file_output_1_ID_EX[26]~output_o ;
wire \debug_register_file_output_1_ID_EX[27]~output_o ;
wire \debug_register_file_output_1_ID_EX[28]~output_o ;
wire \debug_register_file_output_1_ID_EX[29]~output_o ;
wire \debug_register_file_output_1_ID_EX[30]~output_o ;
wire \debug_register_file_output_1_ID_EX[31]~output_o ;
wire \debug_instruction[0]~output_o ;
wire \debug_instruction[1]~output_o ;
wire \debug_instruction[2]~output_o ;
wire \debug_instruction[3]~output_o ;
wire \debug_instruction[4]~output_o ;
wire \debug_instruction[5]~output_o ;
wire \debug_instruction[6]~output_o ;
wire \debug_instruction[7]~output_o ;
wire \debug_instruction[8]~output_o ;
wire \debug_instruction[9]~output_o ;
wire \debug_instruction[10]~output_o ;
wire \debug_instruction[11]~output_o ;
wire \debug_instruction[12]~output_o ;
wire \debug_instruction[13]~output_o ;
wire \debug_instruction[14]~output_o ;
wire \debug_instruction[15]~output_o ;
wire \debug_instruction[16]~output_o ;
wire \debug_instruction[17]~output_o ;
wire \debug_instruction[18]~output_o ;
wire \debug_instruction[19]~output_o ;
wire \debug_instruction[20]~output_o ;
wire \debug_instruction[21]~output_o ;
wire \debug_instruction[22]~output_o ;
wire \debug_instruction[23]~output_o ;
wire \debug_instruction[24]~output_o ;
wire \debug_instruction[25]~output_o ;
wire \debug_instruction[26]~output_o ;
wire \debug_instruction[27]~output_o ;
wire \debug_instruction[28]~output_o ;
wire \debug_instruction[29]~output_o ;
wire \debug_instruction[30]~output_o ;
wire \debug_instruction[31]~output_o ;
wire \clock~input_o ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[2]~31 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[3]~32_combout ;
wire \controller_0|decoded_cluster.AUIPC_1816~combout ;
wire \controller_0|decoded_cluster.INVALID_1924~combout ;
wire \controller_0|decoded_cluster.LUI_1810~combout ;
wire \controller_0|decoded_cluster.OP_1834~combout ;
wire \controller_0|Selector31~0_combout ;
wire \controller_0|Selector31~1_combout ;
wire \controller_0|decoded_cluster.BRANCH_1900~combout ;
wire \controller_0|Selector31~2_combout ;
wire \controller_0|decoded_cluster.OP_IMM_1840~combout ;
wire \controller_0|decoded_cluster.LOAD_1918~combout ;
wire \controller_0|WideNor1~2_combout ;
wire \controller_0|WideNor1~3_combout ;
wire \controller_0|WideNor1~combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[2]~30_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[3]~33 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[4]~35 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[5]~36_combout ;
wire \controller_0|Selector32~1_combout ;
wire \controller_0|Selector32~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~7 ;
wire \datapath_0|JTU_0|internal_adder|Add0~9 ;
wire \datapath_0|JTU_0|internal_adder|Add0~10_combout ;
wire \reset~input_o ;
wire \controller_0|Selector27~0_combout ;
wire \controller_0|WideNor1~4_combout ;
wire \controller_0|Selector93~0_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[4]~34_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~8_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0_combout ;
wire \controller_0|Selector79~2_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0_combout ;
wire \controller_0|Selector78~2_combout ;
wire \datapath_0|FU_0|forward_0~0_combout ;
wire \datapath_0|FU_0|forward_0~1_combout ;
wire \controller_0|Selector82~2_combout ;
wire \datapath_0|FU_0|Equal2~1_combout ;
wire \controller_0|Selector92~0_combout ;
wire \datapath_0|FU_0|forward_0~2_combout ;
wire \controller_0|internal_reg_file_write~combout ;
wire \datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out~q ;
wire \datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ;
wire \datapath_0|FU_0|forward_1~0_combout ;
wire \datapath_0|FU_0|forward_mux_0_control[0]~1_combout ;
wire \datapath_0|FU_0|forward_1~1_combout ;
wire \datapath_0|FU_0|forward_mux_0_control[1]~0_combout ;
wire \datapath_0|Add1~1 ;
wire \datapath_0|Add1~3 ;
wire \datapath_0|Add1~4_combout ;
wire \datapath_0|mux_0|Mux27~1_combout ;
wire \datapath_0|register_file_0|internal_reg_load[2]~5_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux27~1_combout ;
wire \datapath_0|forward_mux_0|Mux27~0_combout ;
wire \datapath_0|forward_mux_0|Mux27~1_combout ;
wire \datapath_0|forward_mux_0|Mux31~3_combout ;
wire \datapath_0|forward_mux_0|Mux27~2_combout ;
wire \datapath_0|Add1~0_combout ;
wire \datapath_0|mux_0|Mux29~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux29~1_combout ;
wire \datapath_0|forward_mux_0|Mux29~0_combout ;
wire \datapath_0|forward_mux_0|Mux29~1_combout ;
wire \datapath_0|forward_mux_0|Mux29~2_combout ;
wire \datapath_0|mux_0|Mux31~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux31~1_combout ;
wire \datapath_0|forward_mux_0|Mux31~0_combout ;
wire \datapath_0|forward_mux_0|Mux31~1_combout ;
wire \datapath_0|forward_mux_0|Mux31~4_combout ;
wire \datapath_0|ALU_0|Add0~33_cout ;
wire \datapath_0|ALU_0|Add0~34_combout ;
wire \controller_0|internal_ALU_branch~combout ;
wire \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ;
wire \datapath_0|ALU_0|Add0~35 ;
wire \datapath_0|ALU_0|Add0~36_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[1]~1_combout ;
wire \controller_0|internal_datamem_write~combout ;
wire \datapath_0|ID_EX_PLR|datamem_write_reg|reg_out~q ;
wire \datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ;
wire \datapath_0|ALU_0|Add0~39 ;
wire \datapath_0|ALU_0|Add0~40_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[5]~5_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~9_combout ;
wire \datapath_0|Add1~5 ;
wire \datapath_0|Add1~7 ;
wire \datapath_0|Add1~8_combout ;
wire \datapath_0|mux_0|Mux25~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux25~1_combout ;
wire \datapath_0|forward_mux_0|Mux25~0_combout ;
wire \datapath_0|forward_mux_0|Mux25~1_combout ;
wire \datapath_0|forward_mux_0|Mux25~2_combout ;
wire \datapath_0|ALU_0|Add0~43 ;
wire \datapath_0|ALU_0|Add0~45 ;
wire \datapath_0|ALU_0|Add0~46_combout ;
wire \datapath_0|datamem_module_0|Equal0~0_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ;
wire \datapath_0|datamem_module_0|output_data~117_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~12_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ;
wire \datapath_0|datamem_module_0|output_data~118_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~2_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~10_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ;
wire \datapath_0|datamem_module_0|output_data~119_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~14_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ;
wire \datapath_0|datamem_module_0|output_data~120_combout ;
wire \datapath_0|datamem_module_0|output_data~121_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~7_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~11_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ;
wire \datapath_0|datamem_module_0|output_data~122_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~15_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ;
wire \datapath_0|datamem_module_0|output_data~123_combout ;
wire \datapath_0|datamem_module_0|output_data~124_combout ;
wire \datapath_0|datamem_module_0|output_data~125_combout ;
wire \datapath_0|Add1~6_combout ;
wire \datapath_0|mux_0|Mux26~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux26~1_combout ;
wire \datapath_0|forward_mux_0|Mux26~0_combout ;
wire \datapath_0|forward_mux_0|Mux26~1_combout ;
wire \datapath_0|forward_mux_0|Mux26~2_combout ;
wire \datapath_0|ALU_0|Add0~44_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~1_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ;
wire \datapath_0|datamem_module_0|output_data~33_combout ;
wire \datapath_0|datamem_module_0|output_data~34_combout ;
wire \datapath_0|datamem_module_0|output_data~35_combout ;
wire \datapath_0|datamem_module_0|output_data~36_combout ;
wire \datapath_0|datamem_module_0|output_data~37_combout ;
wire \datapath_0|datamem_module_0|output_data~38_combout ;
wire \datapath_0|datamem_module_0|output_data~39_combout ;
wire \datapath_0|datamem_module_0|output_data~40_combout ;
wire \datapath_0|datamem_module_0|output_data~41_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~1 ;
wire \datapath_0|JTU_0|internal_adder|Add0~2_combout ;
wire \datapath_0|mux_0|Mux30~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux30~1_combout ;
wire \datapath_0|forward_mux_0|Mux30~0_combout ;
wire \datapath_0|forward_mux_0|Mux30~1_combout ;
wire \datapath_0|forward_mux_0|Mux30~2_combout ;
wire \datapath_0|ALU_0|Add0~37 ;
wire \datapath_0|ALU_0|Add0~38_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[3]~3_combout ;
wire \datapath_0|datamem_module_0|output_data~75_combout ;
wire \datapath_0|datamem_module_0|output_data~76_combout ;
wire \datapath_0|datamem_module_0|output_data~77_combout ;
wire \datapath_0|datamem_module_0|output_data~78_combout ;
wire \datapath_0|datamem_module_0|output_data~79_combout ;
wire \datapath_0|datamem_module_0|output_data~80_combout ;
wire \datapath_0|datamem_module_0|output_data~81_combout ;
wire \datapath_0|datamem_module_0|output_data~82_combout ;
wire \datapath_0|datamem_module_0|output_data~83_combout ;
wire \datapath_0|Add1~2_combout ;
wire \datapath_0|mux_0|Mux28~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux28~1_combout ;
wire \datapath_0|forward_mux_0|Mux28~0_combout ;
wire \datapath_0|forward_mux_0|Mux28~1_combout ;
wire \datapath_0|forward_mux_0|Mux28~2_combout ;
wire \datapath_0|ALU_0|Add0~41 ;
wire \datapath_0|ALU_0|Add0~42_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~7_combout ;
wire \datapath_0|datamem_module_0|output_data~663_combout ;
wire \datapath_0|datamem_module_0|output_data~664_combout ;
wire \datapath_0|datamem_module_0|output_data~665_combout ;
wire \datapath_0|datamem_module_0|output_data~666_combout ;
wire \datapath_0|datamem_module_0|output_data~667_combout ;
wire \datapath_0|datamem_module_0|output_data~668_combout ;
wire \datapath_0|datamem_module_0|output_data~669_combout ;
wire \datapath_0|datamem_module_0|output_data~670_combout ;
wire \datapath_0|datamem_module_0|output_data~671_combout ;
wire \datapath_0|Add1~9 ;
wire \datapath_0|Add1~11 ;
wire \datapath_0|Add1~13 ;
wire \datapath_0|Add1~15 ;
wire \datapath_0|Add1~17 ;
wire \datapath_0|Add1~19 ;
wire \datapath_0|Add1~21 ;
wire \datapath_0|Add1~23 ;
wire \datapath_0|Add1~25 ;
wire \datapath_0|Add1~27 ;
wire \datapath_0|Add1~29 ;
wire \datapath_0|Add1~31 ;
wire \datapath_0|Add1~33 ;
wire \datapath_0|Add1~35 ;
wire \datapath_0|Add1~37 ;
wire \datapath_0|Add1~39 ;
wire \datapath_0|Add1~41 ;
wire \datapath_0|Add1~43 ;
wire \datapath_0|Add1~45 ;
wire \datapath_0|Add1~47 ;
wire \datapath_0|Add1~49 ;
wire \datapath_0|Add1~51 ;
wire \datapath_0|Add1~53 ;
wire \datapath_0|Add1~55 ;
wire \datapath_0|Add1~57 ;
wire \datapath_0|Add1~58_combout ;
wire \datapath_0|mux_0|Mux0~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux0~1_combout ;
wire \datapath_0|forward_mux_0|Mux0~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~5_combout ;
wire \datapath_0|datamem_module_0|output_data~621_combout ;
wire \datapath_0|datamem_module_0|output_data~622_combout ;
wire \datapath_0|datamem_module_0|output_data~623_combout ;
wire \datapath_0|datamem_module_0|output_data~624_combout ;
wire \datapath_0|datamem_module_0|output_data~625_combout ;
wire \datapath_0|datamem_module_0|output_data~626_combout ;
wire \datapath_0|datamem_module_0|output_data~627_combout ;
wire \datapath_0|datamem_module_0|output_data~628_combout ;
wire \datapath_0|datamem_module_0|output_data~629_combout ;
wire \datapath_0|Add1~54_combout ;
wire \datapath_0|mux_0|Mux2~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux2~1_combout ;
wire \datapath_0|forward_mux_0|Mux2~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~3_combout ;
wire \datapath_0|datamem_module_0|output_data~579_combout ;
wire \datapath_0|datamem_module_0|output_data~580_combout ;
wire \datapath_0|datamem_module_0|output_data~581_combout ;
wire \datapath_0|datamem_module_0|output_data~582_combout ;
wire \datapath_0|datamem_module_0|output_data~583_combout ;
wire \datapath_0|datamem_module_0|output_data~584_combout ;
wire \datapath_0|datamem_module_0|output_data~585_combout ;
wire \datapath_0|datamem_module_0|output_data~586_combout ;
wire \datapath_0|datamem_module_0|output_data~587_combout ;
wire \datapath_0|Add1~50_combout ;
wire \datapath_0|mux_0|Mux4~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux4~1_combout ;
wire \datapath_0|forward_mux_0|Mux4~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~1_combout ;
wire \datapath_0|datamem_module_0|output_data~537_combout ;
wire \datapath_0|datamem_module_0|output_data~538_combout ;
wire \datapath_0|datamem_module_0|output_data~539_combout ;
wire \datapath_0|datamem_module_0|output_data~540_combout ;
wire \datapath_0|datamem_module_0|output_data~541_combout ;
wire \datapath_0|datamem_module_0|output_data~542_combout ;
wire \datapath_0|datamem_module_0|output_data~543_combout ;
wire \datapath_0|datamem_module_0|output_data~544_combout ;
wire \datapath_0|datamem_module_0|output_data~545_combout ;
wire \datapath_0|Add1~46_combout ;
wire \datapath_0|mux_0|Mux6~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux6~1_combout ;
wire \datapath_0|forward_mux_0|Mux6~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~7_combout ;
wire \datapath_0|datamem_module_0|output_data~495_combout ;
wire \datapath_0|datamem_module_0|output_data~496_combout ;
wire \datapath_0|datamem_module_0|output_data~497_combout ;
wire \datapath_0|datamem_module_0|output_data~498_combout ;
wire \datapath_0|datamem_module_0|output_data~499_combout ;
wire \datapath_0|datamem_module_0|output_data~500_combout ;
wire \datapath_0|datamem_module_0|output_data~501_combout ;
wire \datapath_0|datamem_module_0|output_data~502_combout ;
wire \datapath_0|datamem_module_0|output_data~503_combout ;
wire \datapath_0|Add1~42_combout ;
wire \datapath_0|mux_0|Mux8~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux8~1_combout ;
wire \datapath_0|forward_mux_0|Mux8~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~5_combout ;
wire \datapath_0|datamem_module_0|output_data~453_combout ;
wire \datapath_0|datamem_module_0|output_data~454_combout ;
wire \datapath_0|datamem_module_0|output_data~455_combout ;
wire \datapath_0|datamem_module_0|output_data~456_combout ;
wire \datapath_0|datamem_module_0|output_data~457_combout ;
wire \datapath_0|datamem_module_0|output_data~458_combout ;
wire \datapath_0|datamem_module_0|output_data~459_combout ;
wire \datapath_0|datamem_module_0|output_data~460_combout ;
wire \datapath_0|datamem_module_0|output_data~461_combout ;
wire \datapath_0|Add1~38_combout ;
wire \datapath_0|mux_0|Mux10~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux10~1_combout ;
wire \datapath_0|forward_mux_0|Mux10~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~3_combout ;
wire \datapath_0|datamem_module_0|output_data~411_combout ;
wire \datapath_0|datamem_module_0|output_data~412_combout ;
wire \datapath_0|datamem_module_0|output_data~413_combout ;
wire \datapath_0|datamem_module_0|output_data~414_combout ;
wire \datapath_0|datamem_module_0|output_data~415_combout ;
wire \datapath_0|datamem_module_0|output_data~416_combout ;
wire \datapath_0|datamem_module_0|output_data~417_combout ;
wire \datapath_0|datamem_module_0|output_data~418_combout ;
wire \datapath_0|datamem_module_0|output_data~419_combout ;
wire \datapath_0|Add1~34_combout ;
wire \datapath_0|mux_0|Mux12~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux12~1_combout ;
wire \datapath_0|forward_mux_0|Mux12~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~1_combout ;
wire \datapath_0|datamem_module_0|output_data~369_combout ;
wire \datapath_0|datamem_module_0|output_data~370_combout ;
wire \datapath_0|datamem_module_0|output_data~371_combout ;
wire \datapath_0|datamem_module_0|output_data~372_combout ;
wire \datapath_0|datamem_module_0|output_data~373_combout ;
wire \datapath_0|datamem_module_0|output_data~374_combout ;
wire \datapath_0|datamem_module_0|output_data~375_combout ;
wire \datapath_0|datamem_module_0|output_data~376_combout ;
wire \datapath_0|datamem_module_0|output_data~377_combout ;
wire \datapath_0|Add1~30_combout ;
wire \datapath_0|mux_0|Mux14~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux14~1_combout ;
wire \datapath_0|forward_mux_0|Mux14~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~7_combout ;
wire \datapath_0|datamem_module_0|output_data~327_combout ;
wire \datapath_0|datamem_module_0|output_data~328_combout ;
wire \datapath_0|datamem_module_0|output_data~329_combout ;
wire \datapath_0|datamem_module_0|output_data~330_combout ;
wire \datapath_0|datamem_module_0|output_data~331_combout ;
wire \datapath_0|datamem_module_0|output_data~332_combout ;
wire \datapath_0|datamem_module_0|output_data~333_combout ;
wire \datapath_0|datamem_module_0|output_data~334_combout ;
wire \datapath_0|datamem_module_0|output_data~335_combout ;
wire \datapath_0|Add1~26_combout ;
wire \datapath_0|mux_0|Mux16~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux16~1_combout ;
wire \datapath_0|forward_mux_0|Mux16~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~5_combout ;
wire \datapath_0|datamem_module_0|output_data~285_combout ;
wire \datapath_0|datamem_module_0|output_data~286_combout ;
wire \datapath_0|datamem_module_0|output_data~287_combout ;
wire \datapath_0|datamem_module_0|output_data~288_combout ;
wire \datapath_0|datamem_module_0|output_data~289_combout ;
wire \datapath_0|datamem_module_0|output_data~290_combout ;
wire \datapath_0|datamem_module_0|output_data~291_combout ;
wire \datapath_0|datamem_module_0|output_data~292_combout ;
wire \datapath_0|datamem_module_0|output_data~293_combout ;
wire \datapath_0|Add1~22_combout ;
wire \datapath_0|mux_0|Mux18~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux18~1_combout ;
wire \datapath_0|forward_mux_0|Mux18~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~3_combout ;
wire \datapath_0|datamem_module_0|output_data~243_combout ;
wire \datapath_0|datamem_module_0|output_data~244_combout ;
wire \datapath_0|datamem_module_0|output_data~245_combout ;
wire \datapath_0|datamem_module_0|output_data~246_combout ;
wire \datapath_0|datamem_module_0|output_data~247_combout ;
wire \datapath_0|datamem_module_0|output_data~248_combout ;
wire \datapath_0|datamem_module_0|output_data~249_combout ;
wire \datapath_0|datamem_module_0|output_data~250_combout ;
wire \datapath_0|datamem_module_0|output_data~251_combout ;
wire \datapath_0|Add1~18_combout ;
wire \datapath_0|mux_0|Mux20~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux20~1_combout ;
wire \datapath_0|forward_mux_0|Mux20~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~1_combout ;
wire \datapath_0|datamem_module_0|output_data~201_combout ;
wire \datapath_0|datamem_module_0|output_data~202_combout ;
wire \datapath_0|datamem_module_0|output_data~203_combout ;
wire \datapath_0|datamem_module_0|output_data~204_combout ;
wire \datapath_0|datamem_module_0|output_data~205_combout ;
wire \datapath_0|datamem_module_0|output_data~206_combout ;
wire \datapath_0|datamem_module_0|output_data~207_combout ;
wire \datapath_0|datamem_module_0|output_data~208_combout ;
wire \datapath_0|datamem_module_0|output_data~209_combout ;
wire \datapath_0|Add1~14_combout ;
wire \datapath_0|mux_0|Mux22~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux22~1_combout ;
wire \datapath_0|forward_mux_0|Mux22~0_combout ;
wire \datapath_0|datamem_module_0|memory_input_0[7]~7_combout ;
wire \datapath_0|datamem_module_0|output_data~159_combout ;
wire \datapath_0|datamem_module_0|output_data~160_combout ;
wire \datapath_0|datamem_module_0|output_data~161_combout ;
wire \datapath_0|datamem_module_0|output_data~162_combout ;
wire \datapath_0|datamem_module_0|output_data~163_combout ;
wire \datapath_0|datamem_module_0|output_data~164_combout ;
wire \datapath_0|datamem_module_0|output_data~165_combout ;
wire \datapath_0|datamem_module_0|output_data~166_combout ;
wire \datapath_0|datamem_module_0|output_data~167_combout ;
wire \datapath_0|Add1~10_combout ;
wire \datapath_0|mux_0|Mux24~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux24~1_combout ;
wire \datapath_0|forward_mux_0|Mux24~0_combout ;
wire \datapath_0|ALU_0|Add0~47 ;
wire \datapath_0|ALU_0|Add0~48_combout ;
wire \datapath_0|forward_mux_0|Mux24~1_combout ;
wire \datapath_0|forward_mux_0|Mux24~2_combout ;
wire \datapath_0|ALU_0|Add0~49 ;
wire \datapath_0|ALU_0|Add0~50_combout ;
wire \datapath_0|Add1~12_combout ;
wire \datapath_0|mux_0|Mux23~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux23~1_combout ;
wire \datapath_0|forward_mux_0|Mux23~0_combout ;
wire \datapath_0|forward_mux_0|Mux23~1_combout ;
wire \datapath_0|forward_mux_0|Mux23~2_combout ;
wire \datapath_0|ALU_0|Add0~51 ;
wire \datapath_0|ALU_0|Add0~52_combout ;
wire \datapath_0|forward_mux_0|Mux22~1_combout ;
wire \datapath_0|forward_mux_0|Mux22~2_combout ;
wire \datapath_0|ALU_0|Add0~53 ;
wire \datapath_0|ALU_0|Add0~54_combout ;
wire \datapath_0|Add1~16_combout ;
wire \datapath_0|mux_0|Mux21~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux21~1_combout ;
wire \datapath_0|forward_mux_0|Mux21~0_combout ;
wire \datapath_0|forward_mux_0|Mux21~1_combout ;
wire \datapath_0|forward_mux_0|Mux21~2_combout ;
wire \datapath_0|ALU_0|Add0~55 ;
wire \datapath_0|ALU_0|Add0~56_combout ;
wire \datapath_0|forward_mux_0|Mux20~1_combout ;
wire \datapath_0|forward_mux_0|Mux20~2_combout ;
wire \datapath_0|ALU_0|Add0~57 ;
wire \datapath_0|ALU_0|Add0~58_combout ;
wire \datapath_0|Add1~20_combout ;
wire \datapath_0|mux_0|Mux19~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux19~1_combout ;
wire \datapath_0|forward_mux_0|Mux19~0_combout ;
wire \datapath_0|forward_mux_0|Mux19~1_combout ;
wire \datapath_0|forward_mux_0|Mux19~2_combout ;
wire \datapath_0|ALU_0|Add0~59 ;
wire \datapath_0|ALU_0|Add0~60_combout ;
wire \datapath_0|forward_mux_0|Mux18~1_combout ;
wire \datapath_0|forward_mux_0|Mux18~2_combout ;
wire \datapath_0|ALU_0|Add0~61 ;
wire \datapath_0|ALU_0|Add0~62_combout ;
wire \datapath_0|Add1~24_combout ;
wire \datapath_0|mux_0|Mux17~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux17~1_combout ;
wire \datapath_0|forward_mux_0|Mux17~0_combout ;
wire \datapath_0|forward_mux_0|Mux17~1_combout ;
wire \datapath_0|forward_mux_0|Mux17~2_combout ;
wire \datapath_0|ALU_0|Add0~63 ;
wire \datapath_0|ALU_0|Add0~64_combout ;
wire \datapath_0|forward_mux_0|Mux16~1_combout ;
wire \datapath_0|forward_mux_0|Mux16~2_combout ;
wire \datapath_0|ALU_0|Add0~65 ;
wire \datapath_0|ALU_0|Add0~66_combout ;
wire \datapath_0|Add1~28_combout ;
wire \datapath_0|mux_0|Mux15~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux15~1_combout ;
wire \datapath_0|forward_mux_0|Mux15~0_combout ;
wire \datapath_0|forward_mux_0|Mux15~1_combout ;
wire \datapath_0|forward_mux_0|Mux15~2_combout ;
wire \datapath_0|ALU_0|Add0~67 ;
wire \datapath_0|ALU_0|Add0~68_combout ;
wire \datapath_0|forward_mux_0|Mux14~1_combout ;
wire \datapath_0|forward_mux_0|Mux14~2_combout ;
wire \datapath_0|ALU_0|Add0~69 ;
wire \datapath_0|ALU_0|Add0~70_combout ;
wire \datapath_0|Add1~32_combout ;
wire \datapath_0|mux_0|Mux13~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux13~1_combout ;
wire \datapath_0|forward_mux_0|Mux13~0_combout ;
wire \datapath_0|forward_mux_0|Mux13~1_combout ;
wire \datapath_0|forward_mux_0|Mux13~2_combout ;
wire \datapath_0|ALU_0|Add0~71 ;
wire \datapath_0|ALU_0|Add0~72_combout ;
wire \datapath_0|forward_mux_0|Mux12~1_combout ;
wire \datapath_0|forward_mux_0|Mux12~2_combout ;
wire \datapath_0|ALU_0|Add0~73 ;
wire \datapath_0|ALU_0|Add0~74_combout ;
wire \datapath_0|Add1~36_combout ;
wire \datapath_0|mux_0|Mux11~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux11~1_combout ;
wire \datapath_0|forward_mux_0|Mux11~0_combout ;
wire \datapath_0|forward_mux_0|Mux11~1_combout ;
wire \datapath_0|forward_mux_0|Mux11~2_combout ;
wire \datapath_0|ALU_0|Add0~75 ;
wire \datapath_0|ALU_0|Add0~76_combout ;
wire \datapath_0|forward_mux_0|Mux10~1_combout ;
wire \datapath_0|forward_mux_0|Mux10~2_combout ;
wire \datapath_0|ALU_0|Add0~77 ;
wire \datapath_0|ALU_0|Add0~78_combout ;
wire \datapath_0|Add1~40_combout ;
wire \datapath_0|mux_0|Mux9~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux9~1_combout ;
wire \datapath_0|forward_mux_0|Mux9~0_combout ;
wire \datapath_0|forward_mux_0|Mux9~1_combout ;
wire \datapath_0|forward_mux_0|Mux9~2_combout ;
wire \datapath_0|ALU_0|Add0~79 ;
wire \datapath_0|ALU_0|Add0~80_combout ;
wire \datapath_0|forward_mux_0|Mux8~1_combout ;
wire \datapath_0|forward_mux_0|Mux8~2_combout ;
wire \datapath_0|ALU_0|Add0~81 ;
wire \datapath_0|ALU_0|Add0~82_combout ;
wire \datapath_0|Add1~44_combout ;
wire \datapath_0|mux_0|Mux7~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux7~1_combout ;
wire \datapath_0|forward_mux_0|Mux7~0_combout ;
wire \datapath_0|forward_mux_0|Mux7~1_combout ;
wire \datapath_0|forward_mux_0|Mux7~2_combout ;
wire \datapath_0|ALU_0|Add0~83 ;
wire \datapath_0|ALU_0|Add0~84_combout ;
wire \datapath_0|forward_mux_0|Mux6~1_combout ;
wire \datapath_0|forward_mux_0|Mux6~2_combout ;
wire \datapath_0|ALU_0|Add0~85 ;
wire \datapath_0|ALU_0|Add0~86_combout ;
wire \datapath_0|Add1~48_combout ;
wire \datapath_0|mux_0|Mux5~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux5~1_combout ;
wire \datapath_0|forward_mux_0|Mux5~0_combout ;
wire \datapath_0|forward_mux_0|Mux5~1_combout ;
wire \datapath_0|forward_mux_0|Mux5~2_combout ;
wire \datapath_0|ALU_0|Add0~87 ;
wire \datapath_0|ALU_0|Add0~88_combout ;
wire \datapath_0|forward_mux_0|Mux4~1_combout ;
wire \datapath_0|forward_mux_0|Mux4~2_combout ;
wire \datapath_0|ALU_0|Add0~89 ;
wire \datapath_0|ALU_0|Add0~90_combout ;
wire \datapath_0|Add1~52_combout ;
wire \datapath_0|mux_0|Mux3~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux3~1_combout ;
wire \datapath_0|forward_mux_0|Mux3~0_combout ;
wire \datapath_0|forward_mux_0|Mux3~1_combout ;
wire \datapath_0|forward_mux_0|Mux3~2_combout ;
wire \datapath_0|ALU_0|Add0~91 ;
wire \datapath_0|ALU_0|Add0~92_combout ;
wire \datapath_0|forward_mux_0|Mux2~1_combout ;
wire \datapath_0|forward_mux_0|Mux2~2_combout ;
wire \datapath_0|ALU_0|Add0~93 ;
wire \datapath_0|ALU_0|Add0~94_combout ;
wire \datapath_0|Add1~56_combout ;
wire \datapath_0|mux_0|Mux1~1_combout ;
wire \datapath_0|register_file_0|output_1_mux|Mux1~1_combout ;
wire \datapath_0|forward_mux_0|Mux1~0_combout ;
wire \datapath_0|forward_mux_0|Mux1~1_combout ;
wire \datapath_0|forward_mux_0|Mux1~2_combout ;
wire \datapath_0|ALU_0|Add0~95 ;
wire \datapath_0|ALU_0|Add0~96_combout ;
wire \datapath_0|forward_mux_0|Mux0~1_combout ;
wire \datapath_0|forward_mux_0|Mux0~2_combout ;
wire \datapath_0|ALU_0|Add0~97 ;
wire \datapath_0|ALU_0|Add0~98_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~0_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~1_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~7_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~8_combout ;
wire \datapath_0|comb~0_combout ;
wire \datapath_0|comb~1_combout ;
wire \datapath_0|comb~2_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[5]~37 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[6]~38_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~11 ;
wire \datapath_0|JTU_0|internal_adder|Add0~12_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0_combout ;
wire \controller_0|Selector29~0_combout ;
wire \controller_0|Selector29~1_combout ;
wire \controller_0|Selector29~2_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~3 ;
wire \datapath_0|JTU_0|internal_adder|Add0~4_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0_combout ;
wire \controller_0|Selector30~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~5 ;
wire \datapath_0|JTU_0|internal_adder|Add0~6_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1_combout ;
wire \controller_0|Equal0~0_combout ;
wire \controller_0|decoded_cluster.JALR_1876~combout ;
wire \controller_0|internal_immediate~0_combout ;
wire \datapath_0|ID_EX_PLR|jump_flag_reg|reg_out~q ;
wire \datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out~q ;
wire \datapath_0|ALU_0|ALU_branch_response~3_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~4_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~5_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~6_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~9_combout ;
wire \datapath_0|ALU_0|ALU_branch_response~10_combout ;
wire \datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out~q ;
wire \datapath_0|comb~3_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1_combout ;
wire \controller_0|Mux42~0_combout ;
wire \controller_0|decoded_cluster.STORE_1912~combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0_combout ;
wire \controller_0|Selector27~1_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~0_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[6]~39 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[7]~40_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~13 ;
wire \datapath_0|JTU_0|internal_adder|Add0~14_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[7]~41 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[8]~42_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~15 ;
wire \datapath_0|JTU_0|internal_adder|Add0~16_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[8]~43 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[9]~44_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~17 ;
wire \datapath_0|JTU_0|internal_adder|Add0~18_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[9]~45 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[10]~46_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~19 ;
wire \datapath_0|JTU_0|internal_adder|Add0~20_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[10]~47 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[11]~48_combout ;
wire \controller_0|decoded_cluster.JAL_1846~combout ;
wire \controller_0|Selector49~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~21 ;
wire \datapath_0|JTU_0|internal_adder|Add0~22_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[11]~49 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[12]~50_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~23 ;
wire \datapath_0|JTU_0|internal_adder|Add0~24_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[12]~51 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[13]~52_combout ;
wire \controller_0|Selector30~1_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~25 ;
wire \datapath_0|JTU_0|internal_adder|Add0~26_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[13]~53 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[14]~54_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~27 ;
wire \datapath_0|JTU_0|internal_adder|Add0~28_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[14]~55 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[15]~56_combout ;
wire \controller_0|Selector56~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~29 ;
wire \datapath_0|JTU_0|internal_adder|Add0~30_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[15]~57 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[16]~58_combout ;
wire \controller_0|Selector57~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~31 ;
wire \datapath_0|JTU_0|internal_adder|Add0~32_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[16]~59 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[17]~60_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~33 ;
wire \datapath_0|JTU_0|internal_adder|Add0~34_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[17]~61 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[18]~62_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~35 ;
wire \datapath_0|JTU_0|internal_adder|Add0~36_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[18]~63 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[19]~64_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~37 ;
wire \datapath_0|JTU_0|internal_adder|Add0~38_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[19]~65 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[20]~66_combout ;
wire \controller_0|Selector62~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~39 ;
wire \datapath_0|JTU_0|internal_adder|Add0~40_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[20]~67 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[21]~68_combout ;
wire \controller_0|Selector63~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~41 ;
wire \datapath_0|JTU_0|internal_adder|Add0~42_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[21]~69 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[22]~70_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~43 ;
wire \datapath_0|JTU_0|internal_adder|Add0~44_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[22]~71 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[23]~72_combout ;
wire \controller_0|Selector65~0_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~45 ;
wire \datapath_0|JTU_0|internal_adder|Add0~46_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[23]~73 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[24]~74_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~47 ;
wire \datapath_0|JTU_0|internal_adder|Add0~48_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[24]~75 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[25]~76_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~49 ;
wire \datapath_0|JTU_0|internal_adder|Add0~50_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[25]~77 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[26]~78_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~51 ;
wire \datapath_0|JTU_0|internal_adder|Add0~52_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[26]~79 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[27]~80_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~53 ;
wire \datapath_0|JTU_0|internal_adder|Add0~54_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[27]~81 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[28]~82_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~55 ;
wire \datapath_0|JTU_0|internal_adder|Add0~56_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[28]~83 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[29]~84_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~57 ;
wire \datapath_0|JTU_0|internal_adder|Add0~58_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[29]~85 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[30]~86_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~59 ;
wire \datapath_0|JTU_0|internal_adder|Add0~60_combout ;
wire \datapath_0|program_counter_0|internal_register|internal_value[30]~87 ;
wire \datapath_0|program_counter_0|internal_register|internal_value[31]~88_combout ;
wire \datapath_0|JTU_0|internal_adder|Add0~61 ;
wire \datapath_0|JTU_0|internal_adder|Add0~62_combout ;
wire \datapath_0|register_file_0|internal_reg_load[31]~2_combout ;
wire \datapath_0|register_file_0|internal_reg_load[31]~3_combout ;
wire \datapath_0|register_file_0|internal_reg_load[1]~4_combout ;
wire \controller_0|Selector87~0_combout ;
wire \controller_0|Selector86~0_combout ;
wire \datapath_0|FU_0|Equal7~0_combout ;
wire \controller_0|Selector89~0_combout ;
wire \datapath_0|FU_0|Equal7~1_combout ;
wire \datapath_0|FU_0|Equal9~0_combout ;
wire \datapath_0|FU_0|forward_1~3_combout ;
wire \datapath_0|register_file_0|internal_reg_load[11]~1_combout ;
wire \datapath_0|FU_0|forward_1~4_combout ;
wire \datapath_0|FU_0|forward_1~5_combout ;
wire \datapath_0|FU_0|forward_1~6_combout ;
wire \datapath_0|FU_0|forward_mux_1_control[1]~0_combout ;
wire \datapath_0|FU_0|forward_1~2_combout ;
wire \datapath_0|FU_0|forward_mux_1_control[0]~1_combout ;
wire \datapath_0|register_file_0|internal_reg_load[3]~6_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~0_combout ;
wire \datapath_0|register_file_0|internal_reg_load[9]~8_combout ;
wire \datapath_0|register_file_0|internal_reg_load[8]~9_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux31~0_combout ;
wire \datapath_0|register_file_0|internal_reg_load[11]~10_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux31~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux31~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux31~3_combout ;
wire \datapath_0|forward_mux_1|Mux31~0_combout ;
wire \datapath_0|forward_mux_1|Mux31~1_combout ;
wire \datapath_0|forward_mux_1|Mux31~2_combout ;
wire \datapath_0|forward_mux_1|Mux31~3_combout ;
wire \controller_0|WideOr29~0_combout ;
wire \controller_0|internal_mux1_sel~combout ;
wire \datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ;
wire \datapath_0|mux_1|output_0[0]~0_combout ;
wire \datapath_0|register_file_0|internal_reg_load[10]~7_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux30~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux30~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux30~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux30~3_combout ;
wire \datapath_0|forward_mux_1|Mux30~0_combout ;
wire \datapath_0|forward_mux_1|Mux30~1_combout ;
wire \datapath_0|forward_mux_1|Mux30~2_combout ;
wire \datapath_0|mux_1|output_0[1]~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux29~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux29~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux29~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux29~3_combout ;
wire \datapath_0|forward_mux_1|Mux29~0_combout ;
wire \datapath_0|forward_mux_1|Mux29~1_combout ;
wire \datapath_0|forward_mux_1|Mux29~2_combout ;
wire \datapath_0|mux_1|output_0[2]~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux28~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux28~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux28~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux28~3_combout ;
wire \datapath_0|forward_mux_1|Mux28~0_combout ;
wire \datapath_0|forward_mux_1|Mux28~1_combout ;
wire \datapath_0|forward_mux_1|Mux28~2_combout ;
wire \datapath_0|mux_1|output_0[3]~3_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux27~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux27~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux27~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux27~3_combout ;
wire \datapath_0|forward_mux_1|Mux27~0_combout ;
wire \datapath_0|forward_mux_1|Mux27~1_combout ;
wire \datapath_0|forward_mux_1|Mux27~2_combout ;
wire \datapath_0|mux_1|output_0[4]~4_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux26~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux26~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux26~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux26~3_combout ;
wire \datapath_0|forward_mux_1|Mux26~0_combout ;
wire \datapath_0|forward_mux_1|Mux26~1_combout ;
wire \datapath_0|forward_mux_1|Mux26~2_combout ;
wire \datapath_0|mux_1|output_0[5]~5_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux25~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux25~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux25~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux25~3_combout ;
wire \datapath_0|forward_mux_1|Mux25~0_combout ;
wire \datapath_0|forward_mux_1|Mux25~1_combout ;
wire \datapath_0|forward_mux_1|Mux25~2_combout ;
wire \datapath_0|mux_1|output_0[6]~6_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux24~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux24~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux24~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux24~3_combout ;
wire \datapath_0|forward_mux_1|Mux24~0_combout ;
wire \datapath_0|forward_mux_1|Mux24~1_combout ;
wire \datapath_0|mux_1|output_0[7]~7_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~0_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~0_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~8_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ;
wire \datapath_0|datamem_module_0|output_data~180_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~13_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ;
wire \datapath_0|datamem_module_0|output_data~181_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~6_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ;
wire \datapath_0|datamem_module_0|output_data~182_combout ;
wire \datapath_0|datamem_module_0|output_data~183_combout ;
wire \datapath_0|datamem_module_0|output_data~184_combout ;
wire \datapath_0|datamem_module_0|datamem_0|Ram0~3_combout ;
wire \datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ;
wire \datapath_0|datamem_module_0|output_data~185_combout ;
wire \datapath_0|datamem_module_0|output_data~186_combout ;
wire \datapath_0|datamem_module_0|output_data~187_combout ;
wire \datapath_0|datamem_module_0|output_data~188_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux23~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux23~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux23~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux23~3_combout ;
wire \datapath_0|forward_mux_1|Mux23~0_combout ;
wire \datapath_0|forward_mux_1|Mux23~1_combout ;
wire \datapath_0|mux_1|output_0[8]~8_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux22~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux22~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux22~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux22~3_combout ;
wire \datapath_0|forward_mux_1|Mux22~0_combout ;
wire \datapath_0|forward_mux_1|Mux22~1_combout ;
wire \datapath_0|mux_1|output_0[9]~9_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~2_combout ;
wire \datapath_0|datamem_module_0|output_data~222_combout ;
wire \datapath_0|datamem_module_0|output_data~223_combout ;
wire \datapath_0|datamem_module_0|output_data~224_combout ;
wire \datapath_0|datamem_module_0|output_data~225_combout ;
wire \datapath_0|datamem_module_0|output_data~226_combout ;
wire \datapath_0|datamem_module_0|output_data~227_combout ;
wire \datapath_0|datamem_module_0|output_data~228_combout ;
wire \datapath_0|datamem_module_0|output_data~229_combout ;
wire \datapath_0|datamem_module_0|output_data~230_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux21~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux21~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux21~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux21~3_combout ;
wire \datapath_0|forward_mux_1|Mux21~0_combout ;
wire \datapath_0|forward_mux_1|Mux21~1_combout ;
wire \datapath_0|mux_1|output_0[10]~10_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~3_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~4_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~5_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux20~6_combout ;
wire \datapath_0|forward_mux_1|Mux20~0_combout ;
wire \datapath_0|forward_mux_1|Mux20~1_combout ;
wire \datapath_0|forward_mux_1|Mux20~2_combout ;
wire \datapath_0|mux_1|output_0[11]~11_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~4_combout ;
wire \datapath_0|datamem_module_0|output_data~264_combout ;
wire \datapath_0|datamem_module_0|output_data~265_combout ;
wire \datapath_0|datamem_module_0|output_data~266_combout ;
wire \datapath_0|datamem_module_0|output_data~267_combout ;
wire \datapath_0|datamem_module_0|output_data~268_combout ;
wire \datapath_0|datamem_module_0|output_data~269_combout ;
wire \datapath_0|datamem_module_0|output_data~270_combout ;
wire \datapath_0|datamem_module_0|output_data~271_combout ;
wire \datapath_0|datamem_module_0|output_data~272_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux19~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux19~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux19~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux19~3_combout ;
wire \datapath_0|forward_mux_1|Mux19~0_combout ;
wire \datapath_0|forward_mux_1|Mux19~1_combout ;
wire \datapath_0|mux_1|output_0[12]~12_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux18~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux18~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux18~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux18~3_combout ;
wire \datapath_0|forward_mux_1|Mux18~0_combout ;
wire \datapath_0|forward_mux_1|Mux18~1_combout ;
wire \datapath_0|forward_mux_1|Mux18~2_combout ;
wire \datapath_0|mux_1|output_0[13]~13_combout ;
wire \datapath_0|datamem_module_0|memory_input_1~6_combout ;
wire \datapath_0|datamem_module_0|output_data~306_combout ;
wire \datapath_0|datamem_module_0|output_data~307_combout ;
wire \datapath_0|datamem_module_0|output_data~308_combout ;
wire \datapath_0|datamem_module_0|output_data~309_combout ;
wire \datapath_0|datamem_module_0|output_data~310_combout ;
wire \datapath_0|datamem_module_0|output_data~311_combout ;
wire \datapath_0|datamem_module_0|output_data~312_combout ;
wire \datapath_0|datamem_module_0|output_data~313_combout ;
wire \datapath_0|datamem_module_0|output_data~314_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux17~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux17~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux17~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux17~3_combout ;
wire \datapath_0|forward_mux_1|Mux17~0_combout ;
wire \datapath_0|forward_mux_1|Mux17~1_combout ;
wire \datapath_0|mux_1|output_0[14]~14_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux16~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux16~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux16~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux16~3_combout ;
wire \datapath_0|forward_mux_1|Mux16~0_combout ;
wire \datapath_0|forward_mux_1|Mux16~1_combout ;
wire \datapath_0|forward_mux_1|Mux16~2_combout ;
wire \datapath_0|mux_1|output_0[15]~15_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux15~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux15~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux15~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux15~3_combout ;
wire \datapath_0|forward_mux_1|Mux15~0_combout ;
wire \datapath_0|forward_mux_1|Mux15~1_combout ;
wire \datapath_0|forward_mux_1|Mux15~2_combout ;
wire \datapath_0|mux_1|output_0[16]~16_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux14~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux14~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux14~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux14~3_combout ;
wire \datapath_0|forward_mux_1|Mux14~0_combout ;
wire \datapath_0|forward_mux_1|Mux14~1_combout ;
wire \datapath_0|mux_1|output_0[17]~17_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~2_combout ;
wire \datapath_0|datamem_module_0|output_data~390_combout ;
wire \datapath_0|datamem_module_0|output_data~391_combout ;
wire \datapath_0|datamem_module_0|output_data~392_combout ;
wire \datapath_0|datamem_module_0|output_data~393_combout ;
wire \datapath_0|datamem_module_0|output_data~394_combout ;
wire \datapath_0|datamem_module_0|output_data~395_combout ;
wire \datapath_0|datamem_module_0|output_data~396_combout ;
wire \datapath_0|datamem_module_0|output_data~397_combout ;
wire \datapath_0|datamem_module_0|output_data~398_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux13~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux13~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux13~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux13~3_combout ;
wire \datapath_0|forward_mux_1|Mux13~0_combout ;
wire \datapath_0|forward_mux_1|Mux13~1_combout ;
wire \datapath_0|mux_1|output_0[18]~18_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux12~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux12~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux12~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux12~3_combout ;
wire \datapath_0|forward_mux_1|Mux12~0_combout ;
wire \datapath_0|forward_mux_1|Mux12~1_combout ;
wire \datapath_0|mux_1|output_0[19]~19_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux11~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux11~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux11~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux11~3_combout ;
wire \datapath_0|forward_mux_1|Mux11~0_combout ;
wire \datapath_0|forward_mux_1|Mux11~1_combout ;
wire \datapath_0|forward_mux_1|Mux11~2_combout ;
wire \datapath_0|mux_1|output_0[20]~20_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux10~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux10~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux10~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux10~3_combout ;
wire \datapath_0|forward_mux_1|Mux10~0_combout ;
wire \datapath_0|forward_mux_1|Mux10~1_combout ;
wire \datapath_0|forward_mux_1|Mux10~2_combout ;
wire \datapath_0|mux_1|output_0[21]~21_combout ;
wire \datapath_0|datamem_module_0|memory_input_2~6_combout ;
wire \datapath_0|datamem_module_0|output_data~474_combout ;
wire \datapath_0|datamem_module_0|output_data~475_combout ;
wire \datapath_0|datamem_module_0|output_data~476_combout ;
wire \datapath_0|datamem_module_0|output_data~477_combout ;
wire \datapath_0|datamem_module_0|output_data~478_combout ;
wire \datapath_0|datamem_module_0|output_data~479_combout ;
wire \datapath_0|datamem_module_0|output_data~480_combout ;
wire \datapath_0|datamem_module_0|output_data~481_combout ;
wire \datapath_0|datamem_module_0|output_data~482_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux9~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux9~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux9~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux9~3_combout ;
wire \datapath_0|forward_mux_1|Mux9~0_combout ;
wire \datapath_0|forward_mux_1|Mux9~1_combout ;
wire \datapath_0|mux_1|output_0[22]~22_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux8~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux8~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux8~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux8~3_combout ;
wire \datapath_0|forward_mux_1|Mux8~0_combout ;
wire \datapath_0|forward_mux_1|Mux8~1_combout ;
wire \datapath_0|forward_mux_1|Mux8~2_combout ;
wire \datapath_0|mux_1|output_0[23]~23_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~0_combout ;
wire \datapath_0|datamem_module_0|output_data~516_combout ;
wire \datapath_0|datamem_module_0|output_data~517_combout ;
wire \datapath_0|datamem_module_0|output_data~518_combout ;
wire \datapath_0|datamem_module_0|output_data~519_combout ;
wire \datapath_0|datamem_module_0|output_data~520_combout ;
wire \datapath_0|datamem_module_0|output_data~521_combout ;
wire \datapath_0|datamem_module_0|output_data~522_combout ;
wire \datapath_0|datamem_module_0|output_data~523_combout ;
wire \datapath_0|datamem_module_0|output_data~524_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux7~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux7~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux7~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux7~3_combout ;
wire \datapath_0|forward_mux_1|Mux7~0_combout ;
wire \datapath_0|forward_mux_1|Mux7~1_combout ;
wire \datapath_0|mux_1|output_0[24]~24_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux6~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux6~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux6~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux6~3_combout ;
wire \datapath_0|forward_mux_1|Mux6~0_combout ;
wire \datapath_0|forward_mux_1|Mux6~1_combout ;
wire \datapath_0|mux_1|output_0[25]~25_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~2_combout ;
wire \datapath_0|datamem_module_0|output_data~558_combout ;
wire \datapath_0|datamem_module_0|output_data~559_combout ;
wire \datapath_0|datamem_module_0|output_data~560_combout ;
wire \datapath_0|datamem_module_0|output_data~561_combout ;
wire \datapath_0|datamem_module_0|output_data~562_combout ;
wire \datapath_0|datamem_module_0|output_data~563_combout ;
wire \datapath_0|datamem_module_0|output_data~564_combout ;
wire \datapath_0|datamem_module_0|output_data~565_combout ;
wire \datapath_0|datamem_module_0|output_data~566_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux5~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux5~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux5~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux5~3_combout ;
wire \datapath_0|forward_mux_1|Mux5~0_combout ;
wire \datapath_0|forward_mux_1|Mux5~1_combout ;
wire \datapath_0|mux_1|output_0[26]~26_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux4~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux4~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux4~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux4~3_combout ;
wire \datapath_0|forward_mux_1|Mux4~0_combout ;
wire \datapath_0|forward_mux_1|Mux4~1_combout ;
wire \datapath_0|mux_1|output_0[27]~27_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~4_combout ;
wire \datapath_0|datamem_module_0|output_data~600_combout ;
wire \datapath_0|datamem_module_0|output_data~601_combout ;
wire \datapath_0|datamem_module_0|output_data~602_combout ;
wire \datapath_0|datamem_module_0|output_data~603_combout ;
wire \datapath_0|datamem_module_0|output_data~604_combout ;
wire \datapath_0|datamem_module_0|output_data~605_combout ;
wire \datapath_0|datamem_module_0|output_data~606_combout ;
wire \datapath_0|datamem_module_0|output_data~607_combout ;
wire \datapath_0|datamem_module_0|output_data~608_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux3~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux3~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux3~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux3~3_combout ;
wire \datapath_0|forward_mux_1|Mux3~0_combout ;
wire \datapath_0|forward_mux_1|Mux3~1_combout ;
wire \datapath_0|mux_1|output_0[28]~28_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux2~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux2~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux2~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux2~3_combout ;
wire \datapath_0|forward_mux_1|Mux2~0_combout ;
wire \datapath_0|forward_mux_1|Mux2~1_combout ;
wire \datapath_0|mux_1|output_0[29]~29_combout ;
wire \datapath_0|datamem_module_0|memory_input_3~6_combout ;
wire \datapath_0|datamem_module_0|output_data~642_combout ;
wire \datapath_0|datamem_module_0|output_data~643_combout ;
wire \datapath_0|datamem_module_0|output_data~644_combout ;
wire \datapath_0|datamem_module_0|output_data~645_combout ;
wire \datapath_0|datamem_module_0|output_data~646_combout ;
wire \datapath_0|datamem_module_0|output_data~647_combout ;
wire \datapath_0|datamem_module_0|output_data~648_combout ;
wire \datapath_0|datamem_module_0|output_data~649_combout ;
wire \datapath_0|datamem_module_0|output_data~650_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux1~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux1~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux1~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux1~3_combout ;
wire \datapath_0|forward_mux_1|Mux1~0_combout ;
wire \datapath_0|forward_mux_1|Mux1~1_combout ;
wire \datapath_0|mux_1|output_0[30]~30_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux0~0_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux0~1_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux0~2_combout ;
wire \datapath_0|register_file_0|output_2_mux|Mux0~3_combout ;
wire \datapath_0|forward_mux_1|Mux0~0_combout ;
wire \datapath_0|forward_mux_1|Mux0~1_combout ;
wire \datapath_0|mux_1|output_0[31]~31_combout ;
wire \datapath_0|FU_0|forward_0~3_combout ;
wire \datapath_0|FU_0|forward_1~7_combout ;
wire \datapath_0|FU_0|Equal2~2_combout ;
wire \datapath_0|FU_0|forward_mux_0_control[2]~2_combout ;
wire \datapath_0|FU_0|forward_mux_1_control[2]~2_combout ;
wire \datapath_0|FU_0|forward_mux_1_control[2]~3_combout ;
wire \datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0_combout ;
wire \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0_combout ;
wire [31:0] \datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value ;
wire [31:0] \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value ;
wire [31:0] \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x1|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x2|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x3|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x8|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x9|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x10|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x11|internal_value ;
wire [31:0] \datapath_0|register_file_0|reg_x31|internal_value ;
wire [31:0] \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value ;
wire [31:0] \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value ;
wire [31:0] \datapath_0|ID_EX_PLR|immediate_reg|internal_value ;
wire [31:0] \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value ;
wire [4:0] \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value ;
wire [4:0] \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value ;
wire [1:0] \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value ;
wire [4:0] \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value ;
wire [31:0] \datapath_0|ALU_0|ALU_output ;
wire [31:0] \datapath_0|datamem_module_0|output_data ;
wire [7:0] \datapath_0|datamem_module_0|memory_input_3 ;
wire [7:0] \datapath_0|datamem_module_0|memory_input_2 ;
wire [7:0] \datapath_0|datamem_module_0|memory_input_1 ;
wire [7:0] \datapath_0|datamem_module_0|memory_input_0 ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value ;
wire [1:0] \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value ;
wire [4:0] \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value ;
wire [31:0] \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value ;
wire [31:0] \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value ;
wire [31:0] \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value ;
wire [7:0] \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value ;
wire [1:0] \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value ;
wire [4:0] \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value ;
wire [31:0] \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value ;
wire [31:0] \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value ;
wire [31:0] \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value ;
wire [4:0] \controller_0|internal_reg_file_write_address ;
wire [4:0] \controller_0|internal_reg_file_read_address_1 ;
wire [4:0] \controller_0|internal_reg_file_read_address_0 ;
wire [1:0] \controller_0|internal_mux0_sel ;
wire [31:0] \controller_0|internal_immediate ;
wire [31:0] \datapath_0|program_counter_0|internal_register|internal_value ;


dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[3]~0 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[3]~0_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q  & (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[3]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[3]~0 .lut_mask = 16'h0002;
defparam \datapath_0|register_file_0|internal_reg_load[3]~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal2~0 (
// Equation(s):
// \datapath_0|FU_0|Equal2~0_combout  = (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0] & (\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0] & 
// (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1] $ (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1])))) # (!\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0] & 
// (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0] & (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1] $ (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]))))

	.dataa(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]),
	.datab(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]),
	.datad(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal2~0 .lut_mask = 16'h8241;
defparam \datapath_0|FU_0|Equal2~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux31~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux31~2_combout  = (\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|FU_0|forward_0~3_combout  & ((!\datapath_0|FU_0|forward_1~1_combout ) # (!\datapath_0|FU_0|forward_0~2_combout ))))

	.dataa(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datab(\datapath_0|FU_0|forward_0~3_combout ),
	.datac(\datapath_0|FU_0|forward_0~2_combout ),
	.datad(\datapath_0|FU_0|forward_1~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux31~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux31~2 .lut_mask = 16'h0888;
defparam \datapath_0|forward_mux_0|Mux31~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [11]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [13]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [15]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [16]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [20]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [21]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [23]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux31~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux31~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [0])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [0])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [0]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [0]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux31~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux30~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux30~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [1])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [1])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [1]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux30~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux29~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux29~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [2])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [2])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [2]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [2]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux29~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux28~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux28~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [3])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [3])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [3]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [3]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux28~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux28~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux28~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux27~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux27~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [4])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [4])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [4]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [4]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux27~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux26~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux26~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [5])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [5])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [5]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [5]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux26~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux25~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux25~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [6])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [6])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [6]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [6]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux25~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux24~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux24~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [7])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [7])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [7]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [7]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux24~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux23~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux23~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [8])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [8])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [8]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [8]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux23~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux22~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux22~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [9])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [9])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [9]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [9]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux22~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux22~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux22~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux21~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux21~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [10])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [10])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [10]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [10]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux21~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux20~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux20~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [11])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [11])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [11]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [11]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux20~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux20~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux20~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux19~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux19~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [12])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [12])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [12]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [12]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux19~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux19~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux19~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux18~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux18~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [13])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [13])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [13]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [13]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux18~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux18~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux18~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux17~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux17~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [14])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [14])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [14]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [14]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux17~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux17~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux17~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux16~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux16~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [15])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [15])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [15]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [15]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux16~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux15~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux15~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [16])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [16])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [16]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [16]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux15~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux14~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux14~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [17])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [17])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [17]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [17]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux14~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux14~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux14~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux13~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux13~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [18])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [18])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [18]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [18]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux13~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux13~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux13~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux12~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux12~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [19])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [19])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [19]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [19]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux12~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux12~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux12~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux11~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux11~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [20])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [20])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [20]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [20]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux11~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux10~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux10~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [21])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [21])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [21]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [21]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux10~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux9~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux9~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [22])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [22])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [22]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [22]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux9~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux9~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux8~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux8~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [23])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [23])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [23]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [23]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux8~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux7~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux7~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [24])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [24])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [24]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [24]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux7~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux7~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux6~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux6~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [25])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [25])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [25]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [25]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux6~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux6~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux6~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux5~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux5~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [26])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [26])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [26]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [26]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux5~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux5~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux5~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux4~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux4~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [27])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [27])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [27]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [27]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux4~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux4~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux4~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux3~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux3~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [28])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [28])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [28]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [28]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux3~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux3~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux2~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux2~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [29])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [29])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [29]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [29]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux2~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux2~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux1~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux1~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [30])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [30])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [30]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [30]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux1~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux1~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux0~0 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux0~0_combout  = (\controller_0|internal_reg_file_read_address_0 [0] & ((\controller_0|internal_reg_file_read_address_0 [1] & (\datapath_0|register_file_0|reg_x3|internal_value [31])) # 
// (!\controller_0|internal_reg_file_read_address_0 [1] & ((\datapath_0|register_file_0|reg_x1|internal_value [31])))))

	.dataa(\controller_0|internal_reg_file_read_address_0 [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [31]),
	.datac(\datapath_0|register_file_0|reg_x1|internal_value [31]),
	.datad(\controller_0|internal_reg_file_read_address_0 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux0~0 .lut_mask = 16'h88A0;
defparam \datapath_0|register_file_0|output_1_mux|Mux0~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_JTU_mux_sel~combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[0]~0 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[0]~0_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [0])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [0]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[0]~0 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~0 (
// Equation(s):
// \datapath_0|ALU_0|Add0~0_combout  = \datapath_0|mux_1|output_0[31]~31_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[31]~31_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~0 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~1 (
// Equation(s):
// \datapath_0|ALU_0|Add0~1_combout  = \datapath_0|mux_1|output_0[30]~30_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[30]~30_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~1 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~2 (
// Equation(s):
// \datapath_0|ALU_0|Add0~2_combout  = \datapath_0|mux_1|output_0[29]~29_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[29]~29_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~2 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~3 (
// Equation(s):
// \datapath_0|ALU_0|Add0~3_combout  = \datapath_0|mux_1|output_0[28]~28_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[28]~28_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~3 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~4 (
// Equation(s):
// \datapath_0|ALU_0|Add0~4_combout  = \datapath_0|mux_1|output_0[27]~27_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[27]~27_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~4 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~5 (
// Equation(s):
// \datapath_0|ALU_0|Add0~5_combout  = \datapath_0|mux_1|output_0[26]~26_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[26]~26_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~5 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~6 (
// Equation(s):
// \datapath_0|ALU_0|Add0~6_combout  = \datapath_0|mux_1|output_0[25]~25_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[25]~25_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~6 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~7 (
// Equation(s):
// \datapath_0|ALU_0|Add0~7_combout  = \datapath_0|mux_1|output_0[24]~24_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[24]~24_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~7 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~8 (
// Equation(s):
// \datapath_0|ALU_0|Add0~8_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux8~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux8~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~8 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~8 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~9 (
// Equation(s):
// \datapath_0|ALU_0|Add0~9_combout  = \datapath_0|mux_1|output_0[22]~22_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[22]~22_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~9 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~9 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~10 (
// Equation(s):
// \datapath_0|ALU_0|Add0~10_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux10~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux10~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~10 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~10 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~11 (
// Equation(s):
// \datapath_0|ALU_0|Add0~11_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux11~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux11~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~11 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~11 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~12 (
// Equation(s):
// \datapath_0|ALU_0|Add0~12_combout  = \datapath_0|mux_1|output_0[19]~19_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[19]~19_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~12 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~12 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~13 (
// Equation(s):
// \datapath_0|ALU_0|Add0~13_combout  = \datapath_0|mux_1|output_0[18]~18_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[18]~18_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~13 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~13 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~14 (
// Equation(s):
// \datapath_0|ALU_0|Add0~14_combout  = \datapath_0|mux_1|output_0[17]~17_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[17]~17_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~14 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~14 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~15 (
// Equation(s):
// \datapath_0|ALU_0|Add0~15_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux15~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux15~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~15 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~15 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~16 (
// Equation(s):
// \datapath_0|ALU_0|Add0~16_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux16~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux16~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~16_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~16 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~16 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~17 (
// Equation(s):
// \datapath_0|ALU_0|Add0~17_combout  = \datapath_0|mux_1|output_0[14]~14_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[14]~14_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~17_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~17 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~17 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~18 (
// Equation(s):
// \datapath_0|ALU_0|Add0~18_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux18~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux18~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~18_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~18 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~18 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~19 (
// Equation(s):
// \datapath_0|ALU_0|Add0~19_combout  = \datapath_0|mux_1|output_0[12]~12_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[12]~12_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~19_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~19 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~19 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~20 (
// Equation(s):
// \datapath_0|ALU_0|Add0~20_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux20~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux20~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~20_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~20 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~20 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~21 (
// Equation(s):
// \datapath_0|ALU_0|Add0~21_combout  = \datapath_0|mux_1|output_0[10]~10_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[10]~10_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~21_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~21 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~21 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~22 (
// Equation(s):
// \datapath_0|ALU_0|Add0~22_combout  = \datapath_0|mux_1|output_0[9]~9_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[9]~9_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~22_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~22 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~22 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~23 (
// Equation(s):
// \datapath_0|ALU_0|Add0~23_combout  = \datapath_0|mux_1|output_0[8]~8_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[8]~8_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~23_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~23 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~23 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~24 (
// Equation(s):
// \datapath_0|ALU_0|Add0~24_combout  = \datapath_0|mux_1|output_0[7]~7_combout  $ (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|mux_1|output_0[7]~7_combout ),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~24_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~24 .lut_mask = 16'h0FF0;
defparam \datapath_0|ALU_0|Add0~24 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~25 (
// Equation(s):
// \datapath_0|ALU_0|Add0~25_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux25~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux25~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~25_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~25 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~25 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~26 (
// Equation(s):
// \datapath_0|ALU_0|Add0~26_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux26~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux26~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~26_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~26 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~26 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~27 (
// Equation(s):
// \datapath_0|ALU_0|Add0~27_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux27~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux27~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~27_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~27 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~27 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~28 (
// Equation(s):
// \datapath_0|ALU_0|Add0~28_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux28~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux28~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~28_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~28 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~28 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~29 (
// Equation(s):
// \datapath_0|ALU_0|Add0~29_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux29~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux29~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~29_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~29 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~29 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~30 (
// Equation(s):
// \datapath_0|ALU_0|Add0~30_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux30~2_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux30~2_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~30_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~30 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~30 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~31 (
// Equation(s):
// \datapath_0|ALU_0|Add0~31_combout  = \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  $ (((\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]))) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & 
// (\datapath_0|forward_mux_1|Mux31~3_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.datab(\datapath_0|forward_mux_1|Mux31~3_combout ),
	.datac(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|Add0~31_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~31 .lut_mask = 16'h1BE4;
defparam \datapath_0|ALU_0|Add0~31 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~2 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~2_combout  = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (!\datapath_0|ALU_0|Add0~34_combout  & (!\datapath_0|ALU_0|Add0~36_combout  & !\datapath_0|ALU_0|Add0~38_combout )))

	.dataa(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.datab(\datapath_0|ALU_0|Add0~34_combout ),
	.datac(\datapath_0|ALU_0|Add0~36_combout ),
	.datad(\datapath_0|ALU_0|Add0~38_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~2 .lut_mask = 16'h0002;
defparam \datapath_0|ALU_0|ALU_branch_response~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[1]~1 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[1]~1_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [1])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [1]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[1]~1 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[2]~2 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[2]~2_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [2])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [2]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[2]~2 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[3]~3 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[3]~3_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [3])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [3]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[3]~3 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[3]~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[4]~4 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[4]~4_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [4])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [4]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[4]~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[4]~4 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[4]~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [5]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[5]~5 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[5]~5_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [5])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [5]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[5]~5 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [6]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[6]~6 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[6]~6_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [6])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [6]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[6]~6 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [7]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[7]~7 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[7]~7_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [7])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [7]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[7]~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[7]~7 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[7]~7 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [8]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[8]~8 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[8]~8_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [8])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [8]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[8]~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[8]~8 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[8]~8 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [9]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[9]~9 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[9]~9_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [9])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [9]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[9]~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[9]~9 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[9]~9 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [10]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[10]~10 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[10]~10_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [10])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [10]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[10]~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[10]~10 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[10]~10 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [11]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[11]~11 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[11]~11_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [11])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [11]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[11]~11 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[11]~11 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [12]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[12]~12 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[12]~12_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [12])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [12]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[12]~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[12]~12 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[12]~12 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [13]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[13]~13 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[13]~13_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [13])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [13]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[13]~13 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[13]~13 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [14]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[14]~14 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[14]~14_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [14])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [14]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[14]~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[14]~14 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[14]~14 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [15]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[15]~15 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[15]~15_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [15])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [15]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[15]~15 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[15]~15 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [16]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[16]~16 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[16]~16_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [16])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [16]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[16]~16_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[16]~16 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[16]~16 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [17]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[17]~17 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[17]~17_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [17])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [17]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[17]~17_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[17]~17 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[17]~17 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [18]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[18]~18 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[18]~18_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [18])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [18]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[18]~18_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[18]~18 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[18]~18 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [19]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[19]~19 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[19]~19_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [19])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [19]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[19]~19_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[19]~19 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[19]~19 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [20]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[20]~20 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[20]~20_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [20])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [20]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[20]~20_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[20]~20 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[20]~20 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [21]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[21]~21 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[21]~21_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [21])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [21]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[21]~21 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[21]~21 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [22]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[22]~22 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[22]~22_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [22])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [22]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[22]~22_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[22]~22 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[22]~22 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [23]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[23]~23 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[23]~23_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [23])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [23]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[23]~23 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[23]~23 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [24]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[24]~24 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[24]~24_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [24])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [24]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[24]~24_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[24]~24 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[24]~24 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [25]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[25]~25 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[25]~25_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [25])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [25]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[25]~25_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[25]~25 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[25]~25 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [26]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[26]~26 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[26]~26_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [26])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [26]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[26]~26_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[26]~26 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[26]~26 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [27]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[27]~27 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[27]~27_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [27])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [27]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[27]~27_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[27]~27 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[27]~27 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [28]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[28]~28 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[28]~28_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [28])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [28]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[28]~28_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[28]~28 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[28]~28 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [29]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[29]~29 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[29]~29_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [29])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [29]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[29]~29_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[29]~29 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[29]~29 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [30]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[30]~30 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[30]~30_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [30])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [30]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[30]~30_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[30]~30 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[30]~30 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [31]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_mux|output_0[31]~31 (
// Equation(s):
// \datapath_0|JTU_0|internal_mux|output_0[31]~31_combout  = (\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31])) # (!\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q  & 
// ((\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [31])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31]),
	.datab(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [31]),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|JTU_mux_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_mux|output_0[31]~31_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_mux|output_0[31]~31 .lut_mask = 16'hAACC;
defparam \datapath_0|JTU_0|internal_mux|output_0[31]~31 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux31~0 (
// Equation(s):
// \datapath_0|mux_0|Mux31~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux31~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux30~0 (
// Equation(s):
// \datapath_0|mux_0|Mux30~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux30~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux29~0 (
// Equation(s):
// \datapath_0|mux_0|Mux29~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux29~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux28~0 (
// Equation(s):
// \datapath_0|mux_0|Mux28~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux28~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux28~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux28~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux27~0 (
// Equation(s):
// \datapath_0|mux_0|Mux27~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux27~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux26~0 (
// Equation(s):
// \datapath_0|mux_0|Mux26~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux26~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux25~0 (
// Equation(s):
// \datapath_0|mux_0|Mux25~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux25~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux24~0 (
// Equation(s):
// \datapath_0|mux_0|Mux24~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux24~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux23~0 (
// Equation(s):
// \datapath_0|mux_0|Mux23~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux23~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [8]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux22~0 (
// Equation(s):
// \datapath_0|mux_0|Mux22~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux22~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux22~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux22~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [9]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux21~0 (
// Equation(s):
// \datapath_0|mux_0|Mux21~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux21~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [10]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux20~0 (
// Equation(s):
// \datapath_0|mux_0|Mux20~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux20~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux20~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux20~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [11]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux19~0 (
// Equation(s):
// \datapath_0|mux_0|Mux19~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux19~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux19~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux19~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [12]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux18~0 (
// Equation(s):
// \datapath_0|mux_0|Mux18~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux18~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux18~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux18~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [13]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux17~0 (
// Equation(s):
// \datapath_0|mux_0|Mux17~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux17~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux17~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux17~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [14]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux16~0 (
// Equation(s):
// \datapath_0|mux_0|Mux16~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux16~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [15]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux15~0 (
// Equation(s):
// \datapath_0|mux_0|Mux15~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux15~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [16]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux14~0 (
// Equation(s):
// \datapath_0|mux_0|Mux14~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux14~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux14~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux14~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [17]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux13~0 (
// Equation(s):
// \datapath_0|mux_0|Mux13~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux13~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux13~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux13~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [18]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux12~0 (
// Equation(s):
// \datapath_0|mux_0|Mux12~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux12~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux12~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux12~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [19]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux11~0 (
// Equation(s):
// \datapath_0|mux_0|Mux11~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux11~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [20]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux10~0 (
// Equation(s):
// \datapath_0|mux_0|Mux10~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux10~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [21]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux9~0 (
// Equation(s):
// \datapath_0|mux_0|Mux9~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux9~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux9~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [22]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux8~0 (
// Equation(s):
// \datapath_0|mux_0|Mux8~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux8~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [23]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux7~0 (
// Equation(s):
// \datapath_0|mux_0|Mux7~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux7~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux7~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [24]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux6~0 (
// Equation(s):
// \datapath_0|mux_0|Mux6~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux6~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux6~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux6~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [25]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux5~0 (
// Equation(s):
// \datapath_0|mux_0|Mux5~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux5~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux5~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux5~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [26]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux4~0 (
// Equation(s):
// \datapath_0|mux_0|Mux4~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux4~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux4~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux4~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [27]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux3~0 (
// Equation(s):
// \datapath_0|mux_0|Mux3~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux3~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux3~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [28]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux2~0 (
// Equation(s):
// \datapath_0|mux_0|Mux2~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux2~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux2~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [29]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux1~0 (
// Equation(s):
// \datapath_0|mux_0|Mux1~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux1~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux1~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [30]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux0~0 (
// Equation(s):
// \datapath_0|mux_0|Mux0~0_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31])) # 
// (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31])))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31]),
	.datab(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux0~0 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_0|Mux0~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [31]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~0 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~0_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~1 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~1_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~0_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~0_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~0_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~1 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~2 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~2_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~2 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~3 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~3_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~2_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~2_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~2_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~2_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~3 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~4 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~4_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~4 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~5 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~5_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~4_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~4_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~4_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~4_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~5 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~6 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~6_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~3_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~5_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~3_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~5_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~6 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~7 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~7_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~7 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~7 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~8 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~8_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~7_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~7_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~7_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~7_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~8 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~8 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~9 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~9_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~6_combout  & ((\datapath_0|datamem_module_0|output_data~8_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~6_combout  & (\datapath_0|datamem_module_0|output_data~1_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~6_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~1_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~6_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~8_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~9 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~9 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~10 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~10_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~10 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~10 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~11 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~11_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~10_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~10_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~10_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~10_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~11 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~11 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~12 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~12_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~12 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~12 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~13 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~13_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~12_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~12_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~12_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~12_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~13 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~13 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~14 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~14_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~14 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~14 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~15 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~15_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~14_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~14_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~14_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~14_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~15 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~15 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~16 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~16_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~13_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~15_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~13_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~15_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~16_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~16 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~16 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~17 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~17_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~17_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~17 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~17 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~18 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~18_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~17_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~17_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~17_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~17_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~18_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~18 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~18 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~19 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~19_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~16_combout  & ((\datapath_0|datamem_module_0|output_data~18_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~16_combout  & (\datapath_0|datamem_module_0|output_data~11_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~16_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~11_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~16_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~18_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~19_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~19 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~19 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~20 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~20_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~9_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~19_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~9_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~19_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~20_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~20 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~20 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~21 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~21_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~21_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~21 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~21 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~22 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~22_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~21_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~21_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~21_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~21_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~22_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~22 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~22 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~23 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~23_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~23_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~23 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~23 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~24 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~24_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~23_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~23_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~23_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~23_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~24_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~24 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~24 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~25 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~25_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~25_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~25 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~25 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~26 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~26_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~25_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~25_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~25_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~25_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~26_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~26 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~26 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~27 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~27_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~24_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~26_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~24_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~26_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~27_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~27 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~27 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~28 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~28_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~28_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~28 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~28 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~29 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~29_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~28_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~28_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~28_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~28_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~29_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~29 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~29 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~30 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~30_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~27_combout  & ((\datapath_0|datamem_module_0|output_data~29_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~27_combout  & (\datapath_0|datamem_module_0|output_data~22_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~27_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~22_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~27_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~29_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~30_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~30 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~30 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~31 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~31_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~31_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~31 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~31 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~32 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~32_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~31_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~31_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~31_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~31_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~32_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~32 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~32 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~42 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~42_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~42_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~42 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~42 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~43 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~43_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~42_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~42_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~42_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~42_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~43_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~43 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~43 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~44 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~44_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~44_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~44 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~44 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~45 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~45_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~44_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~44_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~44_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~44_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~45_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~45 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~45 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~46 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~46_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~46_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~46 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~46 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~47 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~47_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~46_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~46_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~46_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~46_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~47_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~47 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~47 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~48 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~48_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~45_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~47_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~45_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~47_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~48_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~48 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~48 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~49 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~49_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~49_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~49 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~49 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~50 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~50_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~49_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~49_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~49_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~49_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~50_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~50 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~50 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~51 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~51_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~48_combout  & ((\datapath_0|datamem_module_0|output_data~50_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~48_combout  & (\datapath_0|datamem_module_0|output_data~43_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~48_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~43_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~48_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~50_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~51_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~51 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~51 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~52 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~52_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~52_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~52 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~52 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~53 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~53_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~52_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~52_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~52_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~52_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~53_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~53 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~53 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~54 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~54_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~54_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~54 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~54 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~55 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~55_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~54_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~54_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~54_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~54_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~55_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~55 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~55 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~56 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~56_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~56_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~56 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~56 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~57 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~57_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~56_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~56_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~56_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~56_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~57_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~57 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~57 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~58 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~58_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~55_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~57_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~55_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~57_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~58_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~58 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~58 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~59 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~59_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~59_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~59 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~59 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~60 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~60_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~59_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~59_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~59_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~59_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~60_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~60 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~60 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~61 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~61_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~58_combout  & ((\datapath_0|datamem_module_0|output_data~60_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~58_combout  & (\datapath_0|datamem_module_0|output_data~53_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~58_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~53_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~58_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~60_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~61_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~61 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~61 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~62 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~62_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~51_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~61_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~51_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~61_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~62_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~62 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~62 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~63 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~63_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~63_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~63 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~63 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~64 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~64_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~63_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~63_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~63_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~63_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~64_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~64 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~64 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~65 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~65_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~65_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~65 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~65 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~66 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~66_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~65_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~65_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~65_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~65_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~66_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~66 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~66 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~67 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~67_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~67_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~67 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~67 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~68 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~68_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~67_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~67_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~67_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~67_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~68_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~68 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~68 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~69 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~69_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~66_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~68_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~66_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~68_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~69_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~69 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~69 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~70 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~70_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~70_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~70 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~70 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~71 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~71_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~70_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~70_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~70_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~70_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~71_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~71 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~71 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~72 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~72_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~69_combout  & ((\datapath_0|datamem_module_0|output_data~71_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~69_combout  & (\datapath_0|datamem_module_0|output_data~64_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~69_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~64_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~69_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~71_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~72_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~72 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~72 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~73 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~73_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~73_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~73 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~73 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~74 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~74_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~73_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~73_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~73_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~73_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~74_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~74 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~74 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~84 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~84_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~84_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~84 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~84 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~85 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~85_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~84_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~84_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~84_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~84_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~85_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~85 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~85 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~86 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~86_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~86_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~86 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~86 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~87 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~87_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~86_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~86_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~86_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~86_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~87_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~87 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~87 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~88 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~88_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~88_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~88 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~88 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~89 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~89_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~88_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~88_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~88_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~88_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~89_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~89 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~89 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~90 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~90_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~87_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~89_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~87_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~89_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~90_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~90 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~90 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~91 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~91_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~91_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~91 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~91 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~92 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~92_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~91_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~91_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~91_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~91_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~92_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~92 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~92 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~93 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~93_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~90_combout  & ((\datapath_0|datamem_module_0|output_data~92_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~90_combout  & (\datapath_0|datamem_module_0|output_data~85_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~90_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~85_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~90_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~92_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~93_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~93 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~93 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~94 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~94_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~94_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~94 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~94 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~95 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~95_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~94_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~94_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~94_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~94_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~95_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~95 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~95 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~96 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~96_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~96_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~96 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~96 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~97 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~97_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~96_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~96_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~96_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~96_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~97_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~97 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~97 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~98 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~98_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~98_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~98 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~98 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~99 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~99_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~98_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~98_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~98_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~98_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~99_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~99 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~99 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~100 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~100_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~97_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~99_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~97_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~99_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~100_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~100 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~100 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~101 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~101_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~101_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~101 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~101 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~102 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~102_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~101_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~101_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~101_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~101_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~102_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~102 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~102 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~103 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~103_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~100_combout  & ((\datapath_0|datamem_module_0|output_data~102_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~100_combout  & (\datapath_0|datamem_module_0|output_data~95_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~100_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~95_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~100_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~102_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~103_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~103 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~103 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~104 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~104_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~93_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~103_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~93_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~103_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~104_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~104 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~104 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~105 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~105_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~105_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~105 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~105 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~106 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~106_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~105_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~105_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~105_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~105_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~106_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~106 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~106 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~107 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~107_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~107_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~107 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~107 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~108 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~108_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~107_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~107_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~107_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~107_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~108_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~108 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~108 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~109 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~109_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~109_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~109 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~109 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~110 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~110_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~109_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~109_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~109_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~109_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~110_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~110 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~110 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~111 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~111_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~108_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~110_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~108_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~110_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~111_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~111 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~111 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~112 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~112_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~112_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~112 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~112 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~113 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~113_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~112_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~112_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~112_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~112_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~113_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~113 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~113 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~114 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~114_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~111_combout  & ((\datapath_0|datamem_module_0|output_data~113_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~111_combout  & (\datapath_0|datamem_module_0|output_data~106_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~111_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~106_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~111_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~113_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~114_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~114 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~114 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~115 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~115_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~115_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~115 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~115 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~116 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~116_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~115_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~115_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~115_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~115_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~116_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~116 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~116 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~126 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~126_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~126_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~126 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~126 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~127 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~127_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~126_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~126_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~126_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~126_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~127_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~127 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~127 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~128 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~128_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~128_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~128 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~128 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~129 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~129_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~128_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~128_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~128_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~128_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~129_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~129 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~129 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~130 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~130_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~130_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~130 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~130 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~131 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~131_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~130_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~130_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~130_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~130_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~131_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~131 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~131 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~132 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~132_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~129_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~131_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~129_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~131_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~132_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~132 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~132 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~133 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~133_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~133_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~133 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~133 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~134 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~134_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~133_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~133_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~133_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~133_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~134_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~134 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~134 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~135 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~135_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~132_combout  & ((\datapath_0|datamem_module_0|output_data~134_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~132_combout  & (\datapath_0|datamem_module_0|output_data~127_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~132_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~127_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~132_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~134_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~135_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~135 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~135 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~136 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~136_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~136_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~136 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~136 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~137 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~137_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~136_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~136_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~136_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~136_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~137_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~137 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~137 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~138 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~138_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~138_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~138 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~138 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~139 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~139_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~138_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~138_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~138_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~138_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~139_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~139 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~139 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~140 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~140_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~140_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~140 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~140 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~141 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~141_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~140_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~140_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~140_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~140_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~141_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~141 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~141 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~142 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~142_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~139_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~141_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~139_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~141_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~142_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~142 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~142 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~143 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~143_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~143_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~143 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~143 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~144 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~144_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~143_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~143_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~143_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~143_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~144_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~144 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~144 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~145 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~145_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~142_combout  & ((\datapath_0|datamem_module_0|output_data~144_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~142_combout  & (\datapath_0|datamem_module_0|output_data~137_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~142_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~137_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~142_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~144_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~145_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~145 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~145 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~146 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~146_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~135_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~145_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~135_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~145_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~146_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~146 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~146 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~147 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~147_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x25|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x17|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~147_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~147 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~147 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~148 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~148_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~147_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~147_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~147_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x21|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~147_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x29|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~148_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~148 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~148 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~149 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~149_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x22|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x18|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~149_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~149 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~149 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~150 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~150_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~149_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~149_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~149_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x26|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~149_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x30|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~150_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~150 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~150 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~151 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~151_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x20|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x16|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~151_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~151 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~151 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~152 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~152_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~151_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~151_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~151_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x24|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~151_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x28|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~152_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~152 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~152 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~153 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~153_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~150_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~152_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~150_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~152_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~153_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~153 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~153 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~154 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~154_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x27|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x19|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~154_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~154 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~154 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~155 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~155_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~154_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~154_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~154_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x23|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~154_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x31|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~155_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~155 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~155 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~156 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~156_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~153_combout  & ((\datapath_0|datamem_module_0|output_data~155_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~153_combout  & (\datapath_0|datamem_module_0|output_data~148_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~153_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~148_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~153_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~155_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~156_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~156 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~156 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~157 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~157_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x5|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x4|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~157_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~157 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~157 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~158 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~158_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~157_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~157_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~157_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x6|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~157_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x7|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~158_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~158 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~158 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~168 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~168_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~168_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~168 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~168 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~169 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~169_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~168_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~168_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~168_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~168_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~169_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~169 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~169 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~170 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~170_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~170_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~170 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~170 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~171 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~171_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~170_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~170_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~170_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~170_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~171_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~171 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~171 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~172 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~172_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~172_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~172 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~172 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~173 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~173_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~172_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~172_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~172_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~172_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~173_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~173 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~173 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~174 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~174_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~171_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~173_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~171_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~173_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~174_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~174 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~174 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~175 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~175_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~175_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~175 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~175 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~176 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~176_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~175_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~175_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~175_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~175_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~176_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~176 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~176 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~177 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~177_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~174_combout  & ((\datapath_0|datamem_module_0|output_data~176_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~174_combout  & (\datapath_0|datamem_module_0|output_data~169_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~174_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~169_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~174_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~176_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~177_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~177 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~177 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~178 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~178_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~178_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~178 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~178 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~179 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~179_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~178_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~178_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~178_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~178_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~179_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~179 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~179 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~189 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~189_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~189_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~189 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~189 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~190 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~190_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~189_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~189_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~189_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~189_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~190_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~190 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~190 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~191 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~191_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~191_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~191 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~191 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~192 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~192_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~191_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~191_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~191_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~191_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~192_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~192 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~192 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~193 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~193_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~193_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~193 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~193 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~194 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~194_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~193_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~193_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~193_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~193_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~194_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~194 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~194 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~195 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~195_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~192_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~194_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~192_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~194_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~195_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~195 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~195 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~196 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~196_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~196_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~196 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~196 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~197 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~197_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~196_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~196_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~196_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~196_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~197_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~197 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~197 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~198 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~198_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~195_combout  & ((\datapath_0|datamem_module_0|output_data~197_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~195_combout  & (\datapath_0|datamem_module_0|output_data~190_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~195_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~190_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~195_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~197_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~198_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~198 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~198 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~199 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~199_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~199_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~199 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~199 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~200 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~200_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~199_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~199_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~199_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~199_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~200_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~200 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~200 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~210 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~210_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~210_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~210 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~210 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~211 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~211_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~210_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~210_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~210_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~210_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~211_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~211 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~211 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~212 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~212_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~212_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~212 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~212 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~213 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~213_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~212_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~212_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~212_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~212_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~213_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~213 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~213 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~214 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~214_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~214_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~214 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~214 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~215 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~215_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~214_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~214_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~214_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~214_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~215_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~215 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~215 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~216 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~216_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~213_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~215_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~213_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~215_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~216_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~216 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~216 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~217 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~217_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~217_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~217 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~217 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~218 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~218_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~217_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~217_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~217_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~217_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~218_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~218 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~218 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~219 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~219_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~216_combout  & ((\datapath_0|datamem_module_0|output_data~218_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~216_combout  & (\datapath_0|datamem_module_0|output_data~211_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~216_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~211_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~216_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~218_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~219_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~219 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~219 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~220 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~220_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~220_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~220 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~220 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~221 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~221_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~220_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~220_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~220_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~220_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~221_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~221 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~221 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~231 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~231_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~231_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~231 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~231 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~232 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~232_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~231_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~231_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~231_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~231_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~232_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~232 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~232 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~233 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~233_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~233_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~233 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~233 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~234 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~234_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~233_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~233_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~233_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~233_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~234_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~234 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~234 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~235 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~235_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [3]) # ((!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [3] & \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [3]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~235_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~235 .lut_mask = 16'hD8AA;
defparam \datapath_0|datamem_module_0|output_data~235 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~236 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~236_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~235_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|output_data~235_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [3])) # (!\datapath_0|datamem_module_0|output_data~235_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value 
// [3])))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~235_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~236_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~236 .lut_mask = 16'hEE30;
defparam \datapath_0|datamem_module_0|output_data~236 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~237 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~237_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~234_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~236_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~234_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~236_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~237_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~237 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~237 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~238 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~238_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~238_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~238 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~238 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~239 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~239_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~238_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~238_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~238_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~238_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~239_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~239 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~239 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~240 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~240_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~237_combout  & ((\datapath_0|datamem_module_0|output_data~239_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~237_combout  & (\datapath_0|datamem_module_0|output_data~232_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~237_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~232_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~237_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~239_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~240_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~240 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~240 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~241 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~241_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~241_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~241 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~241 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~242 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~242_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~241_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~241_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~241_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~241_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~242_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~242 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~242 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~252 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~252_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~252_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~252 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~252 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~253 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~253_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~252_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~252_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~252_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~252_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~253_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~253 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~253 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~254 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~254_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~254_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~254 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~254 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~255 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~255_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~254_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~254_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~254_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~254_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~255_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~255 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~255 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~256 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~256_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~256_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~256 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~256 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~257 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~257_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~256_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~256_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~256_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~256_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~257_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~257 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~257 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~258 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~258_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~255_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~257_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~255_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~257_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~258_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~258 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~258 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~259 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~259_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~259_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~259 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~259 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~260 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~260_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~259_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~259_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~259_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~259_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~260_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~260 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~260 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~261 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~261_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~258_combout  & ((\datapath_0|datamem_module_0|output_data~260_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~258_combout  & (\datapath_0|datamem_module_0|output_data~253_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~258_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~253_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~258_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~260_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~261_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~261 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~261 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~262 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~262_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~262_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~262 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~262 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~263 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~263_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~262_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~262_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~262_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~262_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~263_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~263 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~263 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~273 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~273_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~273_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~273 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~273 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~274 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~274_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~273_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~273_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~273_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~273_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~274_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~274 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~274 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~275 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~275_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~275_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~275 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~275 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~276 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~276_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~275_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~275_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~275_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~275_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~276_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~276 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~276 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~277 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~277_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~277_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~277 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~277 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~278 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~278_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~277_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~277_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~277_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~277_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~278_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~278 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~278 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~279 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~279_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~276_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~278_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~276_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~278_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~279_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~279 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~279 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~280 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~280_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~280_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~280 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~280 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~281 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~281_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~280_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~280_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~280_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~280_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~281_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~281 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~281 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~282 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~282_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~279_combout  & ((\datapath_0|datamem_module_0|output_data~281_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~279_combout  & (\datapath_0|datamem_module_0|output_data~274_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~279_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~274_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~279_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~281_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~282_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~282 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~282 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~283 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~283_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~283_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~283 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~283 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~284 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~284_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~283_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~283_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~283_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~283_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~284_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~284 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~284 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~294 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~294_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~294_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~294 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~294 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~295 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~295_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~294_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~294_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~294_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~294_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~295_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~295 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~295 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~296 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~296_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~296_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~296 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~296 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~297 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~297_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~296_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~296_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~296_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~296_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~297_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~297 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~297 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~298 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~298_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~298_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~298 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~298 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~299 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~299_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~298_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~298_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~298_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~298_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~299_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~299 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~299 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~300 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~300_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~297_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~299_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~297_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~299_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~300_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~300 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~300 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~301 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~301_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~301_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~301 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~301 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~302 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~302_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~301_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~301_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~301_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~301_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~302_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~302 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~302 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~303 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~303_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~300_combout  & ((\datapath_0|datamem_module_0|output_data~302_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~300_combout  & (\datapath_0|datamem_module_0|output_data~295_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~300_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~295_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~300_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~302_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~303_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~303 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~303 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~304 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~304_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~304_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~304 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~304 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~305 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~305_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~304_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~304_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~304_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~304_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~305_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~305 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~305 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~315 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~315_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x25|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x17|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~315_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~315 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~315 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~316 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~316_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~315_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~315_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~315_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x21|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~315_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x29|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~316_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~316 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~316 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~317 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~317_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x22|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x18|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~317_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~317 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~317 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~318 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~318_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~317_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~317_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~317_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x26|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~317_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x30|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~318_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~318 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~318 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~319 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~319_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x20|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x16|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~319_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~319 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~319 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~320 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~320_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~319_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~319_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~319_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x24|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~319_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x28|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~320_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~320 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~320 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~321 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~321_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~318_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~320_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~318_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~320_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~321_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~321 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~321 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~322 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~322_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x27|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x19|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~322_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~322 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~322 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~323 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~323_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~322_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~322_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~322_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x23|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~322_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x31|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~323_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~323 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~323 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~324 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~324_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~321_combout  & ((\datapath_0|datamem_module_0|output_data~323_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~321_combout  & (\datapath_0|datamem_module_0|output_data~316_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~321_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~316_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~321_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~323_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~324_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~324 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~324 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~325 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~325_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~325_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~325 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~325 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~326 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~326_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~325_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~325_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~325_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~325_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~326_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~326 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~326 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~336 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~336_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~336_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~336 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~336 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~337 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~337_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~336_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~336_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~336_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~336_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~337_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~337 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~337 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~338 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~338_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~338_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~338 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~338 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~339 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~339_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~338_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~338_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~338_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~338_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~339_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~339 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~339 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~340 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~340_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~340_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~340 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~340 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~341 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~341_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~340_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~340_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~340_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~340_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~341_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~341 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~341 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~342 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~342_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~339_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~341_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~339_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~341_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~342_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~342 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~342 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~343 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~343_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~343_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~343 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~343 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~344 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~344_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~343_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~343_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~343_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~343_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~344_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~344 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~344 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~345 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~345_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~342_combout  & ((\datapath_0|datamem_module_0|output_data~344_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~342_combout  & (\datapath_0|datamem_module_0|output_data~337_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~342_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~337_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~342_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~344_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~345_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~345 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~345 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~346 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~346_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~346_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~346 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~346 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~347 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~347_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~346_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~346_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~346_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~346_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~347_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~347 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~347 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~348 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~348_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~348_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~348 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~348 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~349 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~349_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~348_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~348_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~348_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~348_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~349_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~349 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~349 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~350 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~350_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~350_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~350 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~350 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~351 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~351_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~350_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~350_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~350_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~350_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~351_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~351 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~351 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~352 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~352_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~349_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~351_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~349_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~351_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~352_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~352 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~352 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~353 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~353_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~353_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~353 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~353 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~354 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~354_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~353_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~353_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~353_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~353_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~354_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~354 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~354 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~355 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~355_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~352_combout  & ((\datapath_0|datamem_module_0|output_data~354_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~352_combout  & (\datapath_0|datamem_module_0|output_data~347_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~352_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~347_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~352_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~354_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~355_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~355 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~355 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~356 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~356_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~345_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~355_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~345_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~355_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~356_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~356 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~356 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~357 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~357_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~357_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~357 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~357 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~358 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~358_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~357_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~357_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~357_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~357_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~358_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~358 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~358 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~359 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~359_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~359_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~359 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~359 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~360 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~360_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~359_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~359_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~359_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~359_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~360_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~360 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~360 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~361 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~361_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~361_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~361 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~361 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~362 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~362_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~361_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~361_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~361_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~361_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~362_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~362 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~362 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~363 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~363_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~360_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~362_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~360_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~362_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~363_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~363 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~363 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~364 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~364_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~364_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~364 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~364 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~365 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~365_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~364_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~364_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~364_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~364_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~365_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~365 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~365 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~366 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~366_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~363_combout  & ((\datapath_0|datamem_module_0|output_data~365_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~363_combout  & (\datapath_0|datamem_module_0|output_data~358_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~363_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~358_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~363_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~365_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~366_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~366 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~366 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~367 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~367_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~367_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~367 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~367 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~368 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~368_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~367_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~367_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~367_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~367_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~368_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~368 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~368 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~378 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~378_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~378_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~378 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~378 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~379 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~379_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~378_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~378_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~378_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~378_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~379_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~379 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~379 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~380 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~380_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~380_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~380 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~380 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~381 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~381_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~380_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~380_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~380_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~380_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~381_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~381 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~381 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~382 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~382_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~382_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~382 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~382 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~383 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~383_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~382_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~382_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~382_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~382_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~383_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~383 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~383 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~384 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~384_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~381_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~383_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~381_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~383_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~384_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~384 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~384 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~385 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~385_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~385_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~385 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~385 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~386 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~386_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~385_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~385_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~385_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~385_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~386_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~386 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~386 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~387 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~387_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~384_combout  & ((\datapath_0|datamem_module_0|output_data~386_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~384_combout  & (\datapath_0|datamem_module_0|output_data~379_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~384_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~379_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~384_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~386_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~387_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~387 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~387 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~388 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~388_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~388_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~388 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~388 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~389 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~389_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~388_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~388_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~388_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~388_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~389_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~389 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~389 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~399 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~399_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~399_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~399 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~399 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~400 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~400_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~399_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~399_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~399_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~399_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~400_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~400 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~400 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~401 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~401_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~401_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~401 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~401 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~402 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~402_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~401_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~401_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~401_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~401_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~402_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~402 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~402 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~403 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~403_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~403_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~403 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~403 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~404 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~404_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~403_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~403_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~403_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~403_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~404_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~404 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~404 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~405 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~405_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~402_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~404_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~402_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~404_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~405_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~405 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~405 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~406 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~406_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~406_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~406 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~406 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~407 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~407_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~406_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~406_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~406_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~406_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~407_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~407 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~407 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~408 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~408_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~405_combout  & ((\datapath_0|datamem_module_0|output_data~407_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~405_combout  & (\datapath_0|datamem_module_0|output_data~400_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~405_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~400_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~405_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~407_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~408_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~408 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~408 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~409 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~409_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~409_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~409 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~409 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~410 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~410_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~409_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~409_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~409_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~409_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~410_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~410 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~410 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~420 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~420_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~420_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~420 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~420 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~421 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~421_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~420_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~420_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~420_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~420_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~421_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~421 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~421 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~422 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~422_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~422_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~422 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~422 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~423 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~423_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~422_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~422_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~422_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~422_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~423_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~423 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~423 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~424 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~424_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~424_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~424 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~424 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~425 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~425_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~424_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~424_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~424_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~424_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~425_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~425 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~425 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~426 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~426_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~423_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~425_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~423_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~425_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~426_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~426 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~426 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~427 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~427_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~427_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~427 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~427 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~428 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~428_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~427_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~427_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~427_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~427_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~428_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~428 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~428 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~429 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~429_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~426_combout  & ((\datapath_0|datamem_module_0|output_data~428_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~426_combout  & (\datapath_0|datamem_module_0|output_data~421_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~426_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~421_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~426_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~428_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~429_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~429 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~429 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~430 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~430_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~430_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~430 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~430 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~431 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~431_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~430_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~430_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~430_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~430_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~431_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~431 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~431 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~432 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~432_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~432_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~432 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~432 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~433 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~433_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~432_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~432_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~432_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~432_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~433_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~433 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~433 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~434 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~434_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~434_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~434 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~434 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~435 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~435_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~434_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~434_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~434_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~434_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~435_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~435 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~435 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~436 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~436_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~433_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~435_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~433_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~435_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~436_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~436 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~436 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~437 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~437_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~437_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~437 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~437 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~438 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~438_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~437_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~437_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~437_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~437_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~438_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~438 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~438 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~439 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~439_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~436_combout  & ((\datapath_0|datamem_module_0|output_data~438_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~436_combout  & (\datapath_0|datamem_module_0|output_data~431_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~436_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~431_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~436_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~438_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~439_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~439 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~439 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~440 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~440_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~429_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~439_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~429_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~439_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~440_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~440 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~440 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~441 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~441_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~441_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~441 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~441 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~442 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~442_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~441_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~441_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~441_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~441_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~442_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~442 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~442 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~443 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~443_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~443_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~443 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~443 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~444 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~444_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~443_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~443_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~443_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~443_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~444_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~444 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~444 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~445 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~445_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~445_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~445 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~445 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~446 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~446_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~445_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~445_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~445_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~445_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~446_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~446 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~446 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~447 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~447_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~444_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~446_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~444_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~446_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~447_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~447 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~447 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~448 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~448_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~448_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~448 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~448 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~449 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~449_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~448_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~448_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~448_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~448_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~449_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~449 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~449 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~450 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~450_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~447_combout  & ((\datapath_0|datamem_module_0|output_data~449_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~447_combout  & (\datapath_0|datamem_module_0|output_data~442_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~447_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~442_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~447_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~449_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~450_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~450 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~450 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~451 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~451_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~451_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~451 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~451 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~452 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~452_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~451_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~451_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~451_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~451_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~452_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~452 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~452 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~462 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~462_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~462_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~462 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~462 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~463 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~463_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~462_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~462_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~462_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~462_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~463_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~463 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~463 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~464 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~464_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~464_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~464 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~464 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~465 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~465_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~464_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~464_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~464_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~464_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~465_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~465 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~465 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~466 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~466_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~466_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~466 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~466 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~467 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~467_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~466_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~466_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~466_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~466_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~467_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~467 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~467 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~468 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~468_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~465_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~467_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~465_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~467_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~468_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~468 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~468 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~469 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~469_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~469_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~469 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~469 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~470 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~470_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~469_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~469_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~469_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~469_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~470_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~470 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~470 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~471 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~471_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~468_combout  & ((\datapath_0|datamem_module_0|output_data~470_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~468_combout  & (\datapath_0|datamem_module_0|output_data~463_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~468_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~463_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~468_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~470_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~471_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~471 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~471 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~472 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~472_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~472_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~472 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~472 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~473 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~473_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~472_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~472_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~472_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~472_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~473_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~473 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~473 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~483 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~483_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x25|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x17|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~483_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~483 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~483 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~484 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~484_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~483_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~483_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~483_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x21|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~483_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x29|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~484_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~484 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~484 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~485 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~485_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x22|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x18|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~485_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~485 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~485 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~486 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~486_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~485_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~485_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~485_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x26|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~485_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x30|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~486_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~486 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~486 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~487 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~487_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x20|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x16|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~487_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~487 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~487 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~488 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~488_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~487_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~487_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~487_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x24|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~487_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x28|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~488_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~488 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~488 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~489 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~489_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~486_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~488_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~486_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~488_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~489_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~489 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~489 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~490 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~490_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x27|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x19|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~490_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~490 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~490 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~491 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~491_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~490_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~490_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~490_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x23|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~490_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x31|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~491_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~491 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~491 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~492 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~492_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~489_combout  & ((\datapath_0|datamem_module_0|output_data~491_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~489_combout  & (\datapath_0|datamem_module_0|output_data~484_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~489_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~484_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~489_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~491_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~492_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~492 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~492 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~493 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~493_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~493_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~493 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~493 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~494 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~494_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~493_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~493_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~493_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~493_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~494_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~494 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~494 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~504 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~504_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~504_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~504 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~504 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~505 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~505_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~504_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~504_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~504_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~504_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~505_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~505 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~505 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~506 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~506_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~506_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~506 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~506 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~507 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~507_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~506_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~506_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~506_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~506_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~507_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~507 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~507 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~508 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~508_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~508_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~508 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~508 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~509 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~509_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~508_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~508_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~508_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~508_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~509_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~509 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~509 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~510 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~510_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~507_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~509_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~507_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~509_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~510_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~510 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~510 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~511 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~511_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~511_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~511 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~511 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~512 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~512_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~511_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~511_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~511_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~511_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~512_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~512 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~512 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~513 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~513_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~510_combout  & ((\datapath_0|datamem_module_0|output_data~512_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~510_combout  & (\datapath_0|datamem_module_0|output_data~505_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~510_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~505_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~510_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~512_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~513_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~513 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~513 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~514 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~514_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~514_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~514 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~514 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~515 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~515_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~514_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~514_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~514_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~514_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~515_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~515 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~515 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~525 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~525_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~525_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~525 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~525 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~526 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~526_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~525_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~525_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~525_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~525_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~526_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~526 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~526 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~527 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~527_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~527_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~527 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~527 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~528 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~528_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~527_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~527_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~527_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~527_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~528_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~528 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~528 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~529 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~529_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~529_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~529 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~529 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~530 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~530_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~529_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~529_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~529_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~529_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~530_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~530 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~530 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~531 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~531_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~528_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~530_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~528_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~530_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~531_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~531 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~531 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~532 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~532_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~532_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~532 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~532 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~533 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~533_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~532_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~532_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~532_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~532_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~533_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~533 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~533 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~534 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~534_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~531_combout  & ((\datapath_0|datamem_module_0|output_data~533_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~531_combout  & (\datapath_0|datamem_module_0|output_data~526_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~531_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~526_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~531_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~533_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~534_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~534 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~534 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~535 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~535_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~535_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~535 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~535 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~536 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~536_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~535_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~535_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~535_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~535_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~536_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~536 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~536 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~546 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~546_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~546_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~546 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~546 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~547 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~547_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~546_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~546_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~546_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~546_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~547_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~547 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~547 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~548 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~548_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~548_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~548 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~548 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~549 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~549_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~548_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~548_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~548_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~548_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~549_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~549 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~549 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~550 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~550_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~550_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~550 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~550 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~551 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~551_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~550_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~550_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~550_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~550_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~551_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~551 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~551 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~552 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~552_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~549_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~551_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~549_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~551_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~552_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~552 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~552 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~553 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~553_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~553_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~553 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~553 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~554 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~554_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~553_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~553_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~553_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~553_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~554_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~554 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~554 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~555 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~555_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~552_combout  & ((\datapath_0|datamem_module_0|output_data~554_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~552_combout  & (\datapath_0|datamem_module_0|output_data~547_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~552_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~547_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~552_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~554_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~555_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~555 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~555 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~556 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~556_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~556_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~556 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~556 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~557 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~557_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~556_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~556_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~556_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~556_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~557_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~557 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~557 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~567 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~567_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~567_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~567 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~567 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~568 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~568_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~567_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~567_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~567_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~567_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~568_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~568 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~568 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~569 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~569_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~569_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~569 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~569 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~570 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~570_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~569_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~569_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~569_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~569_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~570_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~570 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~570 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~571 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~571_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~571_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~571 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~571 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~572 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~572_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~571_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~571_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~571_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~571_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~572_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~572 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~572 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~573 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~573_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~570_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~572_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~570_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~572_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~573_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~573 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~573 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~574 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~574_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~574_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~574 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~574 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~575 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~575_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~574_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~574_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~574_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~574_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~575_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~575 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~575 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~576 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~576_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~573_combout  & ((\datapath_0|datamem_module_0|output_data~575_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~573_combout  & (\datapath_0|datamem_module_0|output_data~568_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~573_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~568_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~573_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~575_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~576_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~576 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~576 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~577 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~577_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~577_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~577 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~577 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~578 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~578_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~577_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~577_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~577_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~577_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~578_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~578 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~578 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~588 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~588_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~588_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~588 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~588 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~589 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~589_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~588_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~588_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~588_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~588_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~589_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~589 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~589 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~590 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~590_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~590_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~590 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~590 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~591 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~591_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~590_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~590_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~590_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~590_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~591_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~591 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~591 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~592 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~592_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~592_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~592 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~592 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~593 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~593_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~592_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~592_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~592_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~592_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~593_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~593 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~593 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~594 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~594_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~591_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~593_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~591_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~593_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~594_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~594 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~594 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~595 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~595_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~595_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~595 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~595 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~596 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~596_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~595_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~595_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~595_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~595_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~596_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~596 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~596 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~597 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~597_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~594_combout  & ((\datapath_0|datamem_module_0|output_data~596_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~594_combout  & (\datapath_0|datamem_module_0|output_data~589_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~594_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~589_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~594_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~596_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~597_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~597 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~597 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~598 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~598_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~598_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~598 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~598 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~599 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~599_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~598_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~598_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~598_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~598_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~599_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~599 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~599 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~609 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~609_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~609_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~609 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~609 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~610 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~610_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~609_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~609_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~609_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~609_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~610_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~610 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~610 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~611 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~611_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~611_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~611 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~611 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~612 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~612_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~611_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~611_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~611_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~611_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~612_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~612 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~612 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~613 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~613_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~613_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~613 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~613 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~614 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~614_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~613_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~613_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~613_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~613_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~614_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~614 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~614 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~615 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~615_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~612_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~614_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~612_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~614_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~615_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~615 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~615 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~616 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~616_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~616_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~616 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~616 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~617 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~617_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~616_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~616_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~616_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~616_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~617_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~617 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~617 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~618 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~618_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~615_combout  & ((\datapath_0|datamem_module_0|output_data~617_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~615_combout  & (\datapath_0|datamem_module_0|output_data~610_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~615_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~610_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~615_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~617_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~618_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~618 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~618 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~619 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~619_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~619_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~619 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~619 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~620 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~620_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~619_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~619_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~619_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~619_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~620_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~620 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~620 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~630 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~630_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~630_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~630 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~630 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~631 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~631_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~630_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~630_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~630_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~630_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~631_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~631 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~631 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~632 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~632_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~632_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~632 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~632 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~633 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~633_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~632_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~632_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~632_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~632_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~633_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~633 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~633 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~634 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~634_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~634_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~634 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~634 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~635 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~635_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~634_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~634_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~634_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~634_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~635_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~635 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~635 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~636 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~636_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|output_data~633_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~635_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|output_data~633_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|output_data~635_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~636_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~636 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~636 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~637 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~637_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~637_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~637 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~637 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~638 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~638_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~637_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~637_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~637_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~637_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~638_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~638 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~638 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~639 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~639_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~636_combout  & ((\datapath_0|datamem_module_0|output_data~638_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~636_combout  & (\datapath_0|datamem_module_0|output_data~631_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~636_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~631_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~636_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~638_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~639_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~639 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~639 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~640 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~640_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~640_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~640 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~640 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~641 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~641_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~640_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~640_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~640_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~640_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~641_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~641 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~641 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~651 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~651_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x25|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x17|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~651_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~651 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~651 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~652 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~652_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~651_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~651_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~651_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x21|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~651_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x29|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~652_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~652 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~652 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~653 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~653_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x22|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x18|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~653_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~653 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~653 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~654 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~654_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~653_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~653_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~653_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x26|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~653_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x30|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~654_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~654 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~654 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~655 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~655_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x20|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x16|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~655_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~655 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~655 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~656 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~656_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~655_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~655_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~655_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x24|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~655_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x28|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~656_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~656 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~656 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~657 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~657_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|output_data~654_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~656_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|output_data~654_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|output_data~656_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~657_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~657 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~657 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~658 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~658_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x27|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x19|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~658_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~658 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~658 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~659 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~659_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~658_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~658_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~658_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x23|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~658_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x31|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~659_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~659 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~659 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~660 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~660_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~657_combout  & ((\datapath_0|datamem_module_0|output_data~659_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~657_combout  & (\datapath_0|datamem_module_0|output_data~652_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~657_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~652_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~657_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~659_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~660_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~660 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~660 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~661 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~661_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~661_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~661 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~661 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~662 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~662_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~661_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~661_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~661_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~661_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~662_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~662 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~662 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [7]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [8]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [9]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [10]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [11]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [12]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [13]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [14]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [15]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [16]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [17]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [18]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [19]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [20]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [21]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [22]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [23]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [24]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [25]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [26]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [27]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [28]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [29]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [30]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [31]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [8]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [9]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [10]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [11]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [12]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [13]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [14]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [15]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [16]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [17]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [18]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [19]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [20]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [21]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [22]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [23]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [24]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [25]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [26]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [27]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [28]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [29]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [30]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [31]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux26~0 (
// Equation(s):
// \controller_0|Mux26~0_combout  = (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3] & !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]))

	.dataa(gnd),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.cin(gnd),
	.combout(\controller_0|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux26~0 .lut_mask = 16'h0003;
defparam \controller_0|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux26~1 (
// Equation(s):
// \controller_0|Mux26~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5] & \controller_0|Mux26~0_combout ))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datac(\controller_0|Mux26~0_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux26~1 .lut_mask = 16'h8080;
defparam \controller_0|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux32~0 (
// Equation(s):
// \controller_0|Mux32~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]) # ((!\controller_0|Mux26~0_combout ) # (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datab(gnd),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datad(\controller_0|Mux26~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Mux32~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux32~0 .lut_mask = 16'hAFFF;
defparam \controller_0|Mux32~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux30~0 (
// Equation(s):
// \controller_0|Mux30~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]) # ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]) # (!\controller_0|Mux26~0_combout ))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datac(gnd),
	.datad(\controller_0|Mux26~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux30~0 .lut_mask = 16'hEEFF;
defparam \controller_0|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux31~0 (
// Equation(s):
// \controller_0|Mux31~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & 
// !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4])))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.cin(gnd),
	.combout(\controller_0|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux31~0 .lut_mask = 16'h0080;
defparam \controller_0|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux31~1 (
// Equation(s):
// \controller_0|Mux31~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3] & \controller_0|Mux31~0_combout )

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.datab(\controller_0|Mux31~0_combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux31~1 .lut_mask = 16'h8888;
defparam \controller_0|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux27~0 (
// Equation(s):
// \controller_0|Mux27~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5] & 
// !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23])))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.cin(gnd),
	.combout(\controller_0|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux27~0 .lut_mask = 16'h0080;
defparam \controller_0|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux33~0 (
// Equation(s):
// \controller_0|Mux33~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]) # ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]) # ((!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]) # 
// (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2])))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.cin(gnd),
	.combout(\controller_0|Mux33~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux33~0 .lut_mask = 16'hEFFF;
defparam \controller_0|Mux33~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux25~0 (
// Equation(s):
// \controller_0|Mux25~0_combout  = (\controller_0|Mux31~0_combout  & !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3])

	.dataa(\controller_0|Mux31~0_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.cin(gnd),
	.combout(\controller_0|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux25~0 .lut_mask = 16'h00AA;
defparam \controller_0|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux29~0 (
// Equation(s):
// \controller_0|Mux29~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3] & ((!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]))) # 
// (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4])))) # (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & 
// ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4])) # (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & 
// ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3])))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.cin(gnd),
	.combout(\controller_0|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux29~0 .lut_mask = 16'h19F8;
defparam \controller_0|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux29~1 (
// Equation(s):
// \controller_0|Mux29~1_combout  = (\controller_0|Mux29~0_combout ) # ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4] & 
// !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5])))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datad(\controller_0|Mux29~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux29~1 .lut_mask = 16'hFF02;
defparam \controller_0|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux24~0 (
// Equation(s):
// \controller_0|Mux24~0_combout  = (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3])

	.dataa(gnd),
	.datab(gnd),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.cin(gnd),
	.combout(\controller_0|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux24~0 .lut_mask = 16'h000F;
defparam \controller_0|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux24~1 (
// Equation(s):
// \controller_0|Mux24~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & (\controller_0|Mux24~0_combout  & 
// !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4])))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datac(\controller_0|Mux24~0_combout ),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.cin(gnd),
	.combout(\controller_0|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux24~1 .lut_mask = 16'h0080;
defparam \controller_0|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux23~0 (
// Equation(s):
// \controller_0|Mux23~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5] & (\controller_0|Mux26~0_combout  & !\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.datab(\controller_0|Mux26~0_combout ),
	.datac(gnd),
	.datad(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.cin(gnd),
	.combout(\controller_0|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux23~0 .lut_mask = 16'h0088;
defparam \controller_0|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~0_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~0_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[22]~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~1_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~1_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[26]~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~2_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~2_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[18]~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~3_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~3_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[30]~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~4 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~4_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~4 .lut_mask = 16'h0200;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~4_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~4_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[25]~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~5 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~5_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~5 .lut_mask = 16'h0020;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~5_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~5_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[21]~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~6_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~6_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[17]~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~7_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~7_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[29]~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~8_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~8_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[20]~8 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~9_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~9_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[24]~9 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~10_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~10_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[16]~10 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~11_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~11_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[28]~11 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~12_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~12_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[27]~12 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~13_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~13_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[23]~13 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~14_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~14_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[19]~14 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~15_combout  & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datac(\datapath_0|datamem_module_0|datamem_0|Ram0~15_combout ),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[31]~15 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~4_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~4_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[9]~17 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~5_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~5_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[5]~20 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux31~3_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[0]~0 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[0]~0_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [0] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [0]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[0]~0 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux30~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux29~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[2]~2 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[2]~2_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [2]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[2]~2 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux28~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux27~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[4]~4 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[4]~4_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [4] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [4]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[4]~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[4]~4 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[4]~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux26~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux25~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[6]~6 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[6]~6_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [6] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [6]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[6]~6 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux24~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux23~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux22~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux21~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux20~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux19~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux18~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux17~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux16~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux15~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~0 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~0_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [16] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [16]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~0 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux14~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux13~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux12~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux11~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~4 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~4_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [20] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [20]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~4 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux10~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux9~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux8~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux7~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux6~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux5~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux4~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux3~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux2~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux1~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|forward_mux_1|Mux0~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux24~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux24~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux24~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7]),
	.datab(\datapath_0|forward_mux_1|Mux24~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux24~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux24~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux24~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux23~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux23~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux23~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8]),
	.datab(\datapath_0|forward_mux_1|Mux23~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux23~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux23~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux23~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux22~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux22~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux22~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9]),
	.datab(\datapath_0|forward_mux_1|Mux22~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux22~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux22~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux22~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux21~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux21~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux21~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10]),
	.datab(\datapath_0|forward_mux_1|Mux21~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux21~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux21~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux21~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux19~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux19~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux19~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12]),
	.datab(\datapath_0|forward_mux_1|Mux19~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux19~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux19~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux19~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux17~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux17~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux17~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14]),
	.datab(\datapath_0|forward_mux_1|Mux17~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux17~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux17~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux17~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux14~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux14~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux14~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17]),
	.datab(\datapath_0|forward_mux_1|Mux14~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux14~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux14~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux14~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux13~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux13~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux13~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18]),
	.datab(\datapath_0|forward_mux_1|Mux13~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux13~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux13~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux13~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux12~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux12~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux12~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19]),
	.datab(\datapath_0|forward_mux_1|Mux12~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux12~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux12~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux12~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux9~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux9~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux9~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22]),
	.datab(\datapath_0|forward_mux_1|Mux9~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux9~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux9~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux9~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux7~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux7~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux7~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24]),
	.datab(\datapath_0|forward_mux_1|Mux7~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux7~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux7~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux7~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux6~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux6~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux6~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25]),
	.datab(\datapath_0|forward_mux_1|Mux6~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux6~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux6~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux6~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux5~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux5~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux5~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26]),
	.datab(\datapath_0|forward_mux_1|Mux5~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux5~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux5~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux5~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux4~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux4~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux4~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27]),
	.datab(\datapath_0|forward_mux_1|Mux4~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux4~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux4~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux4~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux3~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux3~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux3~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28]),
	.datab(\datapath_0|forward_mux_1|Mux3~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux3~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux3~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux3~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux2~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux2~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux2~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29]),
	.datab(\datapath_0|forward_mux_1|Mux2~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux2~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux2~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux2~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux1~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux1~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux1~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30]),
	.datab(\datapath_0|forward_mux_1|Mux1~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux1~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux1~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux0~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux0~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux0~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31]),
	.datab(\datapath_0|forward_mux_1|Mux0~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux0~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[0] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [0] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [0]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~20_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~20_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [0]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[0] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[0] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[2] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [2] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [2]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~62_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~62_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [2]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[2] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[2] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[4] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [4] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [4]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~104_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~104_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [4]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[4] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[4] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[6] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [6] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [6]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~146_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~146_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [6]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[6] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[6] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[16] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [16] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [16]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~356_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~356_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [16]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [16]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[16] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[16] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[20] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [20] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [20]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~440_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~440_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [20]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [20]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[20] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[20] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_JTU_mux_sel (
// Equation(s):
// \controller_0|internal_JTU_mux_sel~combout  = (\controller_0|WideNor1~combout  & (\controller_0|decoded_cluster.JALR_1876~combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_JTU_mux_sel~combout )))

	.dataa(gnd),
	.datab(\controller_0|decoded_cluster.JALR_1876~combout ),
	.datac(\controller_0|internal_JTU_mux_sel~combout ),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_JTU_mux_sel~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_JTU_mux_sel .lut_mask = 16'hCCF0;
defparam \controller_0|internal_JTU_mux_sel .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[0] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [0] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[0]~0_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [0])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[0]~0_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[0] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[0] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[2] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [2] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[2]~2_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [2])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[2]~2_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[2] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[2] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[4] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [4] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[4]~4_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [4])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[4]~4_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[4] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[4] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[6] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [6] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[6]~6_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [6])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[6]~6_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[6] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[6] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[0] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [0] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~0_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [0])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~0_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[0] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[0] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[4] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [4] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~4_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [4])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~4_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[4] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[4] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[0]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[0]~output .bus_hold = "false";
defparam \debug_pc_output[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[1]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[1]~output .bus_hold = "false";
defparam \debug_pc_output[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[2]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[2]~output .bus_hold = "false";
defparam \debug_pc_output[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[3]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[3]~output .bus_hold = "false";
defparam \debug_pc_output[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[4]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[4]~output .bus_hold = "false";
defparam \debug_pc_output[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[5]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[5]~output .bus_hold = "false";
defparam \debug_pc_output[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[6]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[6]~output .bus_hold = "false";
defparam \debug_pc_output[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[7]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[7]~output .bus_hold = "false";
defparam \debug_pc_output[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[8]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[8]~output .bus_hold = "false";
defparam \debug_pc_output[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[9]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[9]~output .bus_hold = "false";
defparam \debug_pc_output[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[10]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[10]~output .bus_hold = "false";
defparam \debug_pc_output[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[11]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[11]~output .bus_hold = "false";
defparam \debug_pc_output[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[12]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[12]~output .bus_hold = "false";
defparam \debug_pc_output[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[13]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[13]~output .bus_hold = "false";
defparam \debug_pc_output[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[14]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[14]~output .bus_hold = "false";
defparam \debug_pc_output[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[15]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[15]~output .bus_hold = "false";
defparam \debug_pc_output[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[16]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[16]~output .bus_hold = "false";
defparam \debug_pc_output[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[17]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[17]~output .bus_hold = "false";
defparam \debug_pc_output[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[18]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[18]~output .bus_hold = "false";
defparam \debug_pc_output[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[19]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[19]~output .bus_hold = "false";
defparam \debug_pc_output[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[20]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[20]~output .bus_hold = "false";
defparam \debug_pc_output[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[21]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[21]~output .bus_hold = "false";
defparam \debug_pc_output[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[22]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[22]~output .bus_hold = "false";
defparam \debug_pc_output[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[23]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[23]~output .bus_hold = "false";
defparam \debug_pc_output[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[24]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[24]~output .bus_hold = "false";
defparam \debug_pc_output[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[25]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[25]~output .bus_hold = "false";
defparam \debug_pc_output[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[26]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[26]~output .bus_hold = "false";
defparam \debug_pc_output[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[27]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[27]~output .bus_hold = "false";
defparam \debug_pc_output[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[28]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[28]~output .bus_hold = "false";
defparam \debug_pc_output[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[29]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[29]~output .bus_hold = "false";
defparam \debug_pc_output[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[30]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[30]~output .bus_hold = "false";
defparam \debug_pc_output[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_pc_output[31]~output (
	.i(\datapath_0|program_counter_0|internal_register|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_pc_output[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_pc_output[31]~output .bus_hold = "false";
defparam \debug_pc_output[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[0]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[0]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[1]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[1]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[2]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[2]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[3]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[3]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[4]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[4]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[5]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[5]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[6]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[6]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[7]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[7]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[8]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[8]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[9]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[9]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[10]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[10]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[11]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[11]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[12]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[12]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[13]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[13]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[14]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[14]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[15]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[15]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[16]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[16]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[17]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[17]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[18]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[18]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[19]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[19]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[20]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[20]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[21]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[21]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[22]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[22]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[23]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[23]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[24]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[24]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[25]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[25]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[26]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[26]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[27]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[27]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[28]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[28]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[29]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[29]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[30]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[30]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x31_output[31]~output (
	.i(\datapath_0|register_file_0|reg_x31|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x31_output[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x31_output[31]~output .bus_hold = "false";
defparam \debug_regfile_x31_output[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[0]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[0]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[1]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[1]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[2]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[2]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[3]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[3]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[4]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[4]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[5]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[5]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[6]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[6]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[7]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[7]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[8]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[8]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[9]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[9]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[10]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[10]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[11]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[11]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[12]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[12]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[13]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[13]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[14]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[14]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[15]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[15]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[16]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[16]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[17]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[17]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[18]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[18]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[19]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[19]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[20]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[20]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[21]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[21]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[22]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[22]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[23]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[23]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[24]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[24]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[25]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[25]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[26]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[26]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[27]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[27]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[28]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[28]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[29]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[29]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[30]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[30]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x1_output[31]~output (
	.i(\datapath_0|register_file_0|reg_x1|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x1_output[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x1_output[31]~output .bus_hold = "false";
defparam \debug_regfile_x1_output[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[0]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[0]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[1]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[1]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[2]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[2]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[3]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[3]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[4]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[4]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[5]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[5]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[6]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[6]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[7]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[7]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[8]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[8]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[9]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[9]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[10]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[10]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[11]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[11]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[12]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[12]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[13]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[13]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[14]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[14]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[15]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[15]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[16]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[16]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[17]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[17]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[18]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[18]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[19]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[19]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[20]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[20]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[21]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[21]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[22]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[22]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[23]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[23]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[24]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[24]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[25]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[25]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[26]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[26]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[27]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[27]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[28]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[28]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[29]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[29]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[30]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[30]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_x2_output[31]~output (
	.i(\datapath_0|register_file_0|reg_x2|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_x2_output[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_x2_output[31]~output .bus_hold = "false";
defparam \debug_regfile_x2_output[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[0]~output (
	.i(\datapath_0|ALU_0|ALU_output [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[0]~output .bus_hold = "false";
defparam \debug_ALU_output[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[1]~output (
	.i(\datapath_0|ALU_0|ALU_output [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[1]~output .bus_hold = "false";
defparam \debug_ALU_output[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[2]~output (
	.i(\datapath_0|ALU_0|ALU_output [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[2]~output .bus_hold = "false";
defparam \debug_ALU_output[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[3]~output (
	.i(\datapath_0|ALU_0|ALU_output [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[3]~output .bus_hold = "false";
defparam \debug_ALU_output[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[4]~output (
	.i(\datapath_0|ALU_0|ALU_output [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[4]~output .bus_hold = "false";
defparam \debug_ALU_output[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[5]~output (
	.i(\datapath_0|ALU_0|ALU_output [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[5]~output .bus_hold = "false";
defparam \debug_ALU_output[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[6]~output (
	.i(\datapath_0|ALU_0|ALU_output [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[6]~output .bus_hold = "false";
defparam \debug_ALU_output[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[7]~output (
	.i(\datapath_0|ALU_0|ALU_output [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[7]~output .bus_hold = "false";
defparam \debug_ALU_output[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[8]~output (
	.i(\datapath_0|ALU_0|ALU_output [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[8]~output .bus_hold = "false";
defparam \debug_ALU_output[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[9]~output (
	.i(\datapath_0|ALU_0|ALU_output [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[9]~output .bus_hold = "false";
defparam \debug_ALU_output[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[10]~output (
	.i(\datapath_0|ALU_0|ALU_output [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[10]~output .bus_hold = "false";
defparam \debug_ALU_output[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[11]~output (
	.i(\datapath_0|ALU_0|ALU_output [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[11]~output .bus_hold = "false";
defparam \debug_ALU_output[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[12]~output (
	.i(\datapath_0|ALU_0|ALU_output [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[12]~output .bus_hold = "false";
defparam \debug_ALU_output[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[13]~output (
	.i(\datapath_0|ALU_0|ALU_output [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[13]~output .bus_hold = "false";
defparam \debug_ALU_output[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[14]~output (
	.i(\datapath_0|ALU_0|ALU_output [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[14]~output .bus_hold = "false";
defparam \debug_ALU_output[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[15]~output (
	.i(\datapath_0|ALU_0|ALU_output [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[15]~output .bus_hold = "false";
defparam \debug_ALU_output[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[16]~output (
	.i(\datapath_0|ALU_0|ALU_output [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[16]~output .bus_hold = "false";
defparam \debug_ALU_output[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[17]~output (
	.i(\datapath_0|ALU_0|ALU_output [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[17]~output .bus_hold = "false";
defparam \debug_ALU_output[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[18]~output (
	.i(\datapath_0|ALU_0|ALU_output [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[18]~output .bus_hold = "false";
defparam \debug_ALU_output[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[19]~output (
	.i(\datapath_0|ALU_0|ALU_output [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[19]~output .bus_hold = "false";
defparam \debug_ALU_output[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[20]~output (
	.i(\datapath_0|ALU_0|ALU_output [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[20]~output .bus_hold = "false";
defparam \debug_ALU_output[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[21]~output (
	.i(\datapath_0|ALU_0|ALU_output [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[21]~output .bus_hold = "false";
defparam \debug_ALU_output[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[22]~output (
	.i(\datapath_0|ALU_0|ALU_output [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[22]~output .bus_hold = "false";
defparam \debug_ALU_output[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[23]~output (
	.i(\datapath_0|ALU_0|ALU_output [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[23]~output .bus_hold = "false";
defparam \debug_ALU_output[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[24]~output (
	.i(\datapath_0|ALU_0|ALU_output [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[24]~output .bus_hold = "false";
defparam \debug_ALU_output[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[25]~output (
	.i(\datapath_0|ALU_0|ALU_output [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[25]~output .bus_hold = "false";
defparam \debug_ALU_output[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[26]~output (
	.i(\datapath_0|ALU_0|ALU_output [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[26]~output .bus_hold = "false";
defparam \debug_ALU_output[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[27]~output (
	.i(\datapath_0|ALU_0|ALU_output [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[27]~output .bus_hold = "false";
defparam \debug_ALU_output[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[28]~output (
	.i(\datapath_0|ALU_0|ALU_output [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[28]~output .bus_hold = "false";
defparam \debug_ALU_output[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[29]~output (
	.i(\datapath_0|ALU_0|ALU_output [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[29]~output .bus_hold = "false";
defparam \debug_ALU_output[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[30]~output (
	.i(\datapath_0|ALU_0|ALU_output [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[30]~output .bus_hold = "false";
defparam \debug_ALU_output[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output[31]~output (
	.i(\datapath_0|ALU_0|ALU_output [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output[31]~output .bus_hold = "false";
defparam \debug_ALU_output[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_regfile_write~output (
	.i(\controller_0|internal_reg_file_write~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_regfile_write~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_regfile_write~output .bus_hold = "false";
defparam \debug_regfile_write~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[0]~output (
	.i(\datapath_0|forward_mux_0|Mux31~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[0]~output .bus_hold = "false";
defparam \debug_ALU_input_0[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[1]~output (
	.i(\datapath_0|forward_mux_0|Mux30~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[1]~output .bus_hold = "false";
defparam \debug_ALU_input_0[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[2]~output (
	.i(\datapath_0|forward_mux_0|Mux29~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[2]~output .bus_hold = "false";
defparam \debug_ALU_input_0[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[3]~output (
	.i(\datapath_0|forward_mux_0|Mux28~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[3]~output .bus_hold = "false";
defparam \debug_ALU_input_0[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[4]~output (
	.i(\datapath_0|forward_mux_0|Mux27~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[4]~output .bus_hold = "false";
defparam \debug_ALU_input_0[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[5]~output (
	.i(\datapath_0|forward_mux_0|Mux26~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[5]~output .bus_hold = "false";
defparam \debug_ALU_input_0[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[6]~output (
	.i(\datapath_0|forward_mux_0|Mux25~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[6]~output .bus_hold = "false";
defparam \debug_ALU_input_0[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[7]~output (
	.i(\datapath_0|forward_mux_0|Mux24~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[7]~output .bus_hold = "false";
defparam \debug_ALU_input_0[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[8]~output (
	.i(\datapath_0|forward_mux_0|Mux23~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[8]~output .bus_hold = "false";
defparam \debug_ALU_input_0[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[9]~output (
	.i(\datapath_0|forward_mux_0|Mux22~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[9]~output .bus_hold = "false";
defparam \debug_ALU_input_0[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[10]~output (
	.i(\datapath_0|forward_mux_0|Mux21~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[10]~output .bus_hold = "false";
defparam \debug_ALU_input_0[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[11]~output (
	.i(\datapath_0|forward_mux_0|Mux20~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[11]~output .bus_hold = "false";
defparam \debug_ALU_input_0[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[12]~output (
	.i(\datapath_0|forward_mux_0|Mux19~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[12]~output .bus_hold = "false";
defparam \debug_ALU_input_0[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[13]~output (
	.i(\datapath_0|forward_mux_0|Mux18~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[13]~output .bus_hold = "false";
defparam \debug_ALU_input_0[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[14]~output (
	.i(\datapath_0|forward_mux_0|Mux17~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[14]~output .bus_hold = "false";
defparam \debug_ALU_input_0[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[15]~output (
	.i(\datapath_0|forward_mux_0|Mux16~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[15]~output .bus_hold = "false";
defparam \debug_ALU_input_0[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[16]~output (
	.i(\datapath_0|forward_mux_0|Mux15~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[16]~output .bus_hold = "false";
defparam \debug_ALU_input_0[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[17]~output (
	.i(\datapath_0|forward_mux_0|Mux14~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[17]~output .bus_hold = "false";
defparam \debug_ALU_input_0[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[18]~output (
	.i(\datapath_0|forward_mux_0|Mux13~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[18]~output .bus_hold = "false";
defparam \debug_ALU_input_0[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[19]~output (
	.i(\datapath_0|forward_mux_0|Mux12~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[19]~output .bus_hold = "false";
defparam \debug_ALU_input_0[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[20]~output (
	.i(\datapath_0|forward_mux_0|Mux11~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[20]~output .bus_hold = "false";
defparam \debug_ALU_input_0[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[21]~output (
	.i(\datapath_0|forward_mux_0|Mux10~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[21]~output .bus_hold = "false";
defparam \debug_ALU_input_0[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[22]~output (
	.i(\datapath_0|forward_mux_0|Mux9~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[22]~output .bus_hold = "false";
defparam \debug_ALU_input_0[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[23]~output (
	.i(\datapath_0|forward_mux_0|Mux8~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[23]~output .bus_hold = "false";
defparam \debug_ALU_input_0[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[24]~output (
	.i(\datapath_0|forward_mux_0|Mux7~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[24]~output .bus_hold = "false";
defparam \debug_ALU_input_0[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[25]~output (
	.i(\datapath_0|forward_mux_0|Mux6~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[25]~output .bus_hold = "false";
defparam \debug_ALU_input_0[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[26]~output (
	.i(\datapath_0|forward_mux_0|Mux5~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[26]~output .bus_hold = "false";
defparam \debug_ALU_input_0[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[27]~output (
	.i(\datapath_0|forward_mux_0|Mux4~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[27]~output .bus_hold = "false";
defparam \debug_ALU_input_0[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[28]~output (
	.i(\datapath_0|forward_mux_0|Mux3~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[28]~output .bus_hold = "false";
defparam \debug_ALU_input_0[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[29]~output (
	.i(\datapath_0|forward_mux_0|Mux2~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[29]~output .bus_hold = "false";
defparam \debug_ALU_input_0[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[30]~output (
	.i(\datapath_0|forward_mux_0|Mux1~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[30]~output .bus_hold = "false";
defparam \debug_ALU_input_0[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_0[31]~output (
	.i(\datapath_0|forward_mux_0|Mux0~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_0[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_0[31]~output .bus_hold = "false";
defparam \debug_ALU_input_0[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[0]~output (
	.i(\datapath_0|mux_1|output_0[0]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[0]~output .bus_hold = "false";
defparam \debug_ALU_input_1[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[1]~output (
	.i(\datapath_0|mux_1|output_0[1]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[1]~output .bus_hold = "false";
defparam \debug_ALU_input_1[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[2]~output (
	.i(\datapath_0|mux_1|output_0[2]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[2]~output .bus_hold = "false";
defparam \debug_ALU_input_1[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[3]~output (
	.i(\datapath_0|mux_1|output_0[3]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[3]~output .bus_hold = "false";
defparam \debug_ALU_input_1[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[4]~output (
	.i(\datapath_0|mux_1|output_0[4]~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[4]~output .bus_hold = "false";
defparam \debug_ALU_input_1[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[5]~output (
	.i(\datapath_0|mux_1|output_0[5]~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[5]~output .bus_hold = "false";
defparam \debug_ALU_input_1[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[6]~output (
	.i(\datapath_0|mux_1|output_0[6]~6_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[6]~output .bus_hold = "false";
defparam \debug_ALU_input_1[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[7]~output (
	.i(\datapath_0|mux_1|output_0[7]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[7]~output .bus_hold = "false";
defparam \debug_ALU_input_1[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[8]~output (
	.i(\datapath_0|mux_1|output_0[8]~8_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[8]~output .bus_hold = "false";
defparam \debug_ALU_input_1[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[9]~output (
	.i(\datapath_0|mux_1|output_0[9]~9_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[9]~output .bus_hold = "false";
defparam \debug_ALU_input_1[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[10]~output (
	.i(\datapath_0|mux_1|output_0[10]~10_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[10]~output .bus_hold = "false";
defparam \debug_ALU_input_1[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[11]~output (
	.i(\datapath_0|mux_1|output_0[11]~11_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[11]~output .bus_hold = "false";
defparam \debug_ALU_input_1[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[12]~output (
	.i(\datapath_0|mux_1|output_0[12]~12_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[12]~output .bus_hold = "false";
defparam \debug_ALU_input_1[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[13]~output (
	.i(\datapath_0|mux_1|output_0[13]~13_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[13]~output .bus_hold = "false";
defparam \debug_ALU_input_1[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[14]~output (
	.i(\datapath_0|mux_1|output_0[14]~14_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[14]~output .bus_hold = "false";
defparam \debug_ALU_input_1[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[15]~output (
	.i(\datapath_0|mux_1|output_0[15]~15_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[15]~output .bus_hold = "false";
defparam \debug_ALU_input_1[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[16]~output (
	.i(\datapath_0|mux_1|output_0[16]~16_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[16]~output .bus_hold = "false";
defparam \debug_ALU_input_1[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[17]~output (
	.i(\datapath_0|mux_1|output_0[17]~17_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[17]~output .bus_hold = "false";
defparam \debug_ALU_input_1[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[18]~output (
	.i(\datapath_0|mux_1|output_0[18]~18_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[18]~output .bus_hold = "false";
defparam \debug_ALU_input_1[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[19]~output (
	.i(\datapath_0|mux_1|output_0[19]~19_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[19]~output .bus_hold = "false";
defparam \debug_ALU_input_1[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[20]~output (
	.i(\datapath_0|mux_1|output_0[20]~20_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[20]~output .bus_hold = "false";
defparam \debug_ALU_input_1[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[21]~output (
	.i(\datapath_0|mux_1|output_0[21]~21_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[21]~output .bus_hold = "false";
defparam \debug_ALU_input_1[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[22]~output (
	.i(\datapath_0|mux_1|output_0[22]~22_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[22]~output .bus_hold = "false";
defparam \debug_ALU_input_1[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[23]~output (
	.i(\datapath_0|mux_1|output_0[23]~23_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[23]~output .bus_hold = "false";
defparam \debug_ALU_input_1[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[24]~output (
	.i(\datapath_0|mux_1|output_0[24]~24_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[24]~output .bus_hold = "false";
defparam \debug_ALU_input_1[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[25]~output (
	.i(\datapath_0|mux_1|output_0[25]~25_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[25]~output .bus_hold = "false";
defparam \debug_ALU_input_1[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[26]~output (
	.i(\datapath_0|mux_1|output_0[26]~26_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[26]~output .bus_hold = "false";
defparam \debug_ALU_input_1[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[27]~output (
	.i(\datapath_0|mux_1|output_0[27]~27_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[27]~output .bus_hold = "false";
defparam \debug_ALU_input_1[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[28]~output (
	.i(\datapath_0|mux_1|output_0[28]~28_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[28]~output .bus_hold = "false";
defparam \debug_ALU_input_1[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[29]~output (
	.i(\datapath_0|mux_1|output_0[29]~29_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[29]~output .bus_hold = "false";
defparam \debug_ALU_input_1[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[30]~output (
	.i(\datapath_0|mux_1|output_0[30]~30_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[30]~output .bus_hold = "false";
defparam \debug_ALU_input_1[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_input_1[31]~output (
	.i(\datapath_0|mux_1|output_0[31]~31_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_input_1[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_input_1[31]~output .bus_hold = "false";
defparam \debug_ALU_input_1[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0[0]~output (
	.i(\controller_0|internal_reg_file_read_address_0 [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0[0]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0[1]~output (
	.i(\controller_0|internal_reg_file_read_address_0 [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0[1]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0[2]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0[3]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0[4]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0[4]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_1[0]~output (
	.i(\controller_0|internal_reg_file_read_address_1 [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_1[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_1[0]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_1[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_1[1]~output (
	.i(\controller_0|internal_reg_file_read_address_1 [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_1[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_1[1]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_1[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_1[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_1[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_1[2]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_1[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_1[3]~output (
	.i(\controller_0|internal_reg_file_read_address_1 [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_1[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_1[3]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_1[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_1[4]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_1[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_1[4]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_1[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_mux0_sel[0]~output (
	.i(\controller_0|internal_mux0_sel [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_mux0_sel[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_mux0_sel[0]~output .bus_hold = "false";
defparam \debug_mux0_sel[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_mux0_sel[1]~output (
	.i(\controller_0|internal_mux0_sel [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_mux0_sel[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_mux0_sel[1]~output .bus_hold = "false";
defparam \debug_mux0_sel[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[0]~output (
	.i(\controller_0|internal_immediate [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[0]~output .bus_hold = "false";
defparam \debug_immediate[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[1]~output (
	.i(\controller_0|internal_immediate [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[1]~output .bus_hold = "false";
defparam \debug_immediate[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[2]~output (
	.i(\controller_0|internal_immediate [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[2]~output .bus_hold = "false";
defparam \debug_immediate[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[3]~output (
	.i(\controller_0|internal_immediate [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[3]~output .bus_hold = "false";
defparam \debug_immediate[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[4]~output (
	.i(\controller_0|internal_immediate [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[4]~output .bus_hold = "false";
defparam \debug_immediate[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[5]~output (
	.i(\controller_0|internal_immediate [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[5]~output .bus_hold = "false";
defparam \debug_immediate[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[6]~output (
	.i(\controller_0|internal_immediate [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[6]~output .bus_hold = "false";
defparam \debug_immediate[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[7]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[7]~output .bus_hold = "false";
defparam \debug_immediate[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[8]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[8]~output .bus_hold = "false";
defparam \debug_immediate[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[9]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[9]~output .bus_hold = "false";
defparam \debug_immediate[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[10]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[10]~output .bus_hold = "false";
defparam \debug_immediate[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[11]~output (
	.i(\controller_0|internal_immediate [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[11]~output .bus_hold = "false";
defparam \debug_immediate[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[12]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[12]~output .bus_hold = "false";
defparam \debug_immediate[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[13]~output (
	.i(\controller_0|internal_immediate [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[13]~output .bus_hold = "false";
defparam \debug_immediate[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[14]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[14]~output .bus_hold = "false";
defparam \debug_immediate[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[15]~output (
	.i(\controller_0|internal_immediate [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[15]~output .bus_hold = "false";
defparam \debug_immediate[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[16]~output (
	.i(\controller_0|internal_immediate [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[16]~output .bus_hold = "false";
defparam \debug_immediate[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[17]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[17]~output .bus_hold = "false";
defparam \debug_immediate[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[18]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[18]~output .bus_hold = "false";
defparam \debug_immediate[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[19]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[19]~output .bus_hold = "false";
defparam \debug_immediate[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[20]~output (
	.i(\controller_0|internal_immediate [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[20]~output .bus_hold = "false";
defparam \debug_immediate[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[21]~output (
	.i(\controller_0|internal_immediate [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[21]~output .bus_hold = "false";
defparam \debug_immediate[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[22]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[22]~output .bus_hold = "false";
defparam \debug_immediate[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[23]~output (
	.i(\controller_0|internal_immediate [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[23]~output .bus_hold = "false";
defparam \debug_immediate[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[24]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[24]~output .bus_hold = "false";
defparam \debug_immediate[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[25]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[25]~output .bus_hold = "false";
defparam \debug_immediate[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[26]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[26]~output .bus_hold = "false";
defparam \debug_immediate[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[27]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[27]~output .bus_hold = "false";
defparam \debug_immediate[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[28]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[28]~output .bus_hold = "false";
defparam \debug_immediate[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[29]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[29]~output .bus_hold = "false";
defparam \debug_immediate[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[30]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[30]~output .bus_hold = "false";
defparam \debug_immediate[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_immediate[31]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_immediate[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_immediate[31]~output .bus_hold = "false";
defparam \debug_immediate[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_operation[0]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_operation[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_operation[0]~output .bus_hold = "false";
defparam \debug_ALU_operation[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_operation[1]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_operation[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_operation[1]~output .bus_hold = "false";
defparam \debug_ALU_operation[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_operation[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_operation[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_operation[2]~output .bus_hold = "false";
defparam \debug_ALU_operation[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_operation[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_operation[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_operation[3]~output .bus_hold = "false";
defparam \debug_ALU_operation[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_0[0]~output (
	.i(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_0[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_0[0]~output .bus_hold = "false";
defparam \debug_forward_mux_0[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_0[1]~output (
	.i(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_0[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_0[1]~output .bus_hold = "false";
defparam \debug_forward_mux_0[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_0[2]~output (
	.i(\datapath_0|FU_0|forward_mux_0_control[2]~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_0[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_0[2]~output .bus_hold = "false";
defparam \debug_forward_mux_0[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_1[0]~output (
	.i(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_1[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_1[0]~output .bus_hold = "false";
defparam \debug_forward_mux_1[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_1[1]~output (
	.i(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_1[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_1[1]~output .bus_hold = "false";
defparam \debug_forward_mux_1[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_forward_mux_1[2]~output (
	.i(\datapath_0|FU_0|forward_mux_1_control[2]~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_forward_mux_1[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_forward_mux_1[2]~output .bus_hold = "false";
defparam \debug_forward_mux_1[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0_ID_EXE[0]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0_ID_EXE[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0_ID_EXE[0]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0_ID_EXE[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0_ID_EXE[1]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0_ID_EXE[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0_ID_EXE[1]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0_ID_EXE[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0_ID_EXE[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0_ID_EXE[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0_ID_EXE[2]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0_ID_EXE[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0_ID_EXE[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0_ID_EXE[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0_ID_EXE[3]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0_ID_EXE[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_read_address_0_ID_EXE[4]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_read_address_0_ID_EXE[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_read_address_0_ID_EXE[4]~output .bus_hold = "false";
defparam \debug_reg_file_read_address_0_ID_EXE[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_EX_MEM[0]~output (
	.i(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_EX_MEM[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_EX_MEM[0]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_EX_MEM[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_EX_MEM[1]~output (
	.i(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_EX_MEM[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_EX_MEM[1]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_EX_MEM[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_EX_MEM[2]~output (
	.i(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_EX_MEM[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_EX_MEM[2]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_EX_MEM[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_EX_MEM[3]~output (
	.i(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_EX_MEM[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_EX_MEM[3]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_EX_MEM[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_EX_MEM[4]~output (
	.i(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_EX_MEM[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_EX_MEM[4]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_EX_MEM[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_mux0_sel_MEM_WB[0]~output (
	.i(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_mux0_sel_MEM_WB[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_mux0_sel_MEM_WB[0]~output .bus_hold = "false";
defparam \debug_mux0_sel_MEM_WB[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_mux0_sel_MEM_WB[1]~output (
	.i(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_mux0_sel_MEM_WB[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_mux0_sel_MEM_WB[1]~output .bus_hold = "false";
defparam \debug_mux0_sel_MEM_WB[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_MEM_WB~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_MEM_WB~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_MEM_WB~output .bus_hold = "false";
defparam \debug_reg_file_write_MEM_WB~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_MEM_WB[0]~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_MEM_WB[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_MEM_WB[0]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_MEM_WB[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_MEM_WB[1]~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_MEM_WB[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_MEM_WB[1]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_MEM_WB[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_MEM_WB[2]~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_MEM_WB[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_MEM_WB[2]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_MEM_WB[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_MEM_WB[3]~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_MEM_WB[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_MEM_WB[3]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_MEM_WB[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_reg_file_write_address_MEM_WB[4]~output (
	.i(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_reg_file_write_address_MEM_WB[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_reg_file_write_address_MEM_WB[4]~output .bus_hold = "false";
defparam \debug_reg_file_write_address_MEM_WB[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[0]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[0]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[1]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[1]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[2]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[2]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[3]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[3]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[4]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[4]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[5]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[5]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[6]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[6]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[7]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[7]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[8]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[8]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[9]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[9]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[10]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[10]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[11]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[11]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[12]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[12]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[13]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[13]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[14]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[14]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[15]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[15]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[16]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[16]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[17]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[17]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[18]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[18]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[19]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[19]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[20]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[20]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[21]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[21]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[22]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[22]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[23]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[23]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[24]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[24]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[25]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[25]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[26]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[26]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[27]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[27]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[28]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[28]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[29]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[29]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[30]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[30]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_MEM_WB[31]~output (
	.i(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_MEM_WB[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_MEM_WB[31]~output .bus_hold = "false";
defparam \debug_ALU_output_MEM_WB[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[0]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[0]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[1]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[1]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[2]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[2]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[3]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[3]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[4]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[4]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[5]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[5]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[6]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[6]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[7]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[7]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[8]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[8]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[9]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[9]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[10]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[10]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[11]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[11]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[12]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[12]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[13]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[13]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[14]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[14]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[15]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[15]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[16]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[16]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[17]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[17]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[18]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[18]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[19]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[19]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[20]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[20]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[21]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[21]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[22]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[22]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[23]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[23]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[24]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[24]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[25]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[25]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[26]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[26]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[27]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[27]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[28]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[28]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[29]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[29]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[30]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[30]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_ALU_output_EX_MEM[31]~output (
	.i(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_ALU_output_EX_MEM[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_ALU_output_EX_MEM[31]~output .bus_hold = "false";
defparam \debug_ALU_output_EX_MEM[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[0]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux31~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[0]~output .bus_hold = "false";
defparam \debug_register_file_output_0[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[1]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux30~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[1]~output .bus_hold = "false";
defparam \debug_register_file_output_0[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[2]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux29~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[2]~output .bus_hold = "false";
defparam \debug_register_file_output_0[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[3]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux28~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[3]~output .bus_hold = "false";
defparam \debug_register_file_output_0[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[4]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux27~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[4]~output .bus_hold = "false";
defparam \debug_register_file_output_0[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[5]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux26~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[5]~output .bus_hold = "false";
defparam \debug_register_file_output_0[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[6]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux25~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[6]~output .bus_hold = "false";
defparam \debug_register_file_output_0[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[7]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux24~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[7]~output .bus_hold = "false";
defparam \debug_register_file_output_0[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[8]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux23~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[8]~output .bus_hold = "false";
defparam \debug_register_file_output_0[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[9]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux22~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[9]~output .bus_hold = "false";
defparam \debug_register_file_output_0[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[10]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux21~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[10]~output .bus_hold = "false";
defparam \debug_register_file_output_0[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[11]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux20~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[11]~output .bus_hold = "false";
defparam \debug_register_file_output_0[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[12]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux19~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[12]~output .bus_hold = "false";
defparam \debug_register_file_output_0[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[13]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux18~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[13]~output .bus_hold = "false";
defparam \debug_register_file_output_0[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[14]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux17~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[14]~output .bus_hold = "false";
defparam \debug_register_file_output_0[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[15]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux16~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[15]~output .bus_hold = "false";
defparam \debug_register_file_output_0[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[16]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux15~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[16]~output .bus_hold = "false";
defparam \debug_register_file_output_0[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[17]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux14~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[17]~output .bus_hold = "false";
defparam \debug_register_file_output_0[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[18]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux13~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[18]~output .bus_hold = "false";
defparam \debug_register_file_output_0[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[19]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux12~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[19]~output .bus_hold = "false";
defparam \debug_register_file_output_0[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[20]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux11~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[20]~output .bus_hold = "false";
defparam \debug_register_file_output_0[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[21]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux10~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[21]~output .bus_hold = "false";
defparam \debug_register_file_output_0[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[22]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux9~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[22]~output .bus_hold = "false";
defparam \debug_register_file_output_0[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[23]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux8~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[23]~output .bus_hold = "false";
defparam \debug_register_file_output_0[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[24]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux7~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[24]~output .bus_hold = "false";
defparam \debug_register_file_output_0[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[25]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux6~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[25]~output .bus_hold = "false";
defparam \debug_register_file_output_0[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[26]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux5~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[26]~output .bus_hold = "false";
defparam \debug_register_file_output_0[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[27]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux4~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[27]~output .bus_hold = "false";
defparam \debug_register_file_output_0[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[28]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux3~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[28]~output .bus_hold = "false";
defparam \debug_register_file_output_0[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[29]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux2~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[29]~output .bus_hold = "false";
defparam \debug_register_file_output_0[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[30]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux1~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[30]~output .bus_hold = "false";
defparam \debug_register_file_output_0[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0[31]~output (
	.i(\datapath_0|register_file_0|output_1_mux|Mux0~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0[31]~output .bus_hold = "false";
defparam \debug_register_file_output_0[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[0]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux31~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[0]~output .bus_hold = "false";
defparam \debug_register_file_output_1[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[1]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux30~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[1]~output .bus_hold = "false";
defparam \debug_register_file_output_1[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[2]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux29~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[2]~output .bus_hold = "false";
defparam \debug_register_file_output_1[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[3]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux28~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[3]~output .bus_hold = "false";
defparam \debug_register_file_output_1[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[4]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux27~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[4]~output .bus_hold = "false";
defparam \debug_register_file_output_1[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[5]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux26~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[5]~output .bus_hold = "false";
defparam \debug_register_file_output_1[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[6]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux25~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[6]~output .bus_hold = "false";
defparam \debug_register_file_output_1[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[7]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux24~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[7]~output .bus_hold = "false";
defparam \debug_register_file_output_1[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[8]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux23~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[8]~output .bus_hold = "false";
defparam \debug_register_file_output_1[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[9]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux22~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[9]~output .bus_hold = "false";
defparam \debug_register_file_output_1[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[10]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux21~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[10]~output .bus_hold = "false";
defparam \debug_register_file_output_1[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[11]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux20~6_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[11]~output .bus_hold = "false";
defparam \debug_register_file_output_1[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[12]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux19~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[12]~output .bus_hold = "false";
defparam \debug_register_file_output_1[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[13]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux18~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[13]~output .bus_hold = "false";
defparam \debug_register_file_output_1[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[14]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux17~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[14]~output .bus_hold = "false";
defparam \debug_register_file_output_1[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[15]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux16~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[15]~output .bus_hold = "false";
defparam \debug_register_file_output_1[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[16]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux15~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[16]~output .bus_hold = "false";
defparam \debug_register_file_output_1[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[17]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux14~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[17]~output .bus_hold = "false";
defparam \debug_register_file_output_1[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[18]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux13~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[18]~output .bus_hold = "false";
defparam \debug_register_file_output_1[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[19]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux12~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[19]~output .bus_hold = "false";
defparam \debug_register_file_output_1[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[20]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux11~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[20]~output .bus_hold = "false";
defparam \debug_register_file_output_1[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[21]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux10~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[21]~output .bus_hold = "false";
defparam \debug_register_file_output_1[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[22]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux9~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[22]~output .bus_hold = "false";
defparam \debug_register_file_output_1[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[23]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux8~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[23]~output .bus_hold = "false";
defparam \debug_register_file_output_1[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[24]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux7~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[24]~output .bus_hold = "false";
defparam \debug_register_file_output_1[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[25]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux6~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[25]~output .bus_hold = "false";
defparam \debug_register_file_output_1[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[26]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux5~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[26]~output .bus_hold = "false";
defparam \debug_register_file_output_1[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[27]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux4~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[27]~output .bus_hold = "false";
defparam \debug_register_file_output_1[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[28]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux3~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[28]~output .bus_hold = "false";
defparam \debug_register_file_output_1[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[29]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux2~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[29]~output .bus_hold = "false";
defparam \debug_register_file_output_1[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[30]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux1~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[30]~output .bus_hold = "false";
defparam \debug_register_file_output_1[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1[31]~output (
	.i(\datapath_0|register_file_0|output_2_mux|Mux0~3_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1[31]~output .bus_hold = "false";
defparam \debug_register_file_output_1[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[0]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[0]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[1]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[1]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[2]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[2]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[3]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[3]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[4]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[4]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[5]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[5]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[6]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[6]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[7]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[7]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[8]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[8]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[9]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[9]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[10]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[10]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[11]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[11]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[12]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[12]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[13]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[13]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[14]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[14]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[15]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[15]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[16]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[16]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[17]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[17]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[18]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[18]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[19]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[19]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[20]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[20]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[21]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[21]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[22]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[22]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[23]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[23]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[24]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[24]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[25]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[25]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[26]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[26]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[27]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[27]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[28]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[28]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[29]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[29]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[30]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[30]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_0_ID_EX[31]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_0_ID_EX[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_0_ID_EX[31]~output .bus_hold = "false";
defparam \debug_register_file_output_0_ID_EX[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[0]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[0]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[1]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[1]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[2]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[2]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[3]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[3]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[4]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[4]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[5]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[5]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[6]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[6]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[7]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[7]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[8]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[8]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[9]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[9]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[10]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[10]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[11]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[11]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[12]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[12]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[13]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[13]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[14]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[14]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[15]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[15]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[16]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[16]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[17]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[17]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[18]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[18]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[19]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[19]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[20]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[20]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[21]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[21]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[22]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[22]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[23]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[23]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[24]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [24]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[24]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[25]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [25]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[25]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[26]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [26]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[26]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[27]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [27]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[27]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[28]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [28]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[28]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[29]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [29]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[29]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[30]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [30]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[30]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_register_file_output_1_ID_EX[31]~output (
	.i(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [31]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_register_file_output_1_ID_EX[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_register_file_output_1_ID_EX[31]~output .bus_hold = "false";
defparam \debug_register_file_output_1_ID_EX[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[0]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[0]~output .bus_hold = "false";
defparam \debug_instruction[0]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[1]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[1]~output .bus_hold = "false";
defparam \debug_instruction[1]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[2]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[2]~output .bus_hold = "false";
defparam \debug_instruction[2]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[3]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[3]~output .bus_hold = "false";
defparam \debug_instruction[3]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[4]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[4]~output .bus_hold = "false";
defparam \debug_instruction[4]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[5]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[5]~output .bus_hold = "false";
defparam \debug_instruction[5]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[6]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[6]~output .bus_hold = "false";
defparam \debug_instruction[6]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[7]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[7]~output .bus_hold = "false";
defparam \debug_instruction[7]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[8]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[8]~output .bus_hold = "false";
defparam \debug_instruction[8]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[9]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[9]~output .bus_hold = "false";
defparam \debug_instruction[9]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[10]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[10]~output .bus_hold = "false";
defparam \debug_instruction[10]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[11]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[11]~output .bus_hold = "false";
defparam \debug_instruction[11]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[12]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[12]~output .bus_hold = "false";
defparam \debug_instruction[12]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[13]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[13]~output .bus_hold = "false";
defparam \debug_instruction[13]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[14]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[14]~output .bus_hold = "false";
defparam \debug_instruction[14]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[15]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[15]~output .bus_hold = "false";
defparam \debug_instruction[15]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[16]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[16]~output .bus_hold = "false";
defparam \debug_instruction[16]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[17]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[17]~output .bus_hold = "false";
defparam \debug_instruction[17]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[18]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[18]~output .bus_hold = "false";
defparam \debug_instruction[18]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[19]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[19]~output .bus_hold = "false";
defparam \debug_instruction[19]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[20]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[20]~output .bus_hold = "false";
defparam \debug_instruction[20]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[21]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[21]~output .bus_hold = "false";
defparam \debug_instruction[21]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[22]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[22]~output .bus_hold = "false";
defparam \debug_instruction[22]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[23]~output (
	.i(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[23]~output .bus_hold = "false";
defparam \debug_instruction[23]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[24]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[24]~output .bus_hold = "false";
defparam \debug_instruction[24]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[25]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[25]~output .bus_hold = "false";
defparam \debug_instruction[25]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[26]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[26]~output .bus_hold = "false";
defparam \debug_instruction[26]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[27]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[27]~output .bus_hold = "false";
defparam \debug_instruction[27]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[28]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[28]~output .bus_hold = "false";
defparam \debug_instruction[28]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[29]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[29]~output .bus_hold = "false";
defparam \debug_instruction[29]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[30]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[30]~output .bus_hold = "false";
defparam \debug_instruction[30]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_obuf \debug_instruction[31]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\debug_instruction[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \debug_instruction[31]~output .bus_hold = "false";
defparam \debug_instruction[31]~output .open_drain_output = "false";
// synopsys translate_on

cycloneiv_io_ibuf \clock~input (
	.i(clock),
	.ibar(gnd),
	.o(\clock~input_o ));
// synopsys translate_off
defparam \clock~input .bus_hold = "false";
defparam \clock~input .simulate_z_as = "z";
// synopsys translate_on

dffeas \datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value[1] (
	.clk(\clock~input_o ),
	.d(vcc),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [5] & \datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1])

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datab(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2 .lut_mask = 16'h8888;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[2]~30 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[2]~30_combout  = \datapath_0|program_counter_0|internal_register|internal_value [2] $ (VCC)
// \datapath_0|program_counter_0|internal_register|internal_value[2]~31  = CARRY(\datapath_0|program_counter_0|internal_register|internal_value [2])

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[2]~30_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[2]~31 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[2]~30 .lut_mask = 16'h55AA;
defparam \datapath_0|program_counter_0|internal_register|internal_value[2]~30 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[3]~32 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[3]~32_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [3] & (!\datapath_0|program_counter_0|internal_register|internal_value[2]~31 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [3] & ((\datapath_0|program_counter_0|internal_register|internal_value[2]~31 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[3]~33  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[2]~31 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [3]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[2]~31 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[3]~32_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[3]~33 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[3]~32 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[3]~32 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.AUIPC_1816 (
// Equation(s):
// \controller_0|decoded_cluster.AUIPC_1816~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.AUIPC_1816~combout ))) # (!\controller_0|Mux42~0_combout  & (!\controller_0|Mux33~0_combout ))))

	.dataa(\controller_0|Mux33~0_combout ),
	.datab(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.AUIPC_1816 .lut_mask = 16'hC500;
defparam \controller_0|decoded_cluster.AUIPC_1816 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.INVALID_1924 (
// Equation(s):
// \controller_0|decoded_cluster.INVALID_1924~combout  = ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.INVALID_1924~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux29~1_combout ))) # (!\controller_0|Equal0~0_combout )

	.dataa(\controller_0|Mux29~1_combout ),
	.datab(\controller_0|decoded_cluster.INVALID_1924~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.INVALID_1924~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.INVALID_1924 .lut_mask = 16'hCAFF;
defparam \controller_0|decoded_cluster.INVALID_1924 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.LUI_1810 (
// Equation(s):
// \controller_0|decoded_cluster.LUI_1810~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.LUI_1810~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux27~0_combout ))))

	.dataa(\controller_0|Mux27~0_combout ),
	.datab(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.LUI_1810~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.LUI_1810 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.LUI_1810 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.OP_1834 (
// Equation(s):
// \controller_0|decoded_cluster.OP_1834~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.OP_1834~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux26~1_combout ))))

	.dataa(\controller_0|Mux26~1_combout ),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.OP_1834~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.OP_1834 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.OP_1834 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector31~0 (
// Equation(s):
// \controller_0|Selector31~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & (!\controller_0|decoded_cluster.INVALID_1924~combout  & (!\controller_0|decoded_cluster.LUI_1810~combout  & 
// !\controller_0|decoded_cluster.OP_1834~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\controller_0|decoded_cluster.INVALID_1924~combout ),
	.datac(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datad(\controller_0|decoded_cluster.OP_1834~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector31~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector31~0 .lut_mask = 16'h0002;
defparam \controller_0|Selector31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector31~1 (
// Equation(s):
// \controller_0|Selector31~1_combout  = (\controller_0|decoded_cluster.STORE_1912~combout  & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10])) # (!\controller_0|decoded_cluster.STORE_1912~combout  & 
// (((!\controller_0|decoded_cluster.AUIPC_1816~combout  & \controller_0|Selector31~0_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datad(\controller_0|Selector31~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector31~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector31~1 .lut_mask = 16'h8B88;
defparam \controller_0|Selector31~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.BRANCH_1900 (
// Equation(s):
// \controller_0|decoded_cluster.BRANCH_1900~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.BRANCH_1900~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux24~1_combout ))))

	.dataa(\controller_0|Mux24~1_combout ),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.BRANCH_1900 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.BRANCH_1900 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector31~2 (
// Equation(s):
// \controller_0|Selector31~2_combout  = (\controller_0|decoded_cluster.BRANCH_1900~combout  & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8])) # (!\controller_0|decoded_cluster.BRANCH_1900~combout  & ((\controller_0|Selector31~1_combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8]),
	.datab(\controller_0|Selector31~1_combout ),
	.datac(gnd),
	.datad(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector31~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector31~2 .lut_mask = 16'hAACC;
defparam \controller_0|Selector31~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.OP_IMM_1840 (
// Equation(s):
// \controller_0|decoded_cluster.OP_IMM_1840~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.OP_IMM_1840~combout ))) # (!\controller_0|Mux42~0_combout  & (!\controller_0|Mux32~0_combout ))))

	.dataa(\controller_0|Mux32~0_combout ),
	.datab(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.OP_IMM_1840 .lut_mask = 16'hC500;
defparam \controller_0|decoded_cluster.OP_IMM_1840 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.LOAD_1918 (
// Equation(s):
// \controller_0|decoded_cluster.LOAD_1918~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.LOAD_1918~combout ))) # (!\controller_0|Mux42~0_combout  & (!\controller_0|Mux30~0_combout ))))

	.dataa(\controller_0|Mux30~0_combout ),
	.datab(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.LOAD_1918 .lut_mask = 16'hC500;
defparam \controller_0|decoded_cluster.LOAD_1918 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|WideNor1~2 (
// Equation(s):
// \controller_0|WideNor1~2_combout  = (!\controller_0|decoded_cluster.JAL_1846~combout  & (!\controller_0|decoded_cluster.LUI_1810~combout  & (!\controller_0|decoded_cluster.AUIPC_1816~combout  & !\controller_0|decoded_cluster.JALR_1876~combout )))

	.dataa(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datab(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datac(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datad(\controller_0|decoded_cluster.JALR_1876~combout ),
	.cin(gnd),
	.combout(\controller_0|WideNor1~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|WideNor1~2 .lut_mask = 16'h0001;
defparam \controller_0|WideNor1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|WideNor1~3 (
// Equation(s):
// \controller_0|WideNor1~3_combout  = (!\controller_0|decoded_cluster.OP_1834~combout  & (!\controller_0|decoded_cluster.OP_IMM_1840~combout  & (!\controller_0|decoded_cluster.LOAD_1918~combout  & \controller_0|WideNor1~2_combout )))

	.dataa(\controller_0|decoded_cluster.OP_1834~combout ),
	.datab(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datac(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.datad(\controller_0|WideNor1~2_combout ),
	.cin(gnd),
	.combout(\controller_0|WideNor1~3_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|WideNor1~3 .lut_mask = 16'h0100;
defparam \controller_0|WideNor1~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|WideNor1 (
// Equation(s):
// \controller_0|WideNor1~combout  = (\controller_0|decoded_cluster.BRANCH_1900~combout ) # ((\controller_0|decoded_cluster.STORE_1912~combout ) # ((\controller_0|decoded_cluster.INVALID_1924~combout ) # (!\controller_0|WideNor1~3_combout )))

	.dataa(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\controller_0|decoded_cluster.INVALID_1924~combout ),
	.datad(\controller_0|WideNor1~3_combout ),
	.cin(gnd),
	.combout(\controller_0|WideNor1~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|WideNor1 .lut_mask = 16'hFEFF;
defparam \controller_0|WideNor1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[3] (
// Equation(s):
// \controller_0|internal_immediate [3] = (\controller_0|WideNor1~combout  & (\controller_0|Selector31~2_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [3])))

	.dataa(gnd),
	.datab(\controller_0|Selector31~2_combout ),
	.datac(\controller_0|internal_immediate [3]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [3]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[3] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [3]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[4]~34 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[4]~34_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [4] & (\datapath_0|program_counter_0|internal_register|internal_value[3]~33  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [4] & (!\datapath_0|program_counter_0|internal_register|internal_value[3]~33  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[4]~35  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [4] & !\datapath_0|program_counter_0|internal_register|internal_value[3]~33 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[3]~33 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[4]~34_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[4]~35 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[4]~34 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[4]~34 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[5]~36 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[5]~36_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [5] & (!\datapath_0|program_counter_0|internal_register|internal_value[4]~35 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [5] & ((\datapath_0|program_counter_0|internal_register|internal_value[4]~35 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[5]~37  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[4]~35 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [5]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[4]~35 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[5]~36_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[5]~37 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[5]~36 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[5]~36 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector32~1 (
// Equation(s):
// \controller_0|Selector32~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10] & \controller_0|decoded_cluster.BRANCH_1900~combout )

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector32~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector32~1 .lut_mask = 16'h8888;
defparam \controller_0|Selector32~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[5] (
// Equation(s):
// \controller_0|internal_immediate [5] = (\controller_0|WideNor1~combout  & (\controller_0|Selector32~1_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [5])))

	.dataa(gnd),
	.datab(\controller_0|Selector32~1_combout ),
	.datac(\controller_0|internal_immediate [5]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [5]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[5] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [5]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector32~0 (
// Equation(s):
// \controller_0|Selector32~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10] & ((\controller_0|decoded_cluster.BRANCH_1900~combout ) # (\controller_0|decoded_cluster.STORE_1912~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector32~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector32~0 .lut_mask = 16'hA8A8;
defparam \controller_0|Selector32~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[4] (
// Equation(s):
// \controller_0|internal_immediate [4] = (\controller_0|WideNor1~combout  & (\controller_0|Selector32~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [4])))

	.dataa(gnd),
	.datab(\controller_0|Selector32~0_combout ),
	.datac(\controller_0|internal_immediate [4]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [4]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[4] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[4] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~6 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~6_combout  = (\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3] & (\datapath_0|JTU_0|internal_adder|Add0~5  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3] & (!\datapath_0|JTU_0|internal_adder|Add0~5 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~5 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3] & ((\datapath_0|JTU_0|internal_adder|Add0~5 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~7  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3] & !\datapath_0|JTU_0|internal_adder|Add0~5 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~5 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[3]~3_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~5 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~6_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~7 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~6 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~6 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~8 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~8_combout  = ((\datapath_0|JTU_0|internal_mux|output_0[4]~4_combout  $ (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4] $ (!\datapath_0|JTU_0|internal_adder|Add0~7 )))) # (GND)
// \datapath_0|JTU_0|internal_adder|Add0~9  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[4]~4_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]) # (!\datapath_0|JTU_0|internal_adder|Add0~7 ))) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[4]~4_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4] & !\datapath_0|JTU_0|internal_adder|Add0~7 )))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[4]~4_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~7 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~8_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~9 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~8 .lut_mask = 16'h698E;
defparam \datapath_0|JTU_0|internal_adder|Add0~8 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~10 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~10_combout  = (\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5] & (\datapath_0|JTU_0|internal_adder|Add0~9  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5] & (!\datapath_0|JTU_0|internal_adder|Add0~9 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~9 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5] & ((\datapath_0|JTU_0|internal_adder|Add0~9 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~11  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5] & !\datapath_0|JTU_0|internal_adder|Add0~9 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~9 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[5]~5_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~9 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~10_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~11 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~10 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~10 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_io_ibuf \reset~input (
	.i(reset),
	.ibar(gnd),
	.o(\reset~input_o ));
// synopsys translate_off
defparam \reset~input .bus_hold = "false";
defparam \reset~input .simulate_z_as = "z";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector27~0 (
// Equation(s):
// \controller_0|Selector27~0_combout  = (!\controller_0|decoded_cluster.JALR_1876~combout  & (!\controller_0|decoded_cluster.OP_IMM_1840~combout  & !\controller_0|decoded_cluster.LOAD_1918~combout ))

	.dataa(gnd),
	.datab(\controller_0|decoded_cluster.JALR_1876~combout ),
	.datac(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datad(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector27~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector27~0 .lut_mask = 16'h0003;
defparam \controller_0|Selector27~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|WideNor1~4 (
// Equation(s):
// \controller_0|WideNor1~4_combout  = (!\controller_0|decoded_cluster.BRANCH_1900~combout  & !\controller_0|decoded_cluster.STORE_1912~combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datad(\controller_0|decoded_cluster.STORE_1912~combout ),
	.cin(gnd),
	.combout(\controller_0|WideNor1~4_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|WideNor1~4 .lut_mask = 16'h000F;
defparam \controller_0|WideNor1~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector93~0 (
// Equation(s):
// \controller_0|Selector93~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16] & ((\controller_0|decoded_cluster.OP_1834~combout ) # ((!\controller_0|WideNor1~4_combout ) # (!\controller_0|Selector27~0_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16]),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|Selector27~0_combout ),
	.datad(\controller_0|WideNor1~4_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector93~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector93~0 .lut_mask = 16'h8AAA;
defparam \controller_0|Selector93~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_read_address_0[1] (
// Equation(s):
// \controller_0|internal_reg_file_read_address_0 [1] = (\controller_0|WideNor1~combout  & (\controller_0|Selector93~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_read_address_0 [1])))

	.dataa(gnd),
	.datab(\controller_0|Selector93~0_combout ),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_read_address_0 [1]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_read_address_0[1] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_read_address_0[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_read_address_0 [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[4]~34_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~8_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0_combout  = (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & ((\datapath_0|program_counter_0|internal_register|internal_value [2] & 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [3]))) # (!\datapath_0|program_counter_0|internal_register|internal_value [2] & ((\datapath_0|program_counter_0|internal_register|internal_value [4]) # 
// (\datapath_0|program_counter_0|internal_register|internal_value [3])))))

	.dataa(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0 .lut_mask = 16'h0AA8;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux23~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector79~2 (
// Equation(s):
// \controller_0|Selector79~2_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8] & ((\controller_0|decoded_cluster.BRANCH_1900~combout ) # ((\controller_0|decoded_cluster.STORE_1912~combout ) # (!\controller_0|WideNor1~3_combout ))))

	.dataa(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8]),
	.datad(\controller_0|WideNor1~3_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector79~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector79~2 .lut_mask = 16'hE0F0;
defparam \controller_0|Selector79~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_write_address[1] (
// Equation(s):
// \controller_0|internal_reg_file_write_address [1] = (\controller_0|WideNor1~combout  & (\controller_0|Selector79~2_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_write_address [1])))

	.dataa(gnd),
	.datab(\controller_0|Selector79~2_combout ),
	.datac(\controller_0|internal_reg_file_write_address [1]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_write_address [1]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_write_address[1] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_write_address[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write_address [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0_combout  = (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & ((\datapath_0|program_counter_0|internal_register|internal_value [4] & 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [2]))) # (!\datapath_0|program_counter_0|internal_register|internal_value [4] & (\datapath_0|program_counter_0|internal_register|internal_value [3]))))

	.dataa(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0 .lut_mask = 16'h08A8;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux24~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector78~2 (
// Equation(s):
// \controller_0|Selector78~2_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & ((\controller_0|decoded_cluster.BRANCH_1900~combout ) # ((\controller_0|decoded_cluster.STORE_1912~combout ) # (!\controller_0|WideNor1~3_combout ))))

	.dataa(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.datad(\controller_0|WideNor1~3_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector78~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector78~2 .lut_mask = 16'hE0F0;
defparam \controller_0|Selector78~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_write_address[0] (
// Equation(s):
// \controller_0|internal_reg_file_write_address [0] = (\controller_0|WideNor1~combout  & (\controller_0|Selector78~2_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_write_address [0])))

	.dataa(gnd),
	.datab(\controller_0|Selector78~2_combout ),
	.datac(\controller_0|internal_reg_file_write_address [0]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_write_address [0]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_write_address[0] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_write_address[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write_address [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_0~0 (
// Equation(s):
// \datapath_0|FU_0|forward_0~0_combout  = (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & 
// (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1] $ (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))) # (!\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0] & 
// (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0])))

	.dataa(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]),
	.datab(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_0~0 .lut_mask = 16'h8240;
defparam \datapath_0|FU_0|forward_0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_mux0_sel[0] (
// Equation(s):
// \controller_0|internal_mux0_sel [0] = (\controller_0|WideNor1~combout  & (\controller_0|decoded_cluster.LOAD_1918~combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_mux0_sel [0])))

	.dataa(gnd),
	.datab(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.datac(\controller_0|internal_mux0_sel [0]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_mux0_sel [0]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_mux0_sel[0] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_mux0_sel[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_mux0_sel [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_mux0_sel [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|mux0_sel_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_0~1 (
// Equation(s):
// \datapath_0|FU_0|forward_0~1_combout  = (\datapath_0|register_file_0|internal_reg_load[3]~0_combout  & (\datapath_0|FU_0|forward_0~0_combout  & (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value 
// [1])))

	.dataa(\datapath_0|register_file_0|internal_reg_load[3]~0_combout ),
	.datab(\datapath_0|FU_0|forward_0~0_combout ),
	.datac(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_0~1 .lut_mask = 16'h0008;
defparam \datapath_0|FU_0|forward_0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector82~2 (
// Equation(s):
// \controller_0|Selector82~2_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10] & ((\controller_0|decoded_cluster.BRANCH_1900~combout ) # ((\controller_0|decoded_cluster.STORE_1912~combout ) # (!\controller_0|WideNor1~3_combout ))))

	.dataa(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.datad(\controller_0|WideNor1~3_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector82~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector82~2 .lut_mask = 16'hE0F0;
defparam \controller_0|Selector82~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_write_address[4] (
// Equation(s):
// \controller_0|internal_reg_file_write_address [4] = (\controller_0|WideNor1~combout  & (\controller_0|Selector82~2_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_write_address [4])))

	.dataa(gnd),
	.datab(\controller_0|Selector82~2_combout ),
	.datac(\controller_0|internal_reg_file_write_address [4]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_write_address [4]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_write_address[4] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_write_address[4] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write_address [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write_address [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write_address [4]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_address_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal2~1 (
// Equation(s):
// \datapath_0|FU_0|Equal2~1_combout  = (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4] & !\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]))

	.dataa(gnd),
	.datab(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal2~1 .lut_mask = 16'h0003;
defparam \datapath_0|FU_0|Equal2~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector92~0 (
// Equation(s):
// \controller_0|Selector92~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15] & ((\controller_0|decoded_cluster.OP_1834~combout ) # ((!\controller_0|WideNor1~4_combout ) # (!\controller_0|Selector27~0_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15]),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|Selector27~0_combout ),
	.datad(\controller_0|WideNor1~4_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector92~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector92~0 .lut_mask = 16'h8AAA;
defparam \controller_0|Selector92~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_read_address_0[0] (
// Equation(s):
// \controller_0|internal_reg_file_read_address_0 [0] = (\controller_0|WideNor1~combout  & (\controller_0|Selector92~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(gnd),
	.datab(\controller_0|Selector92~0_combout ),
	.datac(\controller_0|internal_reg_file_read_address_0 [0]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_read_address_0 [0]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_read_address_0[0] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_read_address_0[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_read_address_0 [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_0~2 (
// Equation(s):
// \datapath_0|FU_0|forward_0~2_combout  = (\datapath_0|FU_0|Equal2~0_combout  & (\datapath_0|FU_0|Equal2~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]) # 
// (\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]))))

	.dataa(\datapath_0|FU_0|Equal2~0_combout ),
	.datab(\datapath_0|FU_0|Equal2~1_combout ),
	.datac(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [0]),
	.datad(\datapath_0|ID_EX_PLR|register_file_read_address_0_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_0~2 .lut_mask = 16'h8880;
defparam \datapath_0|FU_0|forward_0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_write (
// Equation(s):
// \controller_0|internal_reg_file_write~combout  = (\controller_0|WideNor1~combout  & (!\controller_0|WideNor1~3_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_write~combout )))

	.dataa(gnd),
	.datab(\controller_0|WideNor1~3_combout ),
	.datac(\controller_0|internal_reg_file_write~combout ),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_write~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_write .lut_mask = 16'h33F0;
defparam \controller_0|internal_reg_file_write .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_write~combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|reg_file_write_reg|reg_out~q ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~0 (
// Equation(s):
// \datapath_0|FU_0|forward_1~0_combout  = (\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q  & !\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.datac(gnd),
	.datad(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~0 .lut_mask = 16'h0088;
defparam \datapath_0|FU_0|forward_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_0_control[0]~1 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_0_control[0]~1_combout  = (\datapath_0|FU_0|forward_0~2_combout  & ((\datapath_0|FU_0|forward_1~1_combout ) # ((\datapath_0|FU_0|forward_0~1_combout  & !\datapath_0|FU_0|forward_1~0_combout )))) # 
// (!\datapath_0|FU_0|forward_0~2_combout  & (((\datapath_0|FU_0|forward_0~1_combout ))))

	.dataa(\datapath_0|FU_0|forward_1~1_combout ),
	.datab(\datapath_0|FU_0|forward_0~1_combout ),
	.datac(\datapath_0|FU_0|forward_0~2_combout ),
	.datad(\datapath_0|FU_0|forward_1~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_0_control[0]~1 .lut_mask = 16'hACEC;
defparam \datapath_0|FU_0|forward_mux_0_control[0]~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~1 (
// Equation(s):
// \datapath_0|FU_0|forward_1~1_combout  = (\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q  & (!\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~1 .lut_mask = 16'h000A;
defparam \datapath_0|FU_0|forward_1~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_0_control[1]~0 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_0_control[1]~0_combout  = (\datapath_0|FU_0|forward_0~2_combout  & (!\datapath_0|FU_0|forward_1~1_combout  & ((\datapath_0|FU_0|forward_0~1_combout ) # (\datapath_0|FU_0|forward_1~0_combout )))) # 
// (!\datapath_0|FU_0|forward_0~2_combout  & (\datapath_0|FU_0|forward_0~1_combout ))

	.dataa(\datapath_0|FU_0|forward_0~1_combout ),
	.datab(\datapath_0|FU_0|forward_1~0_combout ),
	.datac(\datapath_0|FU_0|forward_0~2_combout ),
	.datad(\datapath_0|FU_0|forward_1~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_0_control[1]~0 .lut_mask = 16'h0AEA;
defparam \datapath_0|FU_0|forward_mux_0_control[1]~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~0 (
// Equation(s):
// \datapath_0|Add1~0_combout  = \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [2] $ (VCC)
// \datapath_0|Add1~1  = CARRY(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [2])

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [2]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\datapath_0|Add1~0_combout ),
	.cout(\datapath_0|Add1~1 ));
// synopsys translate_off
defparam \datapath_0|Add1~0 .lut_mask = 16'h55AA;
defparam \datapath_0|Add1~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~2 (
// Equation(s):
// \datapath_0|Add1~2_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [3] & (!\datapath_0|Add1~1 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [3] & ((\datapath_0|Add1~1 ) # (GND)))
// \datapath_0|Add1~3  = CARRY((!\datapath_0|Add1~1 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [3]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [3]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~1 ),
	.combout(\datapath_0|Add1~2_combout ),
	.cout(\datapath_0|Add1~3 ));
// synopsys translate_off
defparam \datapath_0|Add1~2 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~2 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~4 (
// Equation(s):
// \datapath_0|Add1~4_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [4] & (\datapath_0|Add1~3  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [4] & (!\datapath_0|Add1~3  & VCC))
// \datapath_0|Add1~5  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [4] & !\datapath_0|Add1~3 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~3 ),
	.combout(\datapath_0|Add1~4_combout ),
	.cout(\datapath_0|Add1~5 ));
// synopsys translate_off
defparam \datapath_0|Add1~4 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~4 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux27~1 (
// Equation(s):
// \datapath_0|mux_0|Mux27~1_combout  = (\datapath_0|mux_0|Mux27~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~4_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux27~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~4_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux27~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[2]~5 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[2]~5_combout  = (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1] & 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0])))

	.dataa(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[2]~5 .lut_mask = 16'h0008;
defparam \datapath_0|register_file_0|internal_reg_load[2]~5 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux27~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux27~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux27~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [4] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux27~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [4]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux27~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux27~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux27~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux27~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux27~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux27~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux27~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]))) # (!\datapath_0|forward_mux_0|Mux27~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [4])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux27~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [4]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux27~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux27~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux31~3 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux31~3_combout  = (\datapath_0|forward_mux_0|Mux31~2_combout  & (!\datapath_0|FU_0|forward_0~1_combout  & ((!\datapath_0|FU_0|forward_0~2_combout ) # (!\datapath_0|FU_0|forward_1~0_combout ))))

	.dataa(\datapath_0|forward_mux_0|Mux31~2_combout ),
	.datab(\datapath_0|FU_0|forward_1~0_combout ),
	.datac(\datapath_0|FU_0|forward_0~2_combout ),
	.datad(\datapath_0|FU_0|forward_0~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux31~3 .lut_mask = 16'h002A;
defparam \datapath_0|forward_mux_0|Mux31~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux27~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux27~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux27~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4]),
	.datab(\datapath_0|forward_mux_0|Mux27~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux27~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux27~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux27~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux29~1 (
// Equation(s):
// \datapath_0|mux_0|Mux29~1_combout  = (\datapath_0|mux_0|Mux29~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~0_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux29~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux29~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux29~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux29~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux29~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [2] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux29~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [2]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux29~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux29~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux29~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux29~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux29~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux29~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux29~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]))) # (!\datapath_0|forward_mux_0|Mux29~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [2])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux29~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [2]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux29~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux29~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux29~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux29~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux29~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2]),
	.datab(\datapath_0|forward_mux_0|Mux29~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux29~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux29~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux29~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux31~1 (
// Equation(s):
// \datapath_0|mux_0|Mux31~1_combout  = (\datapath_0|mux_0|Mux31~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [0] & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value 
// [0])))

	.dataa(\datapath_0|mux_0|Mux31~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux31~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux31~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux31~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux31~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [0] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux31~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [0]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux31~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux31~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux31~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux31~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux31~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux31~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux31~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]))) # (!\datapath_0|forward_mux_0|Mux31~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [0])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux31~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [0]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux31~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux31~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux31~4 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux31~4_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux31~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0]),
	.datab(\datapath_0|forward_mux_0|Mux31~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux31~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux31~4 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux31~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~33 (
// Equation(s):
// \datapath_0|ALU_0|Add0~33_cout  = CARRY(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q )

	.dataa(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(),
	.cout(\datapath_0|ALU_0|Add0~33_cout ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~33 .lut_mask = 16'h00AA;
defparam \datapath_0|ALU_0|Add0~33 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~34 (
// Equation(s):
// \datapath_0|ALU_0|Add0~34_combout  = (\datapath_0|ALU_0|Add0~31_combout  & ((\datapath_0|forward_mux_0|Mux31~4_combout  & (\datapath_0|ALU_0|Add0~33_cout  & VCC)) # (!\datapath_0|forward_mux_0|Mux31~4_combout  & (!\datapath_0|ALU_0|Add0~33_cout )))) # 
// (!\datapath_0|ALU_0|Add0~31_combout  & ((\datapath_0|forward_mux_0|Mux31~4_combout  & (!\datapath_0|ALU_0|Add0~33_cout )) # (!\datapath_0|forward_mux_0|Mux31~4_combout  & ((\datapath_0|ALU_0|Add0~33_cout ) # (GND)))))
// \datapath_0|ALU_0|Add0~35  = CARRY((\datapath_0|ALU_0|Add0~31_combout  & (!\datapath_0|forward_mux_0|Mux31~4_combout  & !\datapath_0|ALU_0|Add0~33_cout )) # (!\datapath_0|ALU_0|Add0~31_combout  & ((!\datapath_0|ALU_0|Add0~33_cout ) # 
// (!\datapath_0|forward_mux_0|Mux31~4_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~31_combout ),
	.datab(\datapath_0|forward_mux_0|Mux31~4_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~33_cout ),
	.combout(\datapath_0|ALU_0|Add0~34_combout ),
	.cout(\datapath_0|ALU_0|Add0~35 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~34 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~34 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_ALU_branch (
// Equation(s):
// \controller_0|internal_ALU_branch~combout  = (\controller_0|WideNor1~combout  & (\controller_0|decoded_cluster.BRANCH_1900~combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_ALU_branch~combout )))

	.dataa(gnd),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(\controller_0|internal_ALU_branch~combout ),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_ALU_branch~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_ALU_branch .lut_mask = 16'hCCF0;
defparam \controller_0|internal_ALU_branch .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_ALU_branch~combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[0] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [0] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [0]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~34_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~34_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [0]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[0] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~36 (
// Equation(s):
// \datapath_0|ALU_0|Add0~36_combout  = ((\datapath_0|ALU_0|Add0~30_combout  $ (\datapath_0|forward_mux_0|Mux30~2_combout  $ (!\datapath_0|ALU_0|Add0~35 )))) # (GND)
// \datapath_0|ALU_0|Add0~37  = CARRY((\datapath_0|ALU_0|Add0~30_combout  & ((\datapath_0|forward_mux_0|Mux30~2_combout ) # (!\datapath_0|ALU_0|Add0~35 ))) # (!\datapath_0|ALU_0|Add0~30_combout  & (\datapath_0|forward_mux_0|Mux30~2_combout  & 
// !\datapath_0|ALU_0|Add0~35 )))

	.dataa(\datapath_0|ALU_0|Add0~30_combout ),
	.datab(\datapath_0|forward_mux_0|Mux30~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~35 ),
	.combout(\datapath_0|ALU_0|Add0~36_combout ),
	.cout(\datapath_0|ALU_0|Add0~37 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~36 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~36 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[1] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [1] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [1]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~36_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~36_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [1]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[1] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[1]~1 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[1]~1_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [1] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [1]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[1]~1 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_datamem_write (
// Equation(s):
// \controller_0|internal_datamem_write~combout  = (\controller_0|WideNor1~combout  & (\controller_0|decoded_cluster.STORE_1912~combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_datamem_write~combout )))

	.dataa(gnd),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\controller_0|internal_datamem_write~combout ),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_datamem_write~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_datamem_write .lut_mask = 16'hCCF0;
defparam \controller_0|internal_datamem_write .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|datamem_write_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_datamem_write~combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|datamem_write_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|datamem_write_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|datamem_write_reg|reg_out .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|datamem_write_reg|reg_out~q ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[1] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [1] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[1]~1_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [1])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[1]~1_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[1] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[1] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~38 (
// Equation(s):
// \datapath_0|ALU_0|Add0~38_combout  = (\datapath_0|ALU_0|Add0~29_combout  & ((\datapath_0|forward_mux_0|Mux29~2_combout  & (\datapath_0|ALU_0|Add0~37  & VCC)) # (!\datapath_0|forward_mux_0|Mux29~2_combout  & (!\datapath_0|ALU_0|Add0~37 )))) # 
// (!\datapath_0|ALU_0|Add0~29_combout  & ((\datapath_0|forward_mux_0|Mux29~2_combout  & (!\datapath_0|ALU_0|Add0~37 )) # (!\datapath_0|forward_mux_0|Mux29~2_combout  & ((\datapath_0|ALU_0|Add0~37 ) # (GND)))))
// \datapath_0|ALU_0|Add0~39  = CARRY((\datapath_0|ALU_0|Add0~29_combout  & (!\datapath_0|forward_mux_0|Mux29~2_combout  & !\datapath_0|ALU_0|Add0~37 )) # (!\datapath_0|ALU_0|Add0~29_combout  & ((!\datapath_0|ALU_0|Add0~37 ) # 
// (!\datapath_0|forward_mux_0|Mux29~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~29_combout ),
	.datab(\datapath_0|forward_mux_0|Mux29~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~37 ),
	.combout(\datapath_0|ALU_0|Add0~38_combout ),
	.cout(\datapath_0|ALU_0|Add0~39 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~38 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~38 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~40 (
// Equation(s):
// \datapath_0|ALU_0|Add0~40_combout  = ((\datapath_0|ALU_0|Add0~28_combout  $ (\datapath_0|forward_mux_0|Mux28~2_combout  $ (!\datapath_0|ALU_0|Add0~39 )))) # (GND)
// \datapath_0|ALU_0|Add0~41  = CARRY((\datapath_0|ALU_0|Add0~28_combout  & ((\datapath_0|forward_mux_0|Mux28~2_combout ) # (!\datapath_0|ALU_0|Add0~39 ))) # (!\datapath_0|ALU_0|Add0~28_combout  & (\datapath_0|forward_mux_0|Mux28~2_combout  & 
// !\datapath_0|ALU_0|Add0~39 )))

	.dataa(\datapath_0|ALU_0|Add0~28_combout ),
	.datab(\datapath_0|forward_mux_0|Mux28~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~39 ),
	.combout(\datapath_0|ALU_0|Add0~40_combout ),
	.cout(\datapath_0|ALU_0|Add0~41 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~40 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~40 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[3] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [3] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [3]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~40_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~40_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [3]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[3] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[5]~5 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[5]~5_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [5] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [5]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[5]~5 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[5] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [5] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[5]~5_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [5])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[5]~5_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[5] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~9 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~9_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~9 .lut_mask = 16'h0100;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~9 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~6 (
// Equation(s):
// \datapath_0|Add1~6_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [5] & (!\datapath_0|Add1~5 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [5] & ((\datapath_0|Add1~5 ) # (GND)))
// \datapath_0|Add1~7  = CARRY((!\datapath_0|Add1~5 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [5]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [5]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~5 ),
	.combout(\datapath_0|Add1~6_combout ),
	.cout(\datapath_0|Add1~7 ));
// synopsys translate_off
defparam \datapath_0|Add1~6 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~6 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~8 (
// Equation(s):
// \datapath_0|Add1~8_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [6] & (\datapath_0|Add1~7  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [6] & (!\datapath_0|Add1~7  & VCC))
// \datapath_0|Add1~9  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [6] & !\datapath_0|Add1~7 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [6]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~7 ),
	.combout(\datapath_0|Add1~8_combout ),
	.cout(\datapath_0|Add1~9 ));
// synopsys translate_off
defparam \datapath_0|Add1~8 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~8 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux25~1 (
// Equation(s):
// \datapath_0|mux_0|Mux25~1_combout  = (\datapath_0|mux_0|Mux25~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~8_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux25~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~8_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux25~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux25~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux25~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux25~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux25~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux25~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [6] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux25~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [6]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux25~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux25~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux25~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux25~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux25~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux25~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux25~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux25~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux25~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]))) # (!\datapath_0|forward_mux_0|Mux25~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [6])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux25~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [6]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux25~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux25~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux25~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux25~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux25~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux25~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux25~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6]),
	.datab(\datapath_0|forward_mux_0|Mux25~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux25~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux25~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux25~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~42 (
// Equation(s):
// \datapath_0|ALU_0|Add0~42_combout  = (\datapath_0|ALU_0|Add0~27_combout  & ((\datapath_0|forward_mux_0|Mux27~2_combout  & (\datapath_0|ALU_0|Add0~41  & VCC)) # (!\datapath_0|forward_mux_0|Mux27~2_combout  & (!\datapath_0|ALU_0|Add0~41 )))) # 
// (!\datapath_0|ALU_0|Add0~27_combout  & ((\datapath_0|forward_mux_0|Mux27~2_combout  & (!\datapath_0|ALU_0|Add0~41 )) # (!\datapath_0|forward_mux_0|Mux27~2_combout  & ((\datapath_0|ALU_0|Add0~41 ) # (GND)))))
// \datapath_0|ALU_0|Add0~43  = CARRY((\datapath_0|ALU_0|Add0~27_combout  & (!\datapath_0|forward_mux_0|Mux27~2_combout  & !\datapath_0|ALU_0|Add0~41 )) # (!\datapath_0|ALU_0|Add0~27_combout  & ((!\datapath_0|ALU_0|Add0~41 ) # 
// (!\datapath_0|forward_mux_0|Mux27~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~27_combout ),
	.datab(\datapath_0|forward_mux_0|Mux27~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~41 ),
	.combout(\datapath_0|ALU_0|Add0~42_combout ),
	.cout(\datapath_0|ALU_0|Add0~43 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~42 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~42 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~44 (
// Equation(s):
// \datapath_0|ALU_0|Add0~44_combout  = ((\datapath_0|ALU_0|Add0~26_combout  $ (\datapath_0|forward_mux_0|Mux26~2_combout  $ (!\datapath_0|ALU_0|Add0~43 )))) # (GND)
// \datapath_0|ALU_0|Add0~45  = CARRY((\datapath_0|ALU_0|Add0~26_combout  & ((\datapath_0|forward_mux_0|Mux26~2_combout ) # (!\datapath_0|ALU_0|Add0~43 ))) # (!\datapath_0|ALU_0|Add0~26_combout  & (\datapath_0|forward_mux_0|Mux26~2_combout  & 
// !\datapath_0|ALU_0|Add0~43 )))

	.dataa(\datapath_0|ALU_0|Add0~26_combout ),
	.datab(\datapath_0|forward_mux_0|Mux26~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~43 ),
	.combout(\datapath_0|ALU_0|Add0~44_combout ),
	.cout(\datapath_0|ALU_0|Add0~45 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~44 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~44 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~46 (
// Equation(s):
// \datapath_0|ALU_0|Add0~46_combout  = (\datapath_0|ALU_0|Add0~25_combout  & ((\datapath_0|forward_mux_0|Mux25~2_combout  & (\datapath_0|ALU_0|Add0~45  & VCC)) # (!\datapath_0|forward_mux_0|Mux25~2_combout  & (!\datapath_0|ALU_0|Add0~45 )))) # 
// (!\datapath_0|ALU_0|Add0~25_combout  & ((\datapath_0|forward_mux_0|Mux25~2_combout  & (!\datapath_0|ALU_0|Add0~45 )) # (!\datapath_0|forward_mux_0|Mux25~2_combout  & ((\datapath_0|ALU_0|Add0~45 ) # (GND)))))
// \datapath_0|ALU_0|Add0~47  = CARRY((\datapath_0|ALU_0|Add0~25_combout  & (!\datapath_0|forward_mux_0|Mux25~2_combout  & !\datapath_0|ALU_0|Add0~45 )) # (!\datapath_0|ALU_0|Add0~25_combout  & ((!\datapath_0|ALU_0|Add0~45 ) # 
// (!\datapath_0|forward_mux_0|Mux25~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~25_combout ),
	.datab(\datapath_0|forward_mux_0|Mux25~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~45 ),
	.combout(\datapath_0|ALU_0|Add0~46_combout ),
	.cout(\datapath_0|ALU_0|Add0~47 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~46 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~46 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[6] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [6] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [6]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~46_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~46_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [6]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[6] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[6] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|Equal0~0 (
// Equation(s):
// \datapath_0|datamem_module_0|Equal0~0_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]) # (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1])

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|Equal0~0 .lut_mask = 16'hEEEE;
defparam \datapath_0|datamem_module_0|Equal0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~9_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~9_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~117 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~117_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~117_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~117 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~117 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~12 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~12_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~12 .lut_mask = 16'h0800;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~12 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~12_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~12_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~118 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~118_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~117_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~117_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~117_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~117_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~118_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~118 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~118 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~2 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~2_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~2 .lut_mask = 16'h0004;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~2_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~2_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~10 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~10_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~10 .lut_mask = 16'h0001;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~10 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~10_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~10_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~119 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~119_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~119_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~119 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~119 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~14 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~14_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~14 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~14 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~14_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~14_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~120 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~120_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~119_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~119_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~119_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~119_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~120_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~120 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~120 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~121 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~121_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~118_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~120_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~118_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~120_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~121_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~121 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~121 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~7 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~7_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~7 .lut_mask = 16'h2000;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~7_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~7_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~11 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~11_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~11 .lut_mask = 16'h1000;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~11 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~11_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~11_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~122 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~122_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~122_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~122 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~122 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~15 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~15_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~15 .lut_mask = 16'h8000;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~15 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~15_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~15_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~123 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~123_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~122_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~122_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~122_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~122_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~123_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~123 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~123 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~124 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~124_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~121_combout  & ((\datapath_0|datamem_module_0|output_data~123_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~121_combout  & (\datapath_0|datamem_module_0|output_data~116_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~121_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~116_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~121_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~123_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~124_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~124 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~124 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~125 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~125_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~114_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~124_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~114_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~124_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~125_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~125 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~125 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[5] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [5] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [5]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~125_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~125_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [5]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[5] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[5] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux26~1 (
// Equation(s):
// \datapath_0|mux_0|Mux26~1_combout  = (\datapath_0|mux_0|Mux26~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~6_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux26~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~6_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux26~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux26~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux26~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux26~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [5] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux26~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [5]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux26~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux26~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux26~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [5])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [5]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux26~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux26~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux26~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux26~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]))) # (!\datapath_0|forward_mux_0|Mux26~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux26~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux26~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux26~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux26~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux26~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux26~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5]),
	.datab(\datapath_0|forward_mux_0|Mux26~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux26~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux26~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux26~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[5] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [5] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [5]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~44_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~44_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [5]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[5] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~1 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~1_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~1 .lut_mask = 16'h0400;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~1_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~1_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~33 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~33_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~33_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~33 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~33 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~34 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~34_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~33_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~33_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~33_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~33_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~34_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~34 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~34 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~35 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~35_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~35_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~35 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~35 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~36 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~36_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~35_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~35_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~35_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~35_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~36_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~36 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~36 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~37 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~37_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~34_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~36_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~34_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~36_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~37_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~37 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~37 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~38 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~38_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~38_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~38 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~38 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~39 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~39_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~38_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~38_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~38_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~38_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~39_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~39 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~39 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~40 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~40_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~37_combout  & ((\datapath_0|datamem_module_0|output_data~39_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~37_combout  & (\datapath_0|datamem_module_0|output_data~32_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~37_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~32_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~37_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~39_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~40_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~40 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~40 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~41 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~41_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~30_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~40_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~30_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~40_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~41_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~41 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~41 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[1] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [1] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [1]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~41_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~41_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [1]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[1] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[1] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~0 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~0_combout  = (\datapath_0|JTU_0|internal_mux|output_0[0]~0_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0] $ (VCC))) # (!\datapath_0|JTU_0|internal_mux|output_0[0]~0_combout  & 
// (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0] & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~1  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[0]~0_combout  & \datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[0]~0_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~0_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~1 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~0 .lut_mask = 16'h6688;
defparam \datapath_0|JTU_0|internal_adder|Add0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~2 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~2_combout  = (\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1] & (\datapath_0|JTU_0|internal_adder|Add0~1  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1] & (!\datapath_0|JTU_0|internal_adder|Add0~1 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~1 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1] & ((\datapath_0|JTU_0|internal_adder|Add0~1 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~3  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1] & !\datapath_0|JTU_0|internal_adder|Add0~1 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~1 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[1]~1_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~1 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~2_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~3 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~2 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~2 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|JTU_0|internal_adder|Add0~2_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|comb~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|IF_ID_PLR|instruction_address_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|instruction_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|instruction_address_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|instruction_address_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux30~1 (
// Equation(s):
// \datapath_0|mux_0|Mux30~1_combout  = (\datapath_0|mux_0|Mux30~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [1] & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value 
// [0])))

	.dataa(\datapath_0|mux_0|Mux30~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [1]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux30~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux30~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux30~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux30~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [1] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux30~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [1]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux30~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux30~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux30~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [1])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [1]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux30~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux30~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux30~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux30~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]))) # (!\datapath_0|forward_mux_0|Mux30~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux30~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux30~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux30~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux30~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux30~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux30~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1]),
	.datab(\datapath_0|forward_mux_0|Mux30~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux30~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux30~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux30~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[2] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [2] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [2]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~38_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~38_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [2]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[2] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[2] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[3]~3 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[3]~3_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [3]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[3]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[3]~3 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[3]~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[3] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [3] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[3]~3_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [3])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[3]~3_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[3] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~75 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~75_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~75_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~75 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~75 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~76 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~76_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~75_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~75_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~75_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~75_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~76_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~76 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~76 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~77 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~77_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~77_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~77 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~77 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~78 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~78_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~77_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~77_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~77_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~77_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~78_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~78 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~78 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~79 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~79_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~76_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~78_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~76_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~78_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~79_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~79 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~79 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~80 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~80_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~80_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~80 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~80 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~81 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~81_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~80_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~80_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~80_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~80_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~81_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~81 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~81 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~82 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~82_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~79_combout  & ((\datapath_0|datamem_module_0|output_data~81_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~79_combout  & (\datapath_0|datamem_module_0|output_data~74_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~79_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~74_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~79_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~81_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~82_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~82 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~82 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~83 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~83_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~72_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~82_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~72_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~82_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~83_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~83 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~83 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[3] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [3] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [3]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~83_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~83_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [3]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[3] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[3] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux28~1 (
// Equation(s):
// \datapath_0|mux_0|Mux28~1_combout  = (\datapath_0|mux_0|Mux28~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~2_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux28~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~2_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux28~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux28~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux28~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux28~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux28~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux28~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [3] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux28~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [3]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux28~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux28~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux28~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux28~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux28~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [3])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [3]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux28~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux28~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux28~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux28~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux28~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux28~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]))) # (!\datapath_0|forward_mux_0|Mux28~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux28~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux28~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux28~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux28~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux28~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux28~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux28~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux28~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3]),
	.datab(\datapath_0|forward_mux_0|Mux28~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux28~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux28~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux28~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[4] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [4] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [4]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~42_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~42_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [4]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[4] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[4] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~7 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~7_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [31] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [31]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~7 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[7] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [7] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~7_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [7])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~7_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[7] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[7] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~663 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~663_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~663_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~663 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~663 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~664 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~664_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~663_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~663_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~663_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~663_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~664_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~664 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~664 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~665 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~665_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~665_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~665 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~665 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~666 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~666_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~665_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~665_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~665_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~665_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~666_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~666 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~666 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~667 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~667_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~664_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~666_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~664_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~666_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~667_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~667 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~667 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~668 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~668_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~668_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~668 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~668 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~669 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~669_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~668_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~668_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~668_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~668_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~669_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~669 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~669 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~670 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~670_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~667_combout  & ((\datapath_0|datamem_module_0|output_data~669_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~667_combout  & (\datapath_0|datamem_module_0|output_data~662_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~667_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~662_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~667_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~669_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~670_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~670 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~670 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~671 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~671_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~660_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~670_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~660_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~670_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~671_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~671 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~671 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[31] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [31] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [31]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~671_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~671_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [31]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [31]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[31] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[31] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~10 (
// Equation(s):
// \datapath_0|Add1~10_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [7] & (!\datapath_0|Add1~9 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [7] & ((\datapath_0|Add1~9 ) # (GND)))
// \datapath_0|Add1~11  = CARRY((!\datapath_0|Add1~9 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [7]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [7]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~9 ),
	.combout(\datapath_0|Add1~10_combout ),
	.cout(\datapath_0|Add1~11 ));
// synopsys translate_off
defparam \datapath_0|Add1~10 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~10 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~12 (
// Equation(s):
// \datapath_0|Add1~12_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [8] & (\datapath_0|Add1~11  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [8] & (!\datapath_0|Add1~11  & VCC))
// \datapath_0|Add1~13  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [8] & !\datapath_0|Add1~11 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [8]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~11 ),
	.combout(\datapath_0|Add1~12_combout ),
	.cout(\datapath_0|Add1~13 ));
// synopsys translate_off
defparam \datapath_0|Add1~12 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~12 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~14 (
// Equation(s):
// \datapath_0|Add1~14_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [9] & (!\datapath_0|Add1~13 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [9] & ((\datapath_0|Add1~13 ) # (GND)))
// \datapath_0|Add1~15  = CARRY((!\datapath_0|Add1~13 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [9]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [9]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~13 ),
	.combout(\datapath_0|Add1~14_combout ),
	.cout(\datapath_0|Add1~15 ));
// synopsys translate_off
defparam \datapath_0|Add1~14 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~14 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~16 (
// Equation(s):
// \datapath_0|Add1~16_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [10] & (\datapath_0|Add1~15  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [10] & (!\datapath_0|Add1~15  & VCC))
// \datapath_0|Add1~17  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [10] & !\datapath_0|Add1~15 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [10]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~15 ),
	.combout(\datapath_0|Add1~16_combout ),
	.cout(\datapath_0|Add1~17 ));
// synopsys translate_off
defparam \datapath_0|Add1~16 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~16 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~18 (
// Equation(s):
// \datapath_0|Add1~18_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [11] & (!\datapath_0|Add1~17 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [11] & ((\datapath_0|Add1~17 ) # (GND)))
// \datapath_0|Add1~19  = CARRY((!\datapath_0|Add1~17 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [11]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [11]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~17 ),
	.combout(\datapath_0|Add1~18_combout ),
	.cout(\datapath_0|Add1~19 ));
// synopsys translate_off
defparam \datapath_0|Add1~18 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~18 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~20 (
// Equation(s):
// \datapath_0|Add1~20_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [12] & (\datapath_0|Add1~19  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [12] & (!\datapath_0|Add1~19  & VCC))
// \datapath_0|Add1~21  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [12] & !\datapath_0|Add1~19 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [12]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~19 ),
	.combout(\datapath_0|Add1~20_combout ),
	.cout(\datapath_0|Add1~21 ));
// synopsys translate_off
defparam \datapath_0|Add1~20 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~20 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~22 (
// Equation(s):
// \datapath_0|Add1~22_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [13] & (!\datapath_0|Add1~21 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [13] & ((\datapath_0|Add1~21 ) # (GND)))
// \datapath_0|Add1~23  = CARRY((!\datapath_0|Add1~21 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [13]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [13]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~21 ),
	.combout(\datapath_0|Add1~22_combout ),
	.cout(\datapath_0|Add1~23 ));
// synopsys translate_off
defparam \datapath_0|Add1~22 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~22 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~24 (
// Equation(s):
// \datapath_0|Add1~24_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [14] & (\datapath_0|Add1~23  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [14] & (!\datapath_0|Add1~23  & VCC))
// \datapath_0|Add1~25  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [14] & !\datapath_0|Add1~23 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [14]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~23 ),
	.combout(\datapath_0|Add1~24_combout ),
	.cout(\datapath_0|Add1~25 ));
// synopsys translate_off
defparam \datapath_0|Add1~24 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~24 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~26 (
// Equation(s):
// \datapath_0|Add1~26_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [15] & (!\datapath_0|Add1~25 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [15] & ((\datapath_0|Add1~25 ) # (GND)))
// \datapath_0|Add1~27  = CARRY((!\datapath_0|Add1~25 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [15]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [15]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~25 ),
	.combout(\datapath_0|Add1~26_combout ),
	.cout(\datapath_0|Add1~27 ));
// synopsys translate_off
defparam \datapath_0|Add1~26 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~26 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~28 (
// Equation(s):
// \datapath_0|Add1~28_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [16] & (\datapath_0|Add1~27  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [16] & (!\datapath_0|Add1~27  & VCC))
// \datapath_0|Add1~29  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [16] & !\datapath_0|Add1~27 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [16]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~27 ),
	.combout(\datapath_0|Add1~28_combout ),
	.cout(\datapath_0|Add1~29 ));
// synopsys translate_off
defparam \datapath_0|Add1~28 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~28 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~30 (
// Equation(s):
// \datapath_0|Add1~30_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [17] & (!\datapath_0|Add1~29 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [17] & ((\datapath_0|Add1~29 ) # (GND)))
// \datapath_0|Add1~31  = CARRY((!\datapath_0|Add1~29 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [17]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [17]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~29 ),
	.combout(\datapath_0|Add1~30_combout ),
	.cout(\datapath_0|Add1~31 ));
// synopsys translate_off
defparam \datapath_0|Add1~30 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~30 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~32 (
// Equation(s):
// \datapath_0|Add1~32_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [18] & (\datapath_0|Add1~31  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [18] & (!\datapath_0|Add1~31  & VCC))
// \datapath_0|Add1~33  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [18] & !\datapath_0|Add1~31 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [18]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~31 ),
	.combout(\datapath_0|Add1~32_combout ),
	.cout(\datapath_0|Add1~33 ));
// synopsys translate_off
defparam \datapath_0|Add1~32 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~32 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~34 (
// Equation(s):
// \datapath_0|Add1~34_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [19] & (!\datapath_0|Add1~33 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [19] & ((\datapath_0|Add1~33 ) # (GND)))
// \datapath_0|Add1~35  = CARRY((!\datapath_0|Add1~33 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [19]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [19]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~33 ),
	.combout(\datapath_0|Add1~34_combout ),
	.cout(\datapath_0|Add1~35 ));
// synopsys translate_off
defparam \datapath_0|Add1~34 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~34 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~36 (
// Equation(s):
// \datapath_0|Add1~36_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [20] & (\datapath_0|Add1~35  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [20] & (!\datapath_0|Add1~35  & VCC))
// \datapath_0|Add1~37  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [20] & !\datapath_0|Add1~35 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [20]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~35 ),
	.combout(\datapath_0|Add1~36_combout ),
	.cout(\datapath_0|Add1~37 ));
// synopsys translate_off
defparam \datapath_0|Add1~36 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~36 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~38 (
// Equation(s):
// \datapath_0|Add1~38_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [21] & (!\datapath_0|Add1~37 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [21] & ((\datapath_0|Add1~37 ) # (GND)))
// \datapath_0|Add1~39  = CARRY((!\datapath_0|Add1~37 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [21]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [21]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~37 ),
	.combout(\datapath_0|Add1~38_combout ),
	.cout(\datapath_0|Add1~39 ));
// synopsys translate_off
defparam \datapath_0|Add1~38 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~38 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~40 (
// Equation(s):
// \datapath_0|Add1~40_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [22] & (\datapath_0|Add1~39  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [22] & (!\datapath_0|Add1~39  & VCC))
// \datapath_0|Add1~41  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [22] & !\datapath_0|Add1~39 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [22]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~39 ),
	.combout(\datapath_0|Add1~40_combout ),
	.cout(\datapath_0|Add1~41 ));
// synopsys translate_off
defparam \datapath_0|Add1~40 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~40 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~42 (
// Equation(s):
// \datapath_0|Add1~42_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [23] & (!\datapath_0|Add1~41 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [23] & ((\datapath_0|Add1~41 ) # (GND)))
// \datapath_0|Add1~43  = CARRY((!\datapath_0|Add1~41 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [23]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [23]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~41 ),
	.combout(\datapath_0|Add1~42_combout ),
	.cout(\datapath_0|Add1~43 ));
// synopsys translate_off
defparam \datapath_0|Add1~42 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~42 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~44 (
// Equation(s):
// \datapath_0|Add1~44_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [24] & (\datapath_0|Add1~43  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [24] & (!\datapath_0|Add1~43  & VCC))
// \datapath_0|Add1~45  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [24] & !\datapath_0|Add1~43 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [24]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~43 ),
	.combout(\datapath_0|Add1~44_combout ),
	.cout(\datapath_0|Add1~45 ));
// synopsys translate_off
defparam \datapath_0|Add1~44 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~44 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~46 (
// Equation(s):
// \datapath_0|Add1~46_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [25] & (!\datapath_0|Add1~45 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [25] & ((\datapath_0|Add1~45 ) # (GND)))
// \datapath_0|Add1~47  = CARRY((!\datapath_0|Add1~45 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [25]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [25]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~45 ),
	.combout(\datapath_0|Add1~46_combout ),
	.cout(\datapath_0|Add1~47 ));
// synopsys translate_off
defparam \datapath_0|Add1~46 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~46 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~48 (
// Equation(s):
// \datapath_0|Add1~48_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [26] & (\datapath_0|Add1~47  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [26] & (!\datapath_0|Add1~47  & VCC))
// \datapath_0|Add1~49  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [26] & !\datapath_0|Add1~47 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [26]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~47 ),
	.combout(\datapath_0|Add1~48_combout ),
	.cout(\datapath_0|Add1~49 ));
// synopsys translate_off
defparam \datapath_0|Add1~48 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~48 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~50 (
// Equation(s):
// \datapath_0|Add1~50_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [27] & (!\datapath_0|Add1~49 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [27] & ((\datapath_0|Add1~49 ) # (GND)))
// \datapath_0|Add1~51  = CARRY((!\datapath_0|Add1~49 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [27]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [27]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~49 ),
	.combout(\datapath_0|Add1~50_combout ),
	.cout(\datapath_0|Add1~51 ));
// synopsys translate_off
defparam \datapath_0|Add1~50 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~50 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~52 (
// Equation(s):
// \datapath_0|Add1~52_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [28] & (\datapath_0|Add1~51  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [28] & (!\datapath_0|Add1~51  & VCC))
// \datapath_0|Add1~53  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [28] & !\datapath_0|Add1~51 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [28]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~51 ),
	.combout(\datapath_0|Add1~52_combout ),
	.cout(\datapath_0|Add1~53 ));
// synopsys translate_off
defparam \datapath_0|Add1~52 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~52 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~54 (
// Equation(s):
// \datapath_0|Add1~54_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [29] & (!\datapath_0|Add1~53 )) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [29] & ((\datapath_0|Add1~53 ) # (GND)))
// \datapath_0|Add1~55  = CARRY((!\datapath_0|Add1~53 ) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [29]))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [29]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~53 ),
	.combout(\datapath_0|Add1~54_combout ),
	.cout(\datapath_0|Add1~55 ));
// synopsys translate_off
defparam \datapath_0|Add1~54 .lut_mask = 16'h5A5F;
defparam \datapath_0|Add1~54 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~56 (
// Equation(s):
// \datapath_0|Add1~56_combout  = (\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [30] & (\datapath_0|Add1~55  $ (GND))) # (!\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [30] & (!\datapath_0|Add1~55  & VCC))
// \datapath_0|Add1~57  = CARRY((\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [30] & !\datapath_0|Add1~55 ))

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [30]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|Add1~55 ),
	.combout(\datapath_0|Add1~56_combout ),
	.cout(\datapath_0|Add1~57 ));
// synopsys translate_off
defparam \datapath_0|Add1~56 .lut_mask = 16'hA50A;
defparam \datapath_0|Add1~56 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|Add1~58 (
// Equation(s):
// \datapath_0|Add1~58_combout  = \datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [31] $ (\datapath_0|Add1~57 )

	.dataa(\datapath_0|MEM_WB_PLR|instruction_address_reg|internal_value [31]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\datapath_0|Add1~57 ),
	.combout(\datapath_0|Add1~58_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|Add1~58 .lut_mask = 16'h5A5A;
defparam \datapath_0|Add1~58 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux0~1 (
// Equation(s):
// \datapath_0|mux_0|Mux0~1_combout  = (\datapath_0|mux_0|Mux0~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~58_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux0~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~58_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux0~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux0~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux0~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux0~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux0~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [31] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux0~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [31]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux0~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux0~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux0~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux0~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [31])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [31]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux0~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~5 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~5_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [29] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [29]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~5 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[5] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [5] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~5_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [5])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~5_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[5] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~621 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~621_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~621_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~621 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~621 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~622 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~622_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~621_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~621_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~621_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~621_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~622_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~622 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~622 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~623 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~623_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~623_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~623 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~623 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~624 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~624_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~623_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~623_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~623_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~623_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~624_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~624 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~624 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~625 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~625_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~622_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~624_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~622_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~624_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~625_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~625 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~625 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~626 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~626_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~626_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~626 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~626 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~627 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~627_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~626_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~626_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~626_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~626_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~627_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~627 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~627 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~628 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~628_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~625_combout  & ((\datapath_0|datamem_module_0|output_data~627_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~625_combout  & (\datapath_0|datamem_module_0|output_data~620_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~625_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~620_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~625_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~627_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~628_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~628 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~628 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~629 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~629_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~618_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~628_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~618_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~628_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~629_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~629 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~629 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[29] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [29] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [29]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~629_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~629_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [29]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [29]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[29] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[29] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux2~1 (
// Equation(s):
// \datapath_0|mux_0|Mux2~1_combout  = (\datapath_0|mux_0|Mux2~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~54_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux2~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~54_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux2~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux2~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux2~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux2~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux2~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [29] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux2~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [29]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux2~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux2~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux2~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux2~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [29])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [29]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux2~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux2~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~3 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~3_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [27] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [27]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~3 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[3] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [3] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~3_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [3])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~3_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[3] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~579 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~579_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~579_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~579 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~579 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~580 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~580_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~579_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~579_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~579_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~579_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~580_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~580 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~580 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~581 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~581_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~581_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~581 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~581 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~582 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~582_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~581_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~581_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~581_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~581_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~582_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~582 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~582 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~583 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~583_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~580_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~582_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~580_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~582_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~583_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~583 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~583 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~584 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~584_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~584_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~584 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~584 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~585 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~585_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~584_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~584_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~584_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~584_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~585_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~585 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~585 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~586 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~586_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~583_combout  & ((\datapath_0|datamem_module_0|output_data~585_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~583_combout  & (\datapath_0|datamem_module_0|output_data~578_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~583_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~578_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~583_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~585_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~586_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~586 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~586 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~587 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~587_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~576_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~586_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~576_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~586_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~587_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~587 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~587 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[27] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [27] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [27]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~587_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~587_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [27]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [27]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[27] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[27] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux4~1 (
// Equation(s):
// \datapath_0|mux_0|Mux4~1_combout  = (\datapath_0|mux_0|Mux4~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~50_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux4~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~50_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux4~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux4~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux4~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux4~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux4~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux4~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [27] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux4~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [27]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux4~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux4~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux4~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux4~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux4~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [27])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [27]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux4~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux4~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux4~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~1 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~1_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [25] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [25]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~1 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[1] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [1] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~1_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [1])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~1_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[1] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~537 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~537_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x10|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x8|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~537_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~537 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~537 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~538 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~538_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~537_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~537_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~537_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x9|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~537_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x11|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~538_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~538 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~538 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~539 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~539_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~539_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~539 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~539 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~540 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~540_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~539_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~539_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~539_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~539_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~540_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~540 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~540 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~541 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~541_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~538_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~540_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~538_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~540_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~541_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~541 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~541 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~542 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~542_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~542_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~542 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~542 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~543 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~543_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~542_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~542_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~542_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~542_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~543_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~543 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~543 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~544 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~544_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~541_combout  & ((\datapath_0|datamem_module_0|output_data~543_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~541_combout  & (\datapath_0|datamem_module_0|output_data~536_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~541_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~536_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~541_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~543_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~544_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~544 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~544 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~545 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~545_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~534_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~544_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~534_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~544_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~545_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~545 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~545 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[25] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [25] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [25]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~545_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~545_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [25]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [25]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[25] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[25] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux6~1 (
// Equation(s):
// \datapath_0|mux_0|Mux6~1_combout  = (\datapath_0|mux_0|Mux6~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~46_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux6~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~46_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux6~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux6~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux6~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux6~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux6~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux6~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [25] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux6~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [25]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux6~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux6~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux6~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux6~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux6~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [25])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [25]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux6~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux6~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux6~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~7 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~7_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [23] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [23]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~7 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[7] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [7] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~7_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [7])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~7_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[7] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[7] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~495 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~495_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~495_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~495 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~495 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~496 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~496_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~495_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~495_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~495_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~495_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~496_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~496 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~496 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~497 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~497_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~497_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~497 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~497 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~498 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~498_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~497_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~497_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~497_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~497_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~498_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~498 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~498 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~499 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~499_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~496_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~498_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~496_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~498_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~499_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~499 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~499 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~500 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~500_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~500_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~500 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~500 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~501 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~501_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~500_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~500_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~500_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~500_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~501_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~501 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~501 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~502 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~502_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~499_combout  & ((\datapath_0|datamem_module_0|output_data~501_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~499_combout  & (\datapath_0|datamem_module_0|output_data~494_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~499_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~494_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~499_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~501_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~502_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~502 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~502 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~503 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~503_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~492_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~502_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~492_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~502_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~503_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~503 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~503 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[23] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [23] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [23]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~503_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~503_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [23]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [23]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[23] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[23] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux8~1 (
// Equation(s):
// \datapath_0|mux_0|Mux8~1_combout  = (\datapath_0|mux_0|Mux8~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~42_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux8~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~42_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux8~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux8~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux8~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux8~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [23] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux8~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [23]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux8~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux8~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux8~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [23])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [23]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux8~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~5 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~5_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [21] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [21]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~5 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[5] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [5] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~5_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [5])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~5_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[5] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~453 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~453_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~453_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~453 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~453 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~454 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~454_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~453_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~453_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~453_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~453_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~454_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~454 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~454 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~455 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~455_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~455_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~455 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~455 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~456 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~456_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~455_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~455_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~455_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~455_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~456_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~456 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~456 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~457 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~457_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~454_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~456_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~454_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~456_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~457_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~457 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~457 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~458 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~458_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~458_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~458 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~458 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~459 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~459_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~458_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~458_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~458_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~458_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~459_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~459 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~459 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~460 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~460_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~457_combout  & ((\datapath_0|datamem_module_0|output_data~459_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~457_combout  & (\datapath_0|datamem_module_0|output_data~452_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~457_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~452_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~457_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~459_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~460_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~460 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~460 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~461 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~461_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~450_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~460_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~450_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~460_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~461_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~461 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~461 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[21] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [21] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [21]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~461_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~461_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [21]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [21]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[21] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[21] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux10~1 (
// Equation(s):
// \datapath_0|mux_0|Mux10~1_combout  = (\datapath_0|mux_0|Mux10~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~38_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux10~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~38_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux10~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux10~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux10~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux10~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux10~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux10~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [21] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux10~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [21]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux10~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux10~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux10~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux10~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux10~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [21])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [21]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux10~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~3 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~3_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [19] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [19]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~3 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[3] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [3] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~3_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [3])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~3_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[3] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~411 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~411_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~411_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~411 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~411 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~412 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~412_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~411_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~411_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~411_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~411_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~412_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~412 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~412 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~413 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~413_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~413_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~413 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~413 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~414 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~414_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~413_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~413_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~413_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~413_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~414_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~414 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~414 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~415 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~415_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~412_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~414_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~412_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~414_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~415_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~415 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~415 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~416 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~416_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~416_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~416 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~416 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~417 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~417_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~416_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~416_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~416_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~416_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~417_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~417 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~417 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~418 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~418_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~415_combout  & ((\datapath_0|datamem_module_0|output_data~417_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~415_combout  & (\datapath_0|datamem_module_0|output_data~410_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~415_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~410_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~415_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~417_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~418_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~418 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~418 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~419 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~419_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~408_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~418_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~408_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~418_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~419_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~419 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~419 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[19] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [19] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [19]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~419_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~419_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [19]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [19]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[19] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[19] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux12~1 (
// Equation(s):
// \datapath_0|mux_0|Mux12~1_combout  = (\datapath_0|mux_0|Mux12~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~34_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux12~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~34_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux12~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux12~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux12~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux12~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux12~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux12~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [19] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux12~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [19]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux12~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux12~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux12~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux12~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux12~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [19])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [19]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux12~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux12~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux12~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~1 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~1_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [17] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [17]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~1 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[1] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [1] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~1_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [1])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~1_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[1] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~369 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~369_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x10|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x8|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~369_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~369 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~369 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~370 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~370_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~369_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~369_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~369_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x9|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~369_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x11|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~370_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~370 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~370 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~371 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~371_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~371_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~371 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~371 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~372 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~372_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~371_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~371_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~371_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~371_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~372_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~372 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~372 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~373 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~373_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~370_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~372_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~370_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~372_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~373_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~373 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~373 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~374 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~374_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~374_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~374 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~374 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~375 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~375_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~374_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~374_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~374_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~374_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~375_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~375 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~375 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~376 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~376_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~373_combout  & ((\datapath_0|datamem_module_0|output_data~375_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~373_combout  & (\datapath_0|datamem_module_0|output_data~368_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~373_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~368_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~373_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~375_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~376_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~376 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~376 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~377 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~377_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~366_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~376_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~366_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~376_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~377_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~377 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~377 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[17] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [17] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [17]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~377_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~377_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [17]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [17]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[17] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[17] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux14~1 (
// Equation(s):
// \datapath_0|mux_0|Mux14~1_combout  = (\datapath_0|mux_0|Mux14~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~30_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux14~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~30_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux14~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux14~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux14~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux14~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux14~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux14~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [17] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux14~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [17]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux14~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux14~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux14~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux14~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux14~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [17])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [17]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux14~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux14~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux14~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~7 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~7_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [15] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [15]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~7 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[7] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [7] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~7_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [7])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~7_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[7] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[7] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~327 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~327_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~327_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~327 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~327 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~328 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~328_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~327_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~327_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~327_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~327_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~328_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~328 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~328 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~329 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~329_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~329_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~329 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~329 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~330 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~330_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~329_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~329_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~329_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~329_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~330_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~330 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~330 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~331 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~331_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~328_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~330_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~328_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~330_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~331_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~331 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~331 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~332 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~332_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~332_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~332 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~332 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~333 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~333_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~332_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~332_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~332_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~332_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~333_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~333 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~333 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~334 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~334_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~331_combout  & ((\datapath_0|datamem_module_0|output_data~333_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~331_combout  & (\datapath_0|datamem_module_0|output_data~326_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~331_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~326_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~331_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~333_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~334_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~334 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~334 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~335 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~335_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~324_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~334_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~324_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~334_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~335_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~335 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~335 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[15] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [15] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [15]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~335_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~335_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [15]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [15]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[15] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[15] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux16~1 (
// Equation(s):
// \datapath_0|mux_0|Mux16~1_combout  = (\datapath_0|mux_0|Mux16~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~26_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux16~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~26_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux16~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux16~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux16~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux16~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux16~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux16~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [15] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux16~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [15]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux16~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux16~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux16~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux16~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux16~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [15])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [15]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux16~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~5 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~5_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [13] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [13]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~5 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[5] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [5] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~5_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [5])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~5_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[5] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[5] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~285 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~285_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~285_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~285 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~285 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~286 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~286_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~285_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~285_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~285_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~285_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~286_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~286 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~286 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~287 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~287_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~287_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~287 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~287 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~288 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~288_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~287_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~287_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~287_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~287_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~288_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~288 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~288 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~289 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~289_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~286_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~288_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~286_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~288_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~289_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~289 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~289 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~290 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~290_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [5])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [5])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [5]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~290_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~290 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~290 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [5]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~291 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~291_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~290_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [5]))) # 
// (!\datapath_0|datamem_module_0|output_data~290_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~290_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [5]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~290_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~291_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~291 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~291 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~292 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~292_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~289_combout  & ((\datapath_0|datamem_module_0|output_data~291_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~289_combout  & (\datapath_0|datamem_module_0|output_data~284_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~289_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~284_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~289_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~291_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~292_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~292 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~292 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~293 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~293_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~282_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~292_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~282_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~292_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~293_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~293 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~293 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[13] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [13] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [13]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~293_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~293_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [13]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [13]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[13] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[13] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux18~1 (
// Equation(s):
// \datapath_0|mux_0|Mux18~1_combout  = (\datapath_0|mux_0|Mux18~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~22_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux18~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~22_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux18~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux18~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux18~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux18~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux18~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux18~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [13] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux18~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [13]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux18~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux18~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux18~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux18~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux18~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [13])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [13]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux18~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux18~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux18~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~3 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~3_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [11] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [11]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~3 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[3] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [3] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~3_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [3])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~3_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[3] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~243 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~243_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~243_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~243 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~243 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~244 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~244_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~243_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~243_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~243_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~243_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~244_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~244 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~244 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~245 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~245_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~245_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~245 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~245 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~246 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~246_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~245_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~245_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~245_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~245_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~246_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~246 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~246 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~247 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~247_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~244_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~246_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~244_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~246_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~247_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~247 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~247 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~248 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~248_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [3])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [3])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~248_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~248 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~248 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [3]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~249 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~249_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~248_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [3]))) # 
// (!\datapath_0|datamem_module_0|output_data~248_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~248_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [3]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~248_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~249_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~249 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~249 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~250 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~250_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~247_combout  & ((\datapath_0|datamem_module_0|output_data~249_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~247_combout  & (\datapath_0|datamem_module_0|output_data~242_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~247_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~242_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~247_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~249_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~250_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~250 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~250 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~251 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~251_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~240_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~250_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~240_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~250_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~251_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~251 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~251 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[11] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [11] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [11]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~251_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~251_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [11]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [11]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[11] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[11] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux20~1 (
// Equation(s):
// \datapath_0|mux_0|Mux20~1_combout  = (\datapath_0|mux_0|Mux20~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~18_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux20~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~18_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux20~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux20~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux20~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux20~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux20~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux20~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [11] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux20~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [11]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux20~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux20~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux20~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux20~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux20~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [11])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [11]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux20~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux20~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux20~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~1 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~1_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [9] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [9]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~1 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[1] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [1] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~1_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [1])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~1_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[1] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~201 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~201_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x10|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x8|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~201_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~201 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~201 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~202 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~202_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~201_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~201_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~201_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x9|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~201_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x11|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~202_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~202 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~202 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~203 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~203_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~203_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~203 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~203 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~204 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~204_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~203_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~203_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~203_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~203_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~204_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~204 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~204 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~205 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~205_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~202_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~204_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~202_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~204_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~205_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~205 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~205 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~206 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~206_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [1])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [1])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [1]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~206_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~206 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~206 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [1]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~207 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~207_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~206_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [1]))) # 
// (!\datapath_0|datamem_module_0|output_data~206_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~206_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~206_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~207_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~207 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~207 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~208 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~208_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~205_combout  & ((\datapath_0|datamem_module_0|output_data~207_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~205_combout  & (\datapath_0|datamem_module_0|output_data~200_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~205_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~200_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~205_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~207_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~208_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~208 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~208 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~209 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~209_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~198_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~208_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~198_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~208_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~209_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~209 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~209 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[9] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [9] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [9]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~209_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~209_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [9]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [9]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[9] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[9] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux22~1 (
// Equation(s):
// \datapath_0|mux_0|Mux22~1_combout  = (\datapath_0|mux_0|Mux22~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~14_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux22~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~14_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux22~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux22~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux22~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux22~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux22~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux22~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [9] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux22~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [9]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux22~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux22~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux22~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux22~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux22~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [9])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [9]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux22~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux22~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux22~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[7]~7 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0[7]~7_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [7] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [7]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0[7]~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[7]~7 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_0[7]~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_0[7] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_0 [7] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_0[7]~7_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_0 [7])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_0[7]~7_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_0[7] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_0[7] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[10]~16_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[8]~18_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~159 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~159_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x10|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x8|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~159_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~159 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~159 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[11]~19_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~160 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~160_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~159_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~159_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~159_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x9|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~159_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x11|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~160_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~160 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~160 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[2]~24_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~161 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~161_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value 
// [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x2|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x0|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~161_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~161 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~161 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~162 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~162_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~161_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~161_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~161_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x1|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~161_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x3|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~162_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~162 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~162 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~163 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~163_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (\datapath_0|datamem_module_0|output_data~160_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~162_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datab(\datapath_0|datamem_module_0|output_data~160_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datad(\datapath_0|datamem_module_0|output_data~162_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~163_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~163 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~163 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[13]~28_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~164 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~164_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [7])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [7])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_0|reg_x13|internal_value [7]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x12|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~164_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~164 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~164 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_0 [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~165 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~165_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~164_combout  & ((\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [7]))) # 
// (!\datapath_0|datamem_module_0|output_data~164_combout  & (\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [7])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~164_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_0|reg_x14|internal_value [7]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~164_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_0|reg_x15|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~165_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~165 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~165 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~166 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~166_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~163_combout  & ((\datapath_0|datamem_module_0|output_data~165_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~163_combout  & (\datapath_0|datamem_module_0|output_data~158_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (((\datapath_0|datamem_module_0|output_data~163_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~158_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|datamem_module_0|output_data~163_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~165_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~166_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~166 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~166 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~167 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~167_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~156_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~166_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~156_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~166_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~167_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~167 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~167 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[7] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [7] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [7]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~167_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~167_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [7]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[7] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[7] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux24~1 (
// Equation(s):
// \datapath_0|mux_0|Mux24~1_combout  = (\datapath_0|mux_0|Mux24~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~10_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux24~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~10_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux24~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux24~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux24~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux24~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [7] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux24~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [7]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux24~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux24~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux24~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [7])) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [7]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux24~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~48 (
// Equation(s):
// \datapath_0|ALU_0|Add0~48_combout  = ((\datapath_0|ALU_0|Add0~24_combout  $ (\datapath_0|forward_mux_0|Mux24~2_combout  $ (!\datapath_0|ALU_0|Add0~47 )))) # (GND)
// \datapath_0|ALU_0|Add0~49  = CARRY((\datapath_0|ALU_0|Add0~24_combout  & ((\datapath_0|forward_mux_0|Mux24~2_combout ) # (!\datapath_0|ALU_0|Add0~47 ))) # (!\datapath_0|ALU_0|Add0~24_combout  & (\datapath_0|forward_mux_0|Mux24~2_combout  & 
// !\datapath_0|ALU_0|Add0~47 )))

	.dataa(\datapath_0|ALU_0|Add0~24_combout ),
	.datab(\datapath_0|forward_mux_0|Mux24~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~47 ),
	.combout(\datapath_0|ALU_0|Add0~48_combout ),
	.cout(\datapath_0|ALU_0|Add0~49 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~48 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~48 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[7] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [7] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [7]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~48_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~48_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [7]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [7]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[7] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[7] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux24~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux24~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux24~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]))) # (!\datapath_0|forward_mux_0|Mux24~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux24~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux24~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux24~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux24~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux24~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux24~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7]),
	.datab(\datapath_0|forward_mux_0|Mux24~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux24~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux24~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux24~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~50 (
// Equation(s):
// \datapath_0|ALU_0|Add0~50_combout  = (\datapath_0|ALU_0|Add0~23_combout  & ((\datapath_0|forward_mux_0|Mux23~2_combout  & (\datapath_0|ALU_0|Add0~49  & VCC)) # (!\datapath_0|forward_mux_0|Mux23~2_combout  & (!\datapath_0|ALU_0|Add0~49 )))) # 
// (!\datapath_0|ALU_0|Add0~23_combout  & ((\datapath_0|forward_mux_0|Mux23~2_combout  & (!\datapath_0|ALU_0|Add0~49 )) # (!\datapath_0|forward_mux_0|Mux23~2_combout  & ((\datapath_0|ALU_0|Add0~49 ) # (GND)))))
// \datapath_0|ALU_0|Add0~51  = CARRY((\datapath_0|ALU_0|Add0~23_combout  & (!\datapath_0|forward_mux_0|Mux23~2_combout  & !\datapath_0|ALU_0|Add0~49 )) # (!\datapath_0|ALU_0|Add0~23_combout  & ((!\datapath_0|ALU_0|Add0~49 ) # 
// (!\datapath_0|forward_mux_0|Mux23~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~23_combout ),
	.datab(\datapath_0|forward_mux_0|Mux23~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~49 ),
	.combout(\datapath_0|ALU_0|Add0~50_combout ),
	.cout(\datapath_0|ALU_0|Add0~51 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~50 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~50 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[8] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [8] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [8]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~50_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~50_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [8]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [8]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[8] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[8] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [8]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux23~1 (
// Equation(s):
// \datapath_0|mux_0|Mux23~1_combout  = (\datapath_0|mux_0|Mux23~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~12_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux23~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~12_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux23~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux23~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux23~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux23~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux23~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux23~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [8] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux23~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [8]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux23~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux23~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux23~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux23~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux23~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux23~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux23~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux23~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux23~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]))) # (!\datapath_0|forward_mux_0|Mux23~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [8])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux23~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [8]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux23~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux23~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux23~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux23~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux23~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux23~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux23~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8]),
	.datab(\datapath_0|forward_mux_0|Mux23~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux23~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux23~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux23~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~52 (
// Equation(s):
// \datapath_0|ALU_0|Add0~52_combout  = ((\datapath_0|ALU_0|Add0~22_combout  $ (\datapath_0|forward_mux_0|Mux22~2_combout  $ (!\datapath_0|ALU_0|Add0~51 )))) # (GND)
// \datapath_0|ALU_0|Add0~53  = CARRY((\datapath_0|ALU_0|Add0~22_combout  & ((\datapath_0|forward_mux_0|Mux22~2_combout ) # (!\datapath_0|ALU_0|Add0~51 ))) # (!\datapath_0|ALU_0|Add0~22_combout  & (\datapath_0|forward_mux_0|Mux22~2_combout  & 
// !\datapath_0|ALU_0|Add0~51 )))

	.dataa(\datapath_0|ALU_0|Add0~22_combout ),
	.datab(\datapath_0|forward_mux_0|Mux22~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~51 ),
	.combout(\datapath_0|ALU_0|Add0~52_combout ),
	.cout(\datapath_0|ALU_0|Add0~53 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~52 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~52 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[9] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [9] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [9]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~52_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~52_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [9]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [9]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[9] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[9] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [9]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux22~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux22~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux22~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]))) # (!\datapath_0|forward_mux_0|Mux22~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux22~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux22~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux22~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux22~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux22~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux22~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux22~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux22~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9]),
	.datab(\datapath_0|forward_mux_0|Mux22~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux22~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux22~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux22~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~54 (
// Equation(s):
// \datapath_0|ALU_0|Add0~54_combout  = (\datapath_0|ALU_0|Add0~21_combout  & ((\datapath_0|forward_mux_0|Mux21~2_combout  & (\datapath_0|ALU_0|Add0~53  & VCC)) # (!\datapath_0|forward_mux_0|Mux21~2_combout  & (!\datapath_0|ALU_0|Add0~53 )))) # 
// (!\datapath_0|ALU_0|Add0~21_combout  & ((\datapath_0|forward_mux_0|Mux21~2_combout  & (!\datapath_0|ALU_0|Add0~53 )) # (!\datapath_0|forward_mux_0|Mux21~2_combout  & ((\datapath_0|ALU_0|Add0~53 ) # (GND)))))
// \datapath_0|ALU_0|Add0~55  = CARRY((\datapath_0|ALU_0|Add0~21_combout  & (!\datapath_0|forward_mux_0|Mux21~2_combout  & !\datapath_0|ALU_0|Add0~53 )) # (!\datapath_0|ALU_0|Add0~21_combout  & ((!\datapath_0|ALU_0|Add0~53 ) # 
// (!\datapath_0|forward_mux_0|Mux21~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~21_combout ),
	.datab(\datapath_0|forward_mux_0|Mux21~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~53 ),
	.combout(\datapath_0|ALU_0|Add0~54_combout ),
	.cout(\datapath_0|ALU_0|Add0~55 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~54 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~54 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[10] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [10] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [10]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~54_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~54_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [10]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [10]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[10] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[10] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [10]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux21~1 (
// Equation(s):
// \datapath_0|mux_0|Mux21~1_combout  = (\datapath_0|mux_0|Mux21~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~16_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux21~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~16_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux21~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux21~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux21~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux21~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux21~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux21~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [10] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux21~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [10]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux21~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux21~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux21~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux21~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux21~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux21~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux21~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux21~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux21~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]))) # 
// (!\datapath_0|forward_mux_0|Mux21~0_combout  & (\datapath_0|datamem_module_0|output_data [10])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux21~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [10]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux21~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux21~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux21~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux21~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux21~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux21~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux21~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10]),
	.datab(\datapath_0|forward_mux_0|Mux21~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux21~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux21~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux21~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~56 (
// Equation(s):
// \datapath_0|ALU_0|Add0~56_combout  = ((\datapath_0|ALU_0|Add0~20_combout  $ (\datapath_0|forward_mux_0|Mux20~2_combout  $ (!\datapath_0|ALU_0|Add0~55 )))) # (GND)
// \datapath_0|ALU_0|Add0~57  = CARRY((\datapath_0|ALU_0|Add0~20_combout  & ((\datapath_0|forward_mux_0|Mux20~2_combout ) # (!\datapath_0|ALU_0|Add0~55 ))) # (!\datapath_0|ALU_0|Add0~20_combout  & (\datapath_0|forward_mux_0|Mux20~2_combout  & 
// !\datapath_0|ALU_0|Add0~55 )))

	.dataa(\datapath_0|ALU_0|Add0~20_combout ),
	.datab(\datapath_0|forward_mux_0|Mux20~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~55 ),
	.combout(\datapath_0|ALU_0|Add0~56_combout ),
	.cout(\datapath_0|ALU_0|Add0~57 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~56 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~56 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[11] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [11] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [11]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~56_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~56_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [11]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [11]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[11] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[11] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [11]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux20~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux20~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux20~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]))) # 
// (!\datapath_0|forward_mux_0|Mux20~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux20~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux20~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux20~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux20~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux20~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux20~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux20~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux20~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11]),
	.datab(\datapath_0|forward_mux_0|Mux20~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux20~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux20~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux20~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~58 (
// Equation(s):
// \datapath_0|ALU_0|Add0~58_combout  = (\datapath_0|ALU_0|Add0~19_combout  & ((\datapath_0|forward_mux_0|Mux19~2_combout  & (\datapath_0|ALU_0|Add0~57  & VCC)) # (!\datapath_0|forward_mux_0|Mux19~2_combout  & (!\datapath_0|ALU_0|Add0~57 )))) # 
// (!\datapath_0|ALU_0|Add0~19_combout  & ((\datapath_0|forward_mux_0|Mux19~2_combout  & (!\datapath_0|ALU_0|Add0~57 )) # (!\datapath_0|forward_mux_0|Mux19~2_combout  & ((\datapath_0|ALU_0|Add0~57 ) # (GND)))))
// \datapath_0|ALU_0|Add0~59  = CARRY((\datapath_0|ALU_0|Add0~19_combout  & (!\datapath_0|forward_mux_0|Mux19~2_combout  & !\datapath_0|ALU_0|Add0~57 )) # (!\datapath_0|ALU_0|Add0~19_combout  & ((!\datapath_0|ALU_0|Add0~57 ) # 
// (!\datapath_0|forward_mux_0|Mux19~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~19_combout ),
	.datab(\datapath_0|forward_mux_0|Mux19~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~57 ),
	.combout(\datapath_0|ALU_0|Add0~58_combout ),
	.cout(\datapath_0|ALU_0|Add0~59 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~58 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~58 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[12] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [12] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [12]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~58_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~58_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [12]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [12]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[12] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[12] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [12]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux19~1 (
// Equation(s):
// \datapath_0|mux_0|Mux19~1_combout  = (\datapath_0|mux_0|Mux19~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~20_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux19~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~20_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux19~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux19~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux19~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux19~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux19~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux19~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [12] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux19~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [12]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux19~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux19~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux19~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux19~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux19~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux19~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux19~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux19~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux19~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux19~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux19~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]))) # 
// (!\datapath_0|forward_mux_0|Mux19~0_combout  & (\datapath_0|datamem_module_0|output_data [12])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux19~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [12]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux19~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux19~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux19~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux19~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux19~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux19~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux19~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12]),
	.datab(\datapath_0|forward_mux_0|Mux19~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux19~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux19~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux19~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~60 (
// Equation(s):
// \datapath_0|ALU_0|Add0~60_combout  = ((\datapath_0|ALU_0|Add0~18_combout  $ (\datapath_0|forward_mux_0|Mux18~2_combout  $ (!\datapath_0|ALU_0|Add0~59 )))) # (GND)
// \datapath_0|ALU_0|Add0~61  = CARRY((\datapath_0|ALU_0|Add0~18_combout  & ((\datapath_0|forward_mux_0|Mux18~2_combout ) # (!\datapath_0|ALU_0|Add0~59 ))) # (!\datapath_0|ALU_0|Add0~18_combout  & (\datapath_0|forward_mux_0|Mux18~2_combout  & 
// !\datapath_0|ALU_0|Add0~59 )))

	.dataa(\datapath_0|ALU_0|Add0~18_combout ),
	.datab(\datapath_0|forward_mux_0|Mux18~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~59 ),
	.combout(\datapath_0|ALU_0|Add0~60_combout ),
	.cout(\datapath_0|ALU_0|Add0~61 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~60 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~60 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[13] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [13] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [13]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~60_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~60_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [13]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [13]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[13] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[13] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [13]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux18~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux18~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux18~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]))) # 
// (!\datapath_0|forward_mux_0|Mux18~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux18~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux18~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux18~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux18~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux18~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux18~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux18~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux18~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13]),
	.datab(\datapath_0|forward_mux_0|Mux18~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux18~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux18~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux18~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~62 (
// Equation(s):
// \datapath_0|ALU_0|Add0~62_combout  = (\datapath_0|ALU_0|Add0~17_combout  & ((\datapath_0|forward_mux_0|Mux17~2_combout  & (\datapath_0|ALU_0|Add0~61  & VCC)) # (!\datapath_0|forward_mux_0|Mux17~2_combout  & (!\datapath_0|ALU_0|Add0~61 )))) # 
// (!\datapath_0|ALU_0|Add0~17_combout  & ((\datapath_0|forward_mux_0|Mux17~2_combout  & (!\datapath_0|ALU_0|Add0~61 )) # (!\datapath_0|forward_mux_0|Mux17~2_combout  & ((\datapath_0|ALU_0|Add0~61 ) # (GND)))))
// \datapath_0|ALU_0|Add0~63  = CARRY((\datapath_0|ALU_0|Add0~17_combout  & (!\datapath_0|forward_mux_0|Mux17~2_combout  & !\datapath_0|ALU_0|Add0~61 )) # (!\datapath_0|ALU_0|Add0~17_combout  & ((!\datapath_0|ALU_0|Add0~61 ) # 
// (!\datapath_0|forward_mux_0|Mux17~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~17_combout ),
	.datab(\datapath_0|forward_mux_0|Mux17~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~61 ),
	.combout(\datapath_0|ALU_0|Add0~62_combout ),
	.cout(\datapath_0|ALU_0|Add0~63 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~62 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~62 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[14] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [14] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [14]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~62_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~62_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [14]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [14]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[14] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[14] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [14]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux17~1 (
// Equation(s):
// \datapath_0|mux_0|Mux17~1_combout  = (\datapath_0|mux_0|Mux17~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~24_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux17~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~24_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux17~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux17~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux17~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux17~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux17~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux17~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [14] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux17~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [14]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux17~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux17~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux17~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux17~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux17~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux17~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux17~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux17~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux17~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux17~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux17~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]))) # 
// (!\datapath_0|forward_mux_0|Mux17~0_combout  & (\datapath_0|datamem_module_0|output_data [14])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux17~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [14]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux17~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux17~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux17~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux17~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux17~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux17~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux17~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14]),
	.datab(\datapath_0|forward_mux_0|Mux17~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux17~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux17~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux17~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~64 (
// Equation(s):
// \datapath_0|ALU_0|Add0~64_combout  = ((\datapath_0|ALU_0|Add0~16_combout  $ (\datapath_0|forward_mux_0|Mux16~2_combout  $ (!\datapath_0|ALU_0|Add0~63 )))) # (GND)
// \datapath_0|ALU_0|Add0~65  = CARRY((\datapath_0|ALU_0|Add0~16_combout  & ((\datapath_0|forward_mux_0|Mux16~2_combout ) # (!\datapath_0|ALU_0|Add0~63 ))) # (!\datapath_0|ALU_0|Add0~16_combout  & (\datapath_0|forward_mux_0|Mux16~2_combout  & 
// !\datapath_0|ALU_0|Add0~63 )))

	.dataa(\datapath_0|ALU_0|Add0~16_combout ),
	.datab(\datapath_0|forward_mux_0|Mux16~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~63 ),
	.combout(\datapath_0|ALU_0|Add0~64_combout ),
	.cout(\datapath_0|ALU_0|Add0~65 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~64 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~64 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[15] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [15] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [15]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~64_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~64_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [15]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [15]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[15] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[15] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [15]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux16~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux16~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux16~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]))) # 
// (!\datapath_0|forward_mux_0|Mux16~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux16~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux16~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux16~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux16~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux16~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux16~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux16~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux16~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15]),
	.datab(\datapath_0|forward_mux_0|Mux16~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux16~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux16~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux16~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~66 (
// Equation(s):
// \datapath_0|ALU_0|Add0~66_combout  = (\datapath_0|ALU_0|Add0~15_combout  & ((\datapath_0|forward_mux_0|Mux15~2_combout  & (\datapath_0|ALU_0|Add0~65  & VCC)) # (!\datapath_0|forward_mux_0|Mux15~2_combout  & (!\datapath_0|ALU_0|Add0~65 )))) # 
// (!\datapath_0|ALU_0|Add0~15_combout  & ((\datapath_0|forward_mux_0|Mux15~2_combout  & (!\datapath_0|ALU_0|Add0~65 )) # (!\datapath_0|forward_mux_0|Mux15~2_combout  & ((\datapath_0|ALU_0|Add0~65 ) # (GND)))))
// \datapath_0|ALU_0|Add0~67  = CARRY((\datapath_0|ALU_0|Add0~15_combout  & (!\datapath_0|forward_mux_0|Mux15~2_combout  & !\datapath_0|ALU_0|Add0~65 )) # (!\datapath_0|ALU_0|Add0~15_combout  & ((!\datapath_0|ALU_0|Add0~65 ) # 
// (!\datapath_0|forward_mux_0|Mux15~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~15_combout ),
	.datab(\datapath_0|forward_mux_0|Mux15~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~65 ),
	.combout(\datapath_0|ALU_0|Add0~66_combout ),
	.cout(\datapath_0|ALU_0|Add0~67 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~66 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~66 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[16] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [16] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [16]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~66_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~66_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [16]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [16]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[16] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[16] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [16]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux15~1 (
// Equation(s):
// \datapath_0|mux_0|Mux15~1_combout  = (\datapath_0|mux_0|Mux15~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~28_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux15~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~28_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux15~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux15~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux15~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux15~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux15~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux15~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [16] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux15~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [16]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux15~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux15~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux15~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux15~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux15~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux15~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux15~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux15~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux15~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]))) # 
// (!\datapath_0|forward_mux_0|Mux15~0_combout  & (\datapath_0|datamem_module_0|output_data [16])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux15~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [16]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux15~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux15~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux15~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux15~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux15~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux15~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux15~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16]),
	.datab(\datapath_0|forward_mux_0|Mux15~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux15~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux15~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux15~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~68 (
// Equation(s):
// \datapath_0|ALU_0|Add0~68_combout  = ((\datapath_0|ALU_0|Add0~14_combout  $ (\datapath_0|forward_mux_0|Mux14~2_combout  $ (!\datapath_0|ALU_0|Add0~67 )))) # (GND)
// \datapath_0|ALU_0|Add0~69  = CARRY((\datapath_0|ALU_0|Add0~14_combout  & ((\datapath_0|forward_mux_0|Mux14~2_combout ) # (!\datapath_0|ALU_0|Add0~67 ))) # (!\datapath_0|ALU_0|Add0~14_combout  & (\datapath_0|forward_mux_0|Mux14~2_combout  & 
// !\datapath_0|ALU_0|Add0~67 )))

	.dataa(\datapath_0|ALU_0|Add0~14_combout ),
	.datab(\datapath_0|forward_mux_0|Mux14~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~67 ),
	.combout(\datapath_0|ALU_0|Add0~68_combout ),
	.cout(\datapath_0|ALU_0|Add0~69 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~68 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~68 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[17] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [17] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [17]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~68_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~68_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [17]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [17]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[17] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[17] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [17]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux14~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux14~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux14~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]))) # 
// (!\datapath_0|forward_mux_0|Mux14~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux14~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux14~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux14~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux14~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux14~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux14~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux14~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux14~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17]),
	.datab(\datapath_0|forward_mux_0|Mux14~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux14~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux14~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux14~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~70 (
// Equation(s):
// \datapath_0|ALU_0|Add0~70_combout  = (\datapath_0|ALU_0|Add0~13_combout  & ((\datapath_0|forward_mux_0|Mux13~2_combout  & (\datapath_0|ALU_0|Add0~69  & VCC)) # (!\datapath_0|forward_mux_0|Mux13~2_combout  & (!\datapath_0|ALU_0|Add0~69 )))) # 
// (!\datapath_0|ALU_0|Add0~13_combout  & ((\datapath_0|forward_mux_0|Mux13~2_combout  & (!\datapath_0|ALU_0|Add0~69 )) # (!\datapath_0|forward_mux_0|Mux13~2_combout  & ((\datapath_0|ALU_0|Add0~69 ) # (GND)))))
// \datapath_0|ALU_0|Add0~71  = CARRY((\datapath_0|ALU_0|Add0~13_combout  & (!\datapath_0|forward_mux_0|Mux13~2_combout  & !\datapath_0|ALU_0|Add0~69 )) # (!\datapath_0|ALU_0|Add0~13_combout  & ((!\datapath_0|ALU_0|Add0~69 ) # 
// (!\datapath_0|forward_mux_0|Mux13~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~13_combout ),
	.datab(\datapath_0|forward_mux_0|Mux13~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~69 ),
	.combout(\datapath_0|ALU_0|Add0~70_combout ),
	.cout(\datapath_0|ALU_0|Add0~71 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~70 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~70 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[18] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [18] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [18]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~70_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~70_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [18]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [18]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[18] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[18] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [18]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux13~1 (
// Equation(s):
// \datapath_0|mux_0|Mux13~1_combout  = (\datapath_0|mux_0|Mux13~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~32_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux13~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~32_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux13~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux13~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux13~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux13~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux13~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux13~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [18] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux13~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [18]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux13~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux13~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux13~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux13~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux13~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux13~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux13~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux13~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux13~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux13~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux13~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]))) # 
// (!\datapath_0|forward_mux_0|Mux13~0_combout  & (\datapath_0|datamem_module_0|output_data [18])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux13~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [18]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux13~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux13~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux13~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux13~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux13~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux13~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux13~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18]),
	.datab(\datapath_0|forward_mux_0|Mux13~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux13~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux13~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux13~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~72 (
// Equation(s):
// \datapath_0|ALU_0|Add0~72_combout  = ((\datapath_0|ALU_0|Add0~12_combout  $ (\datapath_0|forward_mux_0|Mux12~2_combout  $ (!\datapath_0|ALU_0|Add0~71 )))) # (GND)
// \datapath_0|ALU_0|Add0~73  = CARRY((\datapath_0|ALU_0|Add0~12_combout  & ((\datapath_0|forward_mux_0|Mux12~2_combout ) # (!\datapath_0|ALU_0|Add0~71 ))) # (!\datapath_0|ALU_0|Add0~12_combout  & (\datapath_0|forward_mux_0|Mux12~2_combout  & 
// !\datapath_0|ALU_0|Add0~71 )))

	.dataa(\datapath_0|ALU_0|Add0~12_combout ),
	.datab(\datapath_0|forward_mux_0|Mux12~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~71 ),
	.combout(\datapath_0|ALU_0|Add0~72_combout ),
	.cout(\datapath_0|ALU_0|Add0~73 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~72 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~72 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[19] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [19] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [19]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~72_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~72_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [19]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [19]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[19] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[19] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [19]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux12~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux12~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux12~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]))) # 
// (!\datapath_0|forward_mux_0|Mux12~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux12~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux12~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux12~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux12~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux12~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux12~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux12~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux12~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19]),
	.datab(\datapath_0|forward_mux_0|Mux12~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux12~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux12~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux12~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~74 (
// Equation(s):
// \datapath_0|ALU_0|Add0~74_combout  = (\datapath_0|ALU_0|Add0~11_combout  & ((\datapath_0|forward_mux_0|Mux11~2_combout  & (\datapath_0|ALU_0|Add0~73  & VCC)) # (!\datapath_0|forward_mux_0|Mux11~2_combout  & (!\datapath_0|ALU_0|Add0~73 )))) # 
// (!\datapath_0|ALU_0|Add0~11_combout  & ((\datapath_0|forward_mux_0|Mux11~2_combout  & (!\datapath_0|ALU_0|Add0~73 )) # (!\datapath_0|forward_mux_0|Mux11~2_combout  & ((\datapath_0|ALU_0|Add0~73 ) # (GND)))))
// \datapath_0|ALU_0|Add0~75  = CARRY((\datapath_0|ALU_0|Add0~11_combout  & (!\datapath_0|forward_mux_0|Mux11~2_combout  & !\datapath_0|ALU_0|Add0~73 )) # (!\datapath_0|ALU_0|Add0~11_combout  & ((!\datapath_0|ALU_0|Add0~73 ) # 
// (!\datapath_0|forward_mux_0|Mux11~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~11_combout ),
	.datab(\datapath_0|forward_mux_0|Mux11~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~73 ),
	.combout(\datapath_0|ALU_0|Add0~74_combout ),
	.cout(\datapath_0|ALU_0|Add0~75 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~74 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~74 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[20] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [20] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [20]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~74_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~74_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [20]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [20]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[20] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[20] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [20]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux11~1 (
// Equation(s):
// \datapath_0|mux_0|Mux11~1_combout  = (\datapath_0|mux_0|Mux11~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~36_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux11~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~36_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux11~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux11~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux11~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux11~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux11~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux11~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [20] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux11~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [20]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux11~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux11~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux11~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux11~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux11~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux11~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux11~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux11~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux11~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]))) # 
// (!\datapath_0|forward_mux_0|Mux11~0_combout  & (\datapath_0|datamem_module_0|output_data [20])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux11~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [20]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux11~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux11~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux11~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux11~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux11~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux11~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux11~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20]),
	.datab(\datapath_0|forward_mux_0|Mux11~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux11~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux11~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux11~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~76 (
// Equation(s):
// \datapath_0|ALU_0|Add0~76_combout  = ((\datapath_0|ALU_0|Add0~10_combout  $ (\datapath_0|forward_mux_0|Mux10~2_combout  $ (!\datapath_0|ALU_0|Add0~75 )))) # (GND)
// \datapath_0|ALU_0|Add0~77  = CARRY((\datapath_0|ALU_0|Add0~10_combout  & ((\datapath_0|forward_mux_0|Mux10~2_combout ) # (!\datapath_0|ALU_0|Add0~75 ))) # (!\datapath_0|ALU_0|Add0~10_combout  & (\datapath_0|forward_mux_0|Mux10~2_combout  & 
// !\datapath_0|ALU_0|Add0~75 )))

	.dataa(\datapath_0|ALU_0|Add0~10_combout ),
	.datab(\datapath_0|forward_mux_0|Mux10~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~75 ),
	.combout(\datapath_0|ALU_0|Add0~76_combout ),
	.cout(\datapath_0|ALU_0|Add0~77 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~76 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~76 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[21] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [21] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [21]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~76_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~76_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [21]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [21]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[21] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[21] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [21]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux10~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux10~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux10~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]))) # 
// (!\datapath_0|forward_mux_0|Mux10~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux10~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux10~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux10~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux10~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux10~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux10~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux10~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux10~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21]),
	.datab(\datapath_0|forward_mux_0|Mux10~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux10~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux10~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux10~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~78 (
// Equation(s):
// \datapath_0|ALU_0|Add0~78_combout  = (\datapath_0|ALU_0|Add0~9_combout  & ((\datapath_0|forward_mux_0|Mux9~2_combout  & (\datapath_0|ALU_0|Add0~77  & VCC)) # (!\datapath_0|forward_mux_0|Mux9~2_combout  & (!\datapath_0|ALU_0|Add0~77 )))) # 
// (!\datapath_0|ALU_0|Add0~9_combout  & ((\datapath_0|forward_mux_0|Mux9~2_combout  & (!\datapath_0|ALU_0|Add0~77 )) # (!\datapath_0|forward_mux_0|Mux9~2_combout  & ((\datapath_0|ALU_0|Add0~77 ) # (GND)))))
// \datapath_0|ALU_0|Add0~79  = CARRY((\datapath_0|ALU_0|Add0~9_combout  & (!\datapath_0|forward_mux_0|Mux9~2_combout  & !\datapath_0|ALU_0|Add0~77 )) # (!\datapath_0|ALU_0|Add0~9_combout  & ((!\datapath_0|ALU_0|Add0~77 ) # 
// (!\datapath_0|forward_mux_0|Mux9~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~9_combout ),
	.datab(\datapath_0|forward_mux_0|Mux9~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~77 ),
	.combout(\datapath_0|ALU_0|Add0~78_combout ),
	.cout(\datapath_0|ALU_0|Add0~79 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~78 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~78 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[22] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [22] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [22]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~78_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~78_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [22]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [22]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[22] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[22] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [22]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux9~1 (
// Equation(s):
// \datapath_0|mux_0|Mux9~1_combout  = (\datapath_0|mux_0|Mux9~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~40_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux9~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~40_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux9~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux9~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux9~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux9~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux9~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux9~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [22] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux9~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [22]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux9~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux9~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux9~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux9~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux9~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux9~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux9~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux9~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux9~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux9~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]))) # (!\datapath_0|forward_mux_0|Mux9~0_combout  
// & (\datapath_0|datamem_module_0|output_data [22])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux9~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [22]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux9~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux9~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux9~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux9~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux9~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux9~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux9~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22]),
	.datab(\datapath_0|forward_mux_0|Mux9~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux9~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux9~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux9~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~80 (
// Equation(s):
// \datapath_0|ALU_0|Add0~80_combout  = ((\datapath_0|ALU_0|Add0~8_combout  $ (\datapath_0|forward_mux_0|Mux8~2_combout  $ (!\datapath_0|ALU_0|Add0~79 )))) # (GND)
// \datapath_0|ALU_0|Add0~81  = CARRY((\datapath_0|ALU_0|Add0~8_combout  & ((\datapath_0|forward_mux_0|Mux8~2_combout ) # (!\datapath_0|ALU_0|Add0~79 ))) # (!\datapath_0|ALU_0|Add0~8_combout  & (\datapath_0|forward_mux_0|Mux8~2_combout  & 
// !\datapath_0|ALU_0|Add0~79 )))

	.dataa(\datapath_0|ALU_0|Add0~8_combout ),
	.datab(\datapath_0|forward_mux_0|Mux8~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~79 ),
	.combout(\datapath_0|ALU_0|Add0~80_combout ),
	.cout(\datapath_0|ALU_0|Add0~81 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~80 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~80 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[23] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [23] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [23]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~80_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~80_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [23]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [23]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[23] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[23] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [23]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux8~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux8~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux8~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]))) # (!\datapath_0|forward_mux_0|Mux8~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux8~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux8~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux8~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux8~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux8~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux8~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23]),
	.datab(\datapath_0|forward_mux_0|Mux8~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux8~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux8~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux8~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~82 (
// Equation(s):
// \datapath_0|ALU_0|Add0~82_combout  = (\datapath_0|ALU_0|Add0~7_combout  & ((\datapath_0|forward_mux_0|Mux7~2_combout  & (\datapath_0|ALU_0|Add0~81  & VCC)) # (!\datapath_0|forward_mux_0|Mux7~2_combout  & (!\datapath_0|ALU_0|Add0~81 )))) # 
// (!\datapath_0|ALU_0|Add0~7_combout  & ((\datapath_0|forward_mux_0|Mux7~2_combout  & (!\datapath_0|ALU_0|Add0~81 )) # (!\datapath_0|forward_mux_0|Mux7~2_combout  & ((\datapath_0|ALU_0|Add0~81 ) # (GND)))))
// \datapath_0|ALU_0|Add0~83  = CARRY((\datapath_0|ALU_0|Add0~7_combout  & (!\datapath_0|forward_mux_0|Mux7~2_combout  & !\datapath_0|ALU_0|Add0~81 )) # (!\datapath_0|ALU_0|Add0~7_combout  & ((!\datapath_0|ALU_0|Add0~81 ) # 
// (!\datapath_0|forward_mux_0|Mux7~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~7_combout ),
	.datab(\datapath_0|forward_mux_0|Mux7~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~81 ),
	.combout(\datapath_0|ALU_0|Add0~82_combout ),
	.cout(\datapath_0|ALU_0|Add0~83 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~82 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~82 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[24] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [24] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [24]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~82_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~82_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [24]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [24]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[24] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[24] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [24]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux7~1 (
// Equation(s):
// \datapath_0|mux_0|Mux7~1_combout  = (\datapath_0|mux_0|Mux7~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~44_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux7~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~44_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux7~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux7~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux7~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux7~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux7~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [24] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux7~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [24]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux7~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux7~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux7~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux7~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux7~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux7~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux7~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux7~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux7~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]))) # (!\datapath_0|forward_mux_0|Mux7~0_combout  
// & (\datapath_0|datamem_module_0|output_data [24])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux7~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [24]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux7~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux7~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux7~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux7~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux7~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux7~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24]),
	.datab(\datapath_0|forward_mux_0|Mux7~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux7~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux7~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux7~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~84 (
// Equation(s):
// \datapath_0|ALU_0|Add0~84_combout  = ((\datapath_0|ALU_0|Add0~6_combout  $ (\datapath_0|forward_mux_0|Mux6~2_combout  $ (!\datapath_0|ALU_0|Add0~83 )))) # (GND)
// \datapath_0|ALU_0|Add0~85  = CARRY((\datapath_0|ALU_0|Add0~6_combout  & ((\datapath_0|forward_mux_0|Mux6~2_combout ) # (!\datapath_0|ALU_0|Add0~83 ))) # (!\datapath_0|ALU_0|Add0~6_combout  & (\datapath_0|forward_mux_0|Mux6~2_combout  & 
// !\datapath_0|ALU_0|Add0~83 )))

	.dataa(\datapath_0|ALU_0|Add0~6_combout ),
	.datab(\datapath_0|forward_mux_0|Mux6~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~83 ),
	.combout(\datapath_0|ALU_0|Add0~84_combout ),
	.cout(\datapath_0|ALU_0|Add0~85 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~84 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~84 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[25] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [25] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [25]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~84_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~84_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [25]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [25]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[25] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[25] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [25]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux6~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux6~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux6~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]))) # (!\datapath_0|forward_mux_0|Mux6~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux6~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux6~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux6~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux6~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux6~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux6~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux6~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux6~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25]),
	.datab(\datapath_0|forward_mux_0|Mux6~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux6~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux6~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux6~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~86 (
// Equation(s):
// \datapath_0|ALU_0|Add0~86_combout  = (\datapath_0|ALU_0|Add0~5_combout  & ((\datapath_0|forward_mux_0|Mux5~2_combout  & (\datapath_0|ALU_0|Add0~85  & VCC)) # (!\datapath_0|forward_mux_0|Mux5~2_combout  & (!\datapath_0|ALU_0|Add0~85 )))) # 
// (!\datapath_0|ALU_0|Add0~5_combout  & ((\datapath_0|forward_mux_0|Mux5~2_combout  & (!\datapath_0|ALU_0|Add0~85 )) # (!\datapath_0|forward_mux_0|Mux5~2_combout  & ((\datapath_0|ALU_0|Add0~85 ) # (GND)))))
// \datapath_0|ALU_0|Add0~87  = CARRY((\datapath_0|ALU_0|Add0~5_combout  & (!\datapath_0|forward_mux_0|Mux5~2_combout  & !\datapath_0|ALU_0|Add0~85 )) # (!\datapath_0|ALU_0|Add0~5_combout  & ((!\datapath_0|ALU_0|Add0~85 ) # 
// (!\datapath_0|forward_mux_0|Mux5~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~5_combout ),
	.datab(\datapath_0|forward_mux_0|Mux5~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~85 ),
	.combout(\datapath_0|ALU_0|Add0~86_combout ),
	.cout(\datapath_0|ALU_0|Add0~87 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~86 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~86 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[26] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [26] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [26]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~86_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~86_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [26]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [26]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[26] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[26] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [26]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux5~1 (
// Equation(s):
// \datapath_0|mux_0|Mux5~1_combout  = (\datapath_0|mux_0|Mux5~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~48_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux5~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~48_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux5~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux5~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux5~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux5~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux5~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux5~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [26] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux5~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [26]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux5~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux5~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux5~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux5~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux5~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux5~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux5~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux5~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux5~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux5~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux5~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]))) # (!\datapath_0|forward_mux_0|Mux5~0_combout  
// & (\datapath_0|datamem_module_0|output_data [26])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux5~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [26]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux5~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux5~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux5~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux5~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux5~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux5~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux5~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26]),
	.datab(\datapath_0|forward_mux_0|Mux5~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux5~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux5~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux5~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~88 (
// Equation(s):
// \datapath_0|ALU_0|Add0~88_combout  = ((\datapath_0|ALU_0|Add0~4_combout  $ (\datapath_0|forward_mux_0|Mux4~2_combout  $ (!\datapath_0|ALU_0|Add0~87 )))) # (GND)
// \datapath_0|ALU_0|Add0~89  = CARRY((\datapath_0|ALU_0|Add0~4_combout  & ((\datapath_0|forward_mux_0|Mux4~2_combout ) # (!\datapath_0|ALU_0|Add0~87 ))) # (!\datapath_0|ALU_0|Add0~4_combout  & (\datapath_0|forward_mux_0|Mux4~2_combout  & 
// !\datapath_0|ALU_0|Add0~87 )))

	.dataa(\datapath_0|ALU_0|Add0~4_combout ),
	.datab(\datapath_0|forward_mux_0|Mux4~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~87 ),
	.combout(\datapath_0|ALU_0|Add0~88_combout ),
	.cout(\datapath_0|ALU_0|Add0~89 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~88 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~88 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[27] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [27] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [27]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~88_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~88_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [27]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [27]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[27] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[27] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [27]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux4~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux4~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux4~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]))) # (!\datapath_0|forward_mux_0|Mux4~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux4~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux4~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux4~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux4~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux4~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux4~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux4~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux4~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27]),
	.datab(\datapath_0|forward_mux_0|Mux4~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux4~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux4~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux4~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~90 (
// Equation(s):
// \datapath_0|ALU_0|Add0~90_combout  = (\datapath_0|ALU_0|Add0~3_combout  & ((\datapath_0|forward_mux_0|Mux3~2_combout  & (\datapath_0|ALU_0|Add0~89  & VCC)) # (!\datapath_0|forward_mux_0|Mux3~2_combout  & (!\datapath_0|ALU_0|Add0~89 )))) # 
// (!\datapath_0|ALU_0|Add0~3_combout  & ((\datapath_0|forward_mux_0|Mux3~2_combout  & (!\datapath_0|ALU_0|Add0~89 )) # (!\datapath_0|forward_mux_0|Mux3~2_combout  & ((\datapath_0|ALU_0|Add0~89 ) # (GND)))))
// \datapath_0|ALU_0|Add0~91  = CARRY((\datapath_0|ALU_0|Add0~3_combout  & (!\datapath_0|forward_mux_0|Mux3~2_combout  & !\datapath_0|ALU_0|Add0~89 )) # (!\datapath_0|ALU_0|Add0~3_combout  & ((!\datapath_0|ALU_0|Add0~89 ) # 
// (!\datapath_0|forward_mux_0|Mux3~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~3_combout ),
	.datab(\datapath_0|forward_mux_0|Mux3~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~89 ),
	.combout(\datapath_0|ALU_0|Add0~90_combout ),
	.cout(\datapath_0|ALU_0|Add0~91 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~90 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~90 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[28] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [28] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [28]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~90_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~90_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [28]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [28]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[28] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[28] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [28]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux3~1 (
// Equation(s):
// \datapath_0|mux_0|Mux3~1_combout  = (\datapath_0|mux_0|Mux3~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~52_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux3~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~52_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux3~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux3~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux3~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux3~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux3~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [28] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux3~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [28]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux3~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux3~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux3~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux3~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux3~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux3~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux3~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux3~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux3~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]))) # (!\datapath_0|forward_mux_0|Mux3~0_combout  
// & (\datapath_0|datamem_module_0|output_data [28])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux3~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [28]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux3~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux3~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux3~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux3~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux3~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux3~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28]),
	.datab(\datapath_0|forward_mux_0|Mux3~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux3~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux3~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux3~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~92 (
// Equation(s):
// \datapath_0|ALU_0|Add0~92_combout  = ((\datapath_0|ALU_0|Add0~2_combout  $ (\datapath_0|forward_mux_0|Mux2~2_combout  $ (!\datapath_0|ALU_0|Add0~91 )))) # (GND)
// \datapath_0|ALU_0|Add0~93  = CARRY((\datapath_0|ALU_0|Add0~2_combout  & ((\datapath_0|forward_mux_0|Mux2~2_combout ) # (!\datapath_0|ALU_0|Add0~91 ))) # (!\datapath_0|ALU_0|Add0~2_combout  & (\datapath_0|forward_mux_0|Mux2~2_combout  & 
// !\datapath_0|ALU_0|Add0~91 )))

	.dataa(\datapath_0|ALU_0|Add0~2_combout ),
	.datab(\datapath_0|forward_mux_0|Mux2~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~91 ),
	.combout(\datapath_0|ALU_0|Add0~92_combout ),
	.cout(\datapath_0|ALU_0|Add0~93 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~92 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~92 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[29] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [29] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [29]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~92_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~92_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [29]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [29]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[29] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[29] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [29]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux2~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux2~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux2~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]))) # (!\datapath_0|forward_mux_0|Mux2~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux2~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux2~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux2~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux2~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux2~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux2~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux2~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29]),
	.datab(\datapath_0|forward_mux_0|Mux2~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux2~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux2~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux2~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~94 (
// Equation(s):
// \datapath_0|ALU_0|Add0~94_combout  = (\datapath_0|ALU_0|Add0~1_combout  & ((\datapath_0|forward_mux_0|Mux1~2_combout  & (\datapath_0|ALU_0|Add0~93  & VCC)) # (!\datapath_0|forward_mux_0|Mux1~2_combout  & (!\datapath_0|ALU_0|Add0~93 )))) # 
// (!\datapath_0|ALU_0|Add0~1_combout  & ((\datapath_0|forward_mux_0|Mux1~2_combout  & (!\datapath_0|ALU_0|Add0~93 )) # (!\datapath_0|forward_mux_0|Mux1~2_combout  & ((\datapath_0|ALU_0|Add0~93 ) # (GND)))))
// \datapath_0|ALU_0|Add0~95  = CARRY((\datapath_0|ALU_0|Add0~1_combout  & (!\datapath_0|forward_mux_0|Mux1~2_combout  & !\datapath_0|ALU_0|Add0~93 )) # (!\datapath_0|ALU_0|Add0~1_combout  & ((!\datapath_0|ALU_0|Add0~93 ) # 
// (!\datapath_0|forward_mux_0|Mux1~2_combout ))))

	.dataa(\datapath_0|ALU_0|Add0~1_combout ),
	.datab(\datapath_0|forward_mux_0|Mux1~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~93 ),
	.combout(\datapath_0|ALU_0|Add0~94_combout ),
	.cout(\datapath_0|ALU_0|Add0~95 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~94 .lut_mask = 16'h9617;
defparam \datapath_0|ALU_0|Add0~94 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[30] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [30] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [30]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~94_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~94_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [30]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [30]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[30] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[30] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [30]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_0|Mux1~1 (
// Equation(s):
// \datapath_0|mux_0|Mux1~1_combout  = (\datapath_0|mux_0|Mux1~0_combout ) # ((\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|Add1~56_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0])))

	.dataa(\datapath_0|mux_0|Mux1~0_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|Add1~56_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|mux_0|Mux1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_0|Mux1~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|mux_0|Mux1~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x2|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[2]~5_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x2|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x2|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x2|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_1_mux|Mux1~1 (
// Equation(s):
// \datapath_0|register_file_0|output_1_mux|Mux1~1_combout  = (\datapath_0|register_file_0|output_1_mux|Mux1~0_combout ) # ((\datapath_0|register_file_0|reg_x2|internal_value [30] & (\controller_0|internal_reg_file_read_address_0 [1] & 
// !\controller_0|internal_reg_file_read_address_0 [0])))

	.dataa(\datapath_0|register_file_0|output_1_mux|Mux1~0_combout ),
	.datab(\datapath_0|register_file_0|reg_x2|internal_value [30]),
	.datac(\controller_0|internal_reg_file_read_address_0 [1]),
	.datad(\controller_0|internal_reg_file_read_address_0 [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_1_mux|Mux1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_1_mux|Mux1~1 .lut_mask = 16'hAAEA;
defparam \datapath_0|register_file_0|output_1_mux|Mux1~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_1_mux|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux1~0 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux1~0_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30])) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30])))))

	.dataa(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30]),
	.datac(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_0_reg|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux1~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_0|Mux1~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux1~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux1~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & ((\datapath_0|forward_mux_0|Mux1~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]))) # (!\datapath_0|forward_mux_0|Mux1~0_combout  
// & (\datapath_0|datamem_module_0|output_data [30])))) # (!\datapath_0|FU_0|forward_mux_0_control[1]~0_combout  & (((\datapath_0|forward_mux_0|Mux1~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [30]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_0|Mux1~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux1~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux1~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux1~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux1~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux1~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30]),
	.datab(\datapath_0|forward_mux_0|Mux1~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux1~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux1~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~96 (
// Equation(s):
// \datapath_0|ALU_0|Add0~96_combout  = ((\datapath_0|ALU_0|Add0~0_combout  $ (\datapath_0|forward_mux_0|Mux0~2_combout  $ (!\datapath_0|ALU_0|Add0~95 )))) # (GND)
// \datapath_0|ALU_0|Add0~97  = CARRY((\datapath_0|ALU_0|Add0~0_combout  & ((\datapath_0|forward_mux_0|Mux0~2_combout ) # (!\datapath_0|ALU_0|Add0~95 ))) # (!\datapath_0|ALU_0|Add0~0_combout  & (\datapath_0|forward_mux_0|Mux0~2_combout  & 
// !\datapath_0|ALU_0|Add0~95 )))

	.dataa(\datapath_0|ALU_0|Add0~0_combout ),
	.datab(\datapath_0|forward_mux_0|Mux0~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|ALU_0|Add0~95 ),
	.combout(\datapath_0|ALU_0|Add0~96_combout ),
	.cout(\datapath_0|ALU_0|Add0~97 ));
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~96 .lut_mask = 16'h698E;
defparam \datapath_0|ALU_0|Add0~96 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_output[31] (
// Equation(s):
// \datapath_0|ALU_0|ALU_output [31] = (\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & ((\datapath_0|ALU_0|ALU_output [31]))) # (!\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q  & (\datapath_0|ALU_0|Add0~96_combout ))

	.dataa(gnd),
	.datab(\datapath_0|ALU_0|Add0~96_combout ),
	.datac(\datapath_0|ALU_0|ALU_output [31]),
	.datad(\datapath_0|ID_EX_PLR|ALU_branch_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_output [31]),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_output[31] .lut_mask = 16'hF0CC;
defparam \datapath_0|ALU_0|ALU_output[31] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_output [31]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux0~1 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux0~1_combout  = (\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & ((\datapath_0|forward_mux_0|Mux0~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]))) # (!\datapath_0|forward_mux_0|Mux0~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31])))) # (!\datapath_0|FU_0|forward_mux_0_control[0]~1_combout  & (((\datapath_0|forward_mux_0|Mux0~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31]),
	.datab(\datapath_0|FU_0|forward_mux_0_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_0|Mux0~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux0~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_0|Mux0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_0|Mux0~2 (
// Equation(s):
// \datapath_0|forward_mux_0|Mux0~2_combout  = (\datapath_0|forward_mux_0|Mux31~3_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31])) # (!\datapath_0|forward_mux_0|Mux31~3_combout  & ((\datapath_0|forward_mux_0|Mux0~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31]),
	.datab(\datapath_0|forward_mux_0|Mux0~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_0|Mux31~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_0|Mux0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_0|Mux0~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_0|Mux0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|Add0~98 (
// Equation(s):
// \datapath_0|ALU_0|Add0~98_combout  = \datapath_0|ALU_0|Add0~0_combout  $ (\datapath_0|forward_mux_0|Mux0~2_combout  $ (\datapath_0|ALU_0|Add0~97 ))

	.dataa(\datapath_0|ALU_0|Add0~0_combout ),
	.datab(\datapath_0|forward_mux_0|Mux0~2_combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(\datapath_0|ALU_0|Add0~97 ),
	.combout(\datapath_0|ALU_0|Add0~98_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|Add0~98 .lut_mask = 16'h9696;
defparam \datapath_0|ALU_0|Add0~98 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~0 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~0_combout  = (!\datapath_0|ALU_0|Add0~88_combout  & (!\datapath_0|ALU_0|Add0~90_combout  & (!\datapath_0|ALU_0|Add0~92_combout  & !\datapath_0|ALU_0|Add0~94_combout )))

	.dataa(\datapath_0|ALU_0|Add0~88_combout ),
	.datab(\datapath_0|ALU_0|Add0~90_combout ),
	.datac(\datapath_0|ALU_0|Add0~92_combout ),
	.datad(\datapath_0|ALU_0|Add0~94_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~0 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~1 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~1_combout  = (!\datapath_0|ALU_0|Add0~80_combout  & (!\datapath_0|ALU_0|Add0~82_combout  & (!\datapath_0|ALU_0|Add0~84_combout  & !\datapath_0|ALU_0|Add0~86_combout )))

	.dataa(\datapath_0|ALU_0|Add0~80_combout ),
	.datab(\datapath_0|ALU_0|Add0~82_combout ),
	.datac(\datapath_0|ALU_0|Add0~84_combout ),
	.datad(\datapath_0|ALU_0|Add0~86_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~1 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~7 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~7_combout  = (!\datapath_0|ALU_0|Add0~64_combout  & (!\datapath_0|ALU_0|Add0~66_combout  & (!\datapath_0|ALU_0|Add0~68_combout  & !\datapath_0|ALU_0|Add0~70_combout )))

	.dataa(\datapath_0|ALU_0|Add0~64_combout ),
	.datab(\datapath_0|ALU_0|Add0~66_combout ),
	.datac(\datapath_0|ALU_0|Add0~68_combout ),
	.datad(\datapath_0|ALU_0|Add0~70_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~7 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~8 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~8_combout  = (!\datapath_0|ALU_0|Add0~72_combout  & (!\datapath_0|ALU_0|Add0~74_combout  & (!\datapath_0|ALU_0|Add0~76_combout  & !\datapath_0|ALU_0|Add0~78_combout )))

	.dataa(\datapath_0|ALU_0|Add0~72_combout ),
	.datab(\datapath_0|ALU_0|Add0~74_combout ),
	.datac(\datapath_0|ALU_0|Add0~76_combout ),
	.datad(\datapath_0|ALU_0|Add0~78_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~8 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~8 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|comb~0 (
// Equation(s):
// \datapath_0|comb~0_combout  = (\datapath_0|ALU_0|ALU_branch_response~6_combout  & (\datapath_0|ALU_0|ALU_branch_response~7_combout  & \datapath_0|ALU_0|ALU_branch_response~8_combout ))

	.dataa(\datapath_0|ALU_0|ALU_branch_response~6_combout ),
	.datab(\datapath_0|ALU_0|ALU_branch_response~7_combout ),
	.datac(\datapath_0|ALU_0|ALU_branch_response~8_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|comb~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|comb~0 .lut_mask = 16'h8080;
defparam \datapath_0|comb~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|comb~1 (
// Equation(s):
// \datapath_0|comb~1_combout  = (!\datapath_0|ALU_0|Add0~96_combout  & (\datapath_0|ALU_0|ALU_branch_response~1_combout  & \datapath_0|comb~0_combout ))

	.dataa(\datapath_0|ALU_0|Add0~96_combout ),
	.datab(\datapath_0|ALU_0|ALU_branch_response~1_combout ),
	.datac(\datapath_0|comb~0_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|comb~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|comb~1 .lut_mask = 16'h4040;
defparam \datapath_0|comb~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|comb~2 (
// Equation(s):
// \datapath_0|comb~2_combout  = (\datapath_0|ID_EX_PLR|jump_flag_reg|reg_out~q ) # ((!\datapath_0|ALU_0|Add0~98_combout  & (\datapath_0|ALU_0|ALU_branch_response~0_combout  & \datapath_0|comb~1_combout )))

	.dataa(\datapath_0|ID_EX_PLR|jump_flag_reg|reg_out~q ),
	.datab(\datapath_0|ALU_0|Add0~98_combout ),
	.datac(\datapath_0|ALU_0|ALU_branch_response~0_combout ),
	.datad(\datapath_0|comb~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|comb~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|comb~2 .lut_mask = 16'hBAAA;
defparam \datapath_0|comb~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[5]~36_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~10_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[6]~38 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[6]~38_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [6] & (\datapath_0|program_counter_0|internal_register|internal_value[5]~37  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [6] & (!\datapath_0|program_counter_0|internal_register|internal_value[5]~37  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[6]~39  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [6] & !\datapath_0|program_counter_0|internal_register|internal_value[5]~37 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[5]~37 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[6]~38_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[6]~39 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[6]~38 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[6]~38 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [5]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~12 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~12_combout  = ((\datapath_0|JTU_0|internal_mux|output_0[6]~6_combout  $ (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6] $ (!\datapath_0|JTU_0|internal_adder|Add0~11 )))) # (GND)
// \datapath_0|JTU_0|internal_adder|Add0~13  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[6]~6_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]) # (!\datapath_0|JTU_0|internal_adder|Add0~11 ))) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[6]~6_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6] & !\datapath_0|JTU_0|internal_adder|Add0~11 )))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[6]~6_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~11 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~12_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~13 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~12 .lut_mask = 16'h698E;
defparam \datapath_0|JTU_0|internal_adder|Add0~12 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[6]~38_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~12_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & (!\datapath_0|program_counter_0|internal_register|internal_value [5] & 
// !\datapath_0|program_counter_0|internal_register|internal_value [6]))

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(gnd),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0 .lut_mask = 16'h000A;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [3] & (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [4]) # (!\datapath_0|program_counter_0|internal_register|internal_value [2]))))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datab(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0 .lut_mask = 16'h0888;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux10~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector29~0 (
// Equation(s):
// \controller_0|Selector29~0_combout  = (\controller_0|decoded_cluster.LUI_1810~combout ) # ((\controller_0|decoded_cluster.AUIPC_1816~combout ) # ((\controller_0|decoded_cluster.OP_1834~combout ) # (\controller_0|decoded_cluster.INVALID_1924~combout )))

	.dataa(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datab(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datac(\controller_0|decoded_cluster.OP_1834~combout ),
	.datad(\controller_0|decoded_cluster.INVALID_1924~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector29~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector29~0 .lut_mask = 16'hFFFE;
defparam \controller_0|Selector29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector29~1 (
// Equation(s):
// \controller_0|Selector29~1_combout  = (\controller_0|decoded_cluster.STORE_1912~combout  & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8])) # (!\controller_0|decoded_cluster.STORE_1912~combout  & 
// (((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21] & !\controller_0|Selector29~0_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [8]),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21]),
	.datad(\controller_0|Selector29~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector29~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector29~1 .lut_mask = 16'h88B8;
defparam \controller_0|Selector29~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector29~2 (
// Equation(s):
// \controller_0|Selector29~2_combout  = (\controller_0|decoded_cluster.BRANCH_1900~combout  & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23])) # (!\controller_0|decoded_cluster.BRANCH_1900~combout  & ((\controller_0|Selector29~1_combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(\controller_0|Selector29~1_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector29~2_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector29~2 .lut_mask = 16'hB8B8;
defparam \controller_0|Selector29~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[1] (
// Equation(s):
// \controller_0|internal_immediate [1] = (\controller_0|WideNor1~combout  & (\controller_0|Selector29~2_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [1])))

	.dataa(gnd),
	.datab(\controller_0|Selector29~2_combout ),
	.datac(\controller_0|internal_immediate [1]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [1]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[1] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~4 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~4_combout  = ((\datapath_0|JTU_0|internal_mux|output_0[2]~2_combout  $ (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2] $ (!\datapath_0|JTU_0|internal_adder|Add0~3 )))) # (GND)
// \datapath_0|JTU_0|internal_adder|Add0~5  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[2]~2_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]) # (!\datapath_0|JTU_0|internal_adder|Add0~3 ))) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[2]~2_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2] & !\datapath_0|JTU_0|internal_adder|Add0~3 )))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[2]~2_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~3 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~4_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~5 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~4 .lut_mask = 16'h698E;
defparam \datapath_0|JTU_0|internal_adder|Add0~4 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[2]~30_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~4_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [5]) # ((\datapath_0|program_counter_0|internal_register|internal_value [6]) # 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [3] & !\datapath_0|program_counter_0|internal_register|internal_value [4])))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0 .lut_mask = 16'hEEEF;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & (!\datapath_0|program_counter_0|internal_register|internal_value [2] & 
// !\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ))

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(gnd),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datad(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0 .lut_mask = 16'h000A;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux21~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector30~0 (
// Equation(s):
// \controller_0|Selector30~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & ((\controller_0|decoded_cluster.BRANCH_1900~combout ) # ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10] & 
// \controller_0|decoded_cluster.STORE_1912~combout )))) # (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10] & (\controller_0|decoded_cluster.STORE_1912~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [10]),
	.datac(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datad(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector30~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector30~0 .lut_mask = 16'hEAC0;
defparam \controller_0|Selector30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[2] (
// Equation(s):
// \controller_0|internal_immediate [2] = (\controller_0|WideNor1~combout  & (\controller_0|Selector30~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [2])))

	.dataa(gnd),
	.datab(\controller_0|Selector30~0_combout ),
	.datac(\controller_0|internal_immediate [2]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [2]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[2] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[2] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [2]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[3]~32_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~6_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0_combout  = (!\datapath_0|program_counter_0|internal_register|internal_value [5] & (!\datapath_0|program_counter_0|internal_register|internal_value [6] & 
// ((\datapath_0|program_counter_0|internal_register|internal_value [2]) # (\datapath_0|program_counter_0|internal_register|internal_value [4]))))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0 .lut_mask = 16'h000E;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & ((\datapath_0|program_counter_0|internal_register|internal_value [3]) # 
// (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0_combout )))

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~0_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1 .lut_mask = 16'hA8A8;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Equal0~0 (
// Equation(s):
// \controller_0|Equal0~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [0]) # (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [1])

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [0]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [1]),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Equal0~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Equal0~0 .lut_mask = 16'hEEEE;
defparam \controller_0|Equal0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.JALR_1876 (
// Equation(s):
// \controller_0|decoded_cluster.JALR_1876~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.JALR_1876~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux25~0_combout ))))

	.dataa(\controller_0|Mux25~0_combout ),
	.datab(\controller_0|decoded_cluster.JALR_1876~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.JALR_1876~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.JALR_1876 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.JALR_1876 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate~0 (
// Equation(s):
// \controller_0|internal_immediate~0_combout  = (\controller_0|decoded_cluster.JAL_1846~combout ) # (\controller_0|decoded_cluster.JALR_1876~combout )

	.dataa(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datab(\controller_0|decoded_cluster.JALR_1876~combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|internal_immediate~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate~0 .lut_mask = 16'hEEEE;
defparam \controller_0|internal_immediate~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_mux0_sel[1] (
// Equation(s):
// \controller_0|internal_mux0_sel [1] = (\controller_0|WideNor1~combout  & (\controller_0|internal_immediate~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_mux0_sel [1])))

	.dataa(gnd),
	.datab(\controller_0|internal_immediate~0_combout ),
	.datac(\controller_0|internal_mux0_sel [1]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_mux0_sel [1]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_mux0_sel[1] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_mux0_sel[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|jump_flag_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_mux0_sel [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|jump_flag_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|jump_flag_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|jump_flag_reg|reg_out .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\datapath_0|ID_EX_PLR|jump_flag_reg|reg_out~q ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~3 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~3_combout  = (!\datapath_0|ALU_0|Add0~40_combout  & (!\datapath_0|ALU_0|Add0~42_combout  & (!\datapath_0|ALU_0|Add0~44_combout  & !\datapath_0|ALU_0|Add0~46_combout )))

	.dataa(\datapath_0|ALU_0|Add0~40_combout ),
	.datab(\datapath_0|ALU_0|Add0~42_combout ),
	.datac(\datapath_0|ALU_0|Add0~44_combout ),
	.datad(\datapath_0|ALU_0|Add0~46_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~3 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~4 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~4_combout  = (!\datapath_0|ALU_0|Add0~48_combout  & (!\datapath_0|ALU_0|Add0~50_combout  & (!\datapath_0|ALU_0|Add0~52_combout  & !\datapath_0|ALU_0|Add0~54_combout )))

	.dataa(\datapath_0|ALU_0|Add0~48_combout ),
	.datab(\datapath_0|ALU_0|Add0~50_combout ),
	.datac(\datapath_0|ALU_0|Add0~52_combout ),
	.datad(\datapath_0|ALU_0|Add0~54_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~4 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~5 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~5_combout  = (!\datapath_0|ALU_0|Add0~56_combout  & (!\datapath_0|ALU_0|Add0~58_combout  & (!\datapath_0|ALU_0|Add0~60_combout  & !\datapath_0|ALU_0|Add0~62_combout )))

	.dataa(\datapath_0|ALU_0|Add0~56_combout ),
	.datab(\datapath_0|ALU_0|Add0~58_combout ),
	.datac(\datapath_0|ALU_0|Add0~60_combout ),
	.datad(\datapath_0|ALU_0|Add0~62_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~5 .lut_mask = 16'h0001;
defparam \datapath_0|ALU_0|ALU_branch_response~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~6 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~6_combout  = (\datapath_0|ALU_0|ALU_branch_response~2_combout  & (\datapath_0|ALU_0|ALU_branch_response~3_combout  & (\datapath_0|ALU_0|ALU_branch_response~4_combout  & \datapath_0|ALU_0|ALU_branch_response~5_combout 
// )))

	.dataa(\datapath_0|ALU_0|ALU_branch_response~2_combout ),
	.datab(\datapath_0|ALU_0|ALU_branch_response~3_combout ),
	.datac(\datapath_0|ALU_0|ALU_branch_response~4_combout ),
	.datad(\datapath_0|ALU_0|ALU_branch_response~5_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~6 .lut_mask = 16'h8000;
defparam \datapath_0|ALU_0|ALU_branch_response~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~9 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~9_combout  = (\datapath_0|ALU_0|ALU_branch_response~7_combout  & (\datapath_0|ALU_0|ALU_branch_response~8_combout  & (\datapath_0|ALU_0|ALU_branch_response~1_combout  & \datapath_0|ALU_0|ALU_branch_response~0_combout 
// )))

	.dataa(\datapath_0|ALU_0|ALU_branch_response~7_combout ),
	.datab(\datapath_0|ALU_0|ALU_branch_response~8_combout ),
	.datac(\datapath_0|ALU_0|ALU_branch_response~1_combout ),
	.datad(\datapath_0|ALU_0|ALU_branch_response~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~9 .lut_mask = 16'h8000;
defparam \datapath_0|ALU_0|ALU_branch_response~9 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|ALU_0|ALU_branch_response~10 (
// Equation(s):
// \datapath_0|ALU_0|ALU_branch_response~10_combout  = (!\datapath_0|ALU_0|Add0~96_combout  & (!\datapath_0|ALU_0|Add0~98_combout  & (\datapath_0|ALU_0|ALU_branch_response~6_combout  & \datapath_0|ALU_0|ALU_branch_response~9_combout )))

	.dataa(\datapath_0|ALU_0|Add0~96_combout ),
	.datab(\datapath_0|ALU_0|Add0~98_combout ),
	.datac(\datapath_0|ALU_0|ALU_branch_response~6_combout ),
	.datad(\datapath_0|ALU_0|ALU_branch_response~9_combout ),
	.cin(gnd),
	.combout(\datapath_0|ALU_0|ALU_branch_response~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|ALU_0|ALU_branch_response~10 .lut_mask = 16'h1000;
defparam \datapath_0|ALU_0|ALU_branch_response~10 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\datapath_0|ALU_0|ALU_branch_response~10_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|comb~3 (
// Equation(s):
// \datapath_0|comb~3_combout  = (\reset~input_o ) # ((\clock~input_o  & ((\datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out~q ) # (\datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out~q ))))

	.dataa(\reset~input_o ),
	.datab(\clock~input_o ),
	.datac(\datapath_0|EX_MEM_PLR|jump_flag_reg|reg_out~q ),
	.datad(\datapath_0|EX_MEM_PLR|ALU_branch_respose_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|comb~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|comb~3 .lut_mask = 16'hEEEA;
defparam \datapath_0|comb~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~2_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0_combout  = (!\datapath_0|program_counter_0|internal_register|internal_value [5] & ((\datapath_0|program_counter_0|internal_register|internal_value [2] & 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [4]) # (!\datapath_0|program_counter_0|internal_register|internal_value [3]))) # (!\datapath_0|program_counter_0|internal_register|internal_value [2] & 
// ((\datapath_0|program_counter_0|internal_register|internal_value [3]) # (\datapath_0|program_counter_0|internal_register|internal_value [4])))))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0 .lut_mask = 16'h007E;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & ((\datapath_0|program_counter_0|internal_register|internal_value [6]) # 
// (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0_combout )))

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.datac(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~0_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1 .lut_mask = 16'hA8A8;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Mux42~0 (
// Equation(s):
// \controller_0|Mux42~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2] & (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3] & \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.datab(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [3]),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [4]),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Mux42~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Mux42~0 .lut_mask = 16'h8080;
defparam \controller_0|Mux42~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.STORE_1912 (
// Equation(s):
// \controller_0|decoded_cluster.STORE_1912~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.STORE_1912~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux23~0_combout ))))

	.dataa(\controller_0|Mux23~0_combout ),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.STORE_1912~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.STORE_1912 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.STORE_1912 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0_combout  = (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & (!\datapath_0|program_counter_0|internal_register|internal_value [3] & 
// ((\datapath_0|program_counter_0|internal_register|internal_value [2]) # (\datapath_0|program_counter_0|internal_register|internal_value [4]))))

	.dataa(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0 .lut_mask = 16'h00A8;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux11~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector27~1 (
// Equation(s):
// \controller_0|Selector27~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & ((\controller_0|decoded_cluster.STORE_1912~combout ) # ((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20] & 
// !\controller_0|Selector27~0_combout )))) # (!\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & (((\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20] & !\controller_0|Selector27~0_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.datab(\controller_0|decoded_cluster.STORE_1912~combout ),
	.datac(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.datad(\controller_0|Selector27~0_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector27~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector27~1 .lut_mask = 16'h88F8;
defparam \controller_0|Selector27~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[0] (
// Equation(s):
// \controller_0|internal_immediate [0] = (\controller_0|WideNor1~combout  & (\controller_0|Selector27~1_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [0])))

	.dataa(gnd),
	.datab(\controller_0|Selector27~1_combout ),
	.datac(\controller_0|internal_immediate [0]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [0]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[0] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|JTU_0|internal_adder|Add0~0_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|comb~2_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[7]~40 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[7]~40_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [7] & (!\datapath_0|program_counter_0|internal_register|internal_value[6]~39 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [7] & ((\datapath_0|program_counter_0|internal_register|internal_value[6]~39 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[7]~41  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[6]~39 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [7]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [7]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[6]~39 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[7]~40_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[7]~41 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[7]~40 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[7]~40 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~14 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~14_combout  = (\datapath_0|JTU_0|internal_mux|output_0[7]~7_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~13 )) # (!\datapath_0|JTU_0|internal_mux|output_0[7]~7_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~13 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~15  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~13 ) # (!\datapath_0|JTU_0|internal_mux|output_0[7]~7_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[7]~7_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~13 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~14_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~15 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~14 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~14 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[7]~40_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~14_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[8]~42 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[8]~42_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [8] & (\datapath_0|program_counter_0|internal_register|internal_value[7]~41  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [8] & (!\datapath_0|program_counter_0|internal_register|internal_value[7]~41  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[8]~43  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [8] & !\datapath_0|program_counter_0|internal_register|internal_value[7]~41 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [8]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[7]~41 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[8]~42_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[8]~43 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[8]~42 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[8]~42 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~16 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~16_combout  = (\datapath_0|JTU_0|internal_mux|output_0[8]~8_combout  & (\datapath_0|JTU_0|internal_adder|Add0~15  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[8]~8_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~15  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~17  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[8]~8_combout  & !\datapath_0|JTU_0|internal_adder|Add0~15 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[8]~8_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~15 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~16_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~17 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~16 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~16 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[8]~42_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~16_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[9]~44 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[9]~44_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [9] & (!\datapath_0|program_counter_0|internal_register|internal_value[8]~43 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [9] & ((\datapath_0|program_counter_0|internal_register|internal_value[8]~43 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[9]~45  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[8]~43 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [9]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [9]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[8]~43 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[9]~44_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[9]~45 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[9]~44 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[9]~44 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~18 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~18_combout  = (\datapath_0|JTU_0|internal_mux|output_0[9]~9_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~17 )) # (!\datapath_0|JTU_0|internal_mux|output_0[9]~9_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~17 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~19  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~17 ) # (!\datapath_0|JTU_0|internal_mux|output_0[9]~9_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[9]~9_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~17 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~18_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~19 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~18 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~18 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[9]~44_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~18_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[10]~46 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[10]~46_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [10] & (\datapath_0|program_counter_0|internal_register|internal_value[9]~45  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [10] & (!\datapath_0|program_counter_0|internal_register|internal_value[9]~45  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[10]~47  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [10] & !\datapath_0|program_counter_0|internal_register|internal_value[9]~45 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [10]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[9]~45 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[10]~46_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[10]~47 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[10]~46 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[10]~46 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~20 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~20_combout  = (\datapath_0|JTU_0|internal_mux|output_0[10]~10_combout  & (\datapath_0|JTU_0|internal_adder|Add0~19  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[10]~10_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~19  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~21  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[10]~10_combout  & !\datapath_0|JTU_0|internal_adder|Add0~19 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[10]~10_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~19 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~20_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~21 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~20 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~20 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[10]~46_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~20_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[11]~48 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[11]~48_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [11] & (!\datapath_0|program_counter_0|internal_register|internal_value[10]~47 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [11] & ((\datapath_0|program_counter_0|internal_register|internal_value[10]~47 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[11]~49  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[10]~47 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [11]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [11]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[10]~47 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[11]~48_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[11]~49 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[11]~48 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[11]~48 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|decoded_cluster.JAL_1846 (
// Equation(s):
// \controller_0|decoded_cluster.JAL_1846~combout  = (\controller_0|Equal0~0_combout  & ((\controller_0|Mux42~0_combout  & ((\controller_0|decoded_cluster.JAL_1846~combout ))) # (!\controller_0|Mux42~0_combout  & (\controller_0|Mux31~1_combout ))))

	.dataa(\controller_0|Mux31~1_combout ),
	.datab(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datac(\controller_0|Mux42~0_combout ),
	.datad(\controller_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\controller_0|decoded_cluster.JAL_1846~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|decoded_cluster.JAL_1846 .lut_mask = 16'hCA00;
defparam \controller_0|decoded_cluster.JAL_1846 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector49~0 (
// Equation(s):
// \controller_0|Selector49~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20] & \controller_0|decoded_cluster.JAL_1846~combout )

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.datab(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector49~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector49~0 .lut_mask = 16'h8888;
defparam \controller_0|Selector49~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[11] (
// Equation(s):
// \controller_0|internal_immediate [11] = (\controller_0|WideNor1~combout  & (\controller_0|Selector49~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [11])))

	.dataa(gnd),
	.datab(\controller_0|Selector49~0_combout ),
	.datac(\controller_0|internal_immediate [11]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [11]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[11] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[11] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [11]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~22 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~22_combout  = (\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11] & (\datapath_0|JTU_0|internal_adder|Add0~21  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11] & (!\datapath_0|JTU_0|internal_adder|Add0~21 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~21 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11] & ((\datapath_0|JTU_0|internal_adder|Add0~21 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~23  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11] & !\datapath_0|JTU_0|internal_adder|Add0~21 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~21 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[11]~11_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~21 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~22_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~23 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~22 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~22 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[11]~48_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~22_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[12]~50 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[12]~50_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [12] & (\datapath_0|program_counter_0|internal_register|internal_value[11]~49  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [12] & (!\datapath_0|program_counter_0|internal_register|internal_value[11]~49  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[12]~51  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [12] & !\datapath_0|program_counter_0|internal_register|internal_value[11]~49 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [12]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[11]~49 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[12]~50_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[12]~51 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[12]~50 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[12]~50 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~24 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~24_combout  = (\datapath_0|JTU_0|internal_mux|output_0[12]~12_combout  & (\datapath_0|JTU_0|internal_adder|Add0~23  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[12]~12_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~23  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~25  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[12]~12_combout  & !\datapath_0|JTU_0|internal_adder|Add0~23 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[12]~12_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~23 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~24_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~25 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~24 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~24 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[12]~50_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~24_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[13]~52 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[13]~52_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [13] & (!\datapath_0|program_counter_0|internal_register|internal_value[12]~51 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [13] & ((\datapath_0|program_counter_0|internal_register|internal_value[12]~51 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[13]~53  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[12]~51 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [13]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [13]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[12]~51 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[13]~52_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[13]~53 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[13]~52 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[13]~52 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector30~1 (
// Equation(s):
// \controller_0|Selector30~1_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7] & \controller_0|decoded_cluster.BRANCH_1900~combout )

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [7]),
	.datab(\controller_0|decoded_cluster.BRANCH_1900~combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector30~1_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector30~1 .lut_mask = 16'h8888;
defparam \controller_0|Selector30~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[13] (
// Equation(s):
// \controller_0|internal_immediate [13] = (\controller_0|WideNor1~combout  & (\controller_0|Selector30~1_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [13])))

	.dataa(gnd),
	.datab(\controller_0|Selector30~1_combout ),
	.datac(\controller_0|internal_immediate [13]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [13]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[13] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[13] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [13]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~26 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~26_combout  = (\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13] & (\datapath_0|JTU_0|internal_adder|Add0~25  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13] & (!\datapath_0|JTU_0|internal_adder|Add0~25 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~25 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13] & ((\datapath_0|JTU_0|internal_adder|Add0~25 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~27  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13] & !\datapath_0|JTU_0|internal_adder|Add0~25 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~25 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[13]~13_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~25 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~26_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~27 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~26 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~26 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[13]~52_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~26_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[14]~54 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[14]~54_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [14] & (\datapath_0|program_counter_0|internal_register|internal_value[13]~53  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [14] & (!\datapath_0|program_counter_0|internal_register|internal_value[13]~53  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[14]~55  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [14] & !\datapath_0|program_counter_0|internal_register|internal_value[13]~53 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [14]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[13]~53 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[14]~54_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[14]~55 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[14]~54 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[14]~54 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~28 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~28_combout  = (\datapath_0|JTU_0|internal_mux|output_0[14]~14_combout  & (\datapath_0|JTU_0|internal_adder|Add0~27  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[14]~14_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~27  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~29  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[14]~14_combout  & !\datapath_0|JTU_0|internal_adder|Add0~27 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[14]~14_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~27 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~28_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~29 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~28 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~28 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[14]~54_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~28_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[15]~56 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[15]~56_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [15] & (!\datapath_0|program_counter_0|internal_register|internal_value[14]~55 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [15] & ((\datapath_0|program_counter_0|internal_register|internal_value[14]~55 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[15]~57  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[14]~55 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [15]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [15]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[14]~55 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[15]~56_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[15]~57 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[15]~56 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[15]~56 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector56~0 (
// Equation(s):
// \controller_0|Selector56~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15] & ((\controller_0|decoded_cluster.JAL_1846~combout ) # ((\controller_0|decoded_cluster.LUI_1810~combout ) # 
// (\controller_0|decoded_cluster.AUIPC_1816~combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15]),
	.datab(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datac(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datad(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector56~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector56~0 .lut_mask = 16'hAAA8;
defparam \controller_0|Selector56~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[15] (
// Equation(s):
// \controller_0|internal_immediate [15] = (\controller_0|WideNor1~combout  & (\controller_0|Selector56~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [15])))

	.dataa(gnd),
	.datab(\controller_0|Selector56~0_combout ),
	.datac(\controller_0|internal_immediate [15]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [15]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[15] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[15] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [15]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~30 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~30_combout  = (\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15] & (\datapath_0|JTU_0|internal_adder|Add0~29  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15] & (!\datapath_0|JTU_0|internal_adder|Add0~29 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~29 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15] & ((\datapath_0|JTU_0|internal_adder|Add0~29 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~31  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15] & !\datapath_0|JTU_0|internal_adder|Add0~29 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~29 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[15]~15_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~29 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~30_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~31 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~30 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~30 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[15]~56_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~30_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[16]~58 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[16]~58_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [16] & (\datapath_0|program_counter_0|internal_register|internal_value[15]~57  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [16] & (!\datapath_0|program_counter_0|internal_register|internal_value[15]~57  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[16]~59  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [16] & !\datapath_0|program_counter_0|internal_register|internal_value[15]~57 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [16]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[15]~57 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[16]~58_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[16]~59 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[16]~58 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[16]~58 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector57~0 (
// Equation(s):
// \controller_0|Selector57~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16] & ((\controller_0|decoded_cluster.JAL_1846~combout ) # ((\controller_0|decoded_cluster.LUI_1810~combout ) # 
// (\controller_0|decoded_cluster.AUIPC_1816~combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16]),
	.datab(\controller_0|decoded_cluster.JAL_1846~combout ),
	.datac(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datad(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.cin(gnd),
	.combout(\controller_0|Selector57~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector57~0 .lut_mask = 16'hAAA8;
defparam \controller_0|Selector57~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[16] (
// Equation(s):
// \controller_0|internal_immediate [16] = (\controller_0|WideNor1~combout  & (\controller_0|Selector57~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [16])))

	.dataa(gnd),
	.datab(\controller_0|Selector57~0_combout ),
	.datac(\controller_0|internal_immediate [16]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [16]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[16] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[16] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [16]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~32 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~32_combout  = ((\datapath_0|JTU_0|internal_mux|output_0[16]~16_combout  $ (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16] $ (!\datapath_0|JTU_0|internal_adder|Add0~31 )))) # (GND)
// \datapath_0|JTU_0|internal_adder|Add0~33  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[16]~16_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]) # (!\datapath_0|JTU_0|internal_adder|Add0~31 ))) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[16]~16_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16] & !\datapath_0|JTU_0|internal_adder|Add0~31 )))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[16]~16_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~31 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~32_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~33 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~32 .lut_mask = 16'h698E;
defparam \datapath_0|JTU_0|internal_adder|Add0~32 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[16]~58_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~32_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[17]~60 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[17]~60_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [17] & (!\datapath_0|program_counter_0|internal_register|internal_value[16]~59 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [17] & ((\datapath_0|program_counter_0|internal_register|internal_value[16]~59 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[17]~61  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[16]~59 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [17]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [17]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[16]~59 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[17]~60_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[17]~61 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[17]~60 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[17]~60 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~34 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~34_combout  = (\datapath_0|JTU_0|internal_mux|output_0[17]~17_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~33 )) # (!\datapath_0|JTU_0|internal_mux|output_0[17]~17_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~33 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~35  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~33 ) # (!\datapath_0|JTU_0|internal_mux|output_0[17]~17_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[17]~17_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~33 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~34_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~35 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~34 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~34 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[17]~60_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~34_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[18]~62 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[18]~62_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [18] & (\datapath_0|program_counter_0|internal_register|internal_value[17]~61  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [18] & (!\datapath_0|program_counter_0|internal_register|internal_value[17]~61  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[18]~63  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [18] & !\datapath_0|program_counter_0|internal_register|internal_value[17]~61 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [18]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[17]~61 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[18]~62_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[18]~63 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[18]~62 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[18]~62 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~36 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~36_combout  = (\datapath_0|JTU_0|internal_mux|output_0[18]~18_combout  & (\datapath_0|JTU_0|internal_adder|Add0~35  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[18]~18_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~35  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~37  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[18]~18_combout  & !\datapath_0|JTU_0|internal_adder|Add0~35 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[18]~18_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~35 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~36_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~37 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~36 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~36 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[18]~62_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~36_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[19]~64 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[19]~64_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [19] & (!\datapath_0|program_counter_0|internal_register|internal_value[18]~63 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [19] & ((\datapath_0|program_counter_0|internal_register|internal_value[18]~63 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[19]~65  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[18]~63 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [19]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [19]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[18]~63 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[19]~64_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[19]~65 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[19]~64 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[19]~64 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~38 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~38_combout  = (\datapath_0|JTU_0|internal_mux|output_0[19]~19_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~37 )) # (!\datapath_0|JTU_0|internal_mux|output_0[19]~19_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~37 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~39  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~37 ) # (!\datapath_0|JTU_0|internal_mux|output_0[19]~19_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[19]~19_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~37 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~38_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~39 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~38 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~38 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[19]~64_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~38_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[20]~66 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[20]~66_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [20] & (\datapath_0|program_counter_0|internal_register|internal_value[19]~65  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [20] & (!\datapath_0|program_counter_0|internal_register|internal_value[19]~65  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[20]~67  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [20] & !\datapath_0|program_counter_0|internal_register|internal_value[19]~65 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [20]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[19]~65 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[20]~66_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[20]~67 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[20]~66 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[20]~66 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector62~0 (
// Equation(s):
// \controller_0|Selector62~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20] & ((\controller_0|decoded_cluster.LUI_1810~combout ) # (\controller_0|decoded_cluster.AUIPC_1816~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.datab(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datac(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector62~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector62~0 .lut_mask = 16'hA8A8;
defparam \controller_0|Selector62~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[20] (
// Equation(s):
// \controller_0|internal_immediate [20] = (\controller_0|WideNor1~combout  & (\controller_0|Selector62~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [20])))

	.dataa(gnd),
	.datab(\controller_0|Selector62~0_combout ),
	.datac(\controller_0|internal_immediate [20]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [20]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[20] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[20] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [20]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~40 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~40_combout  = ((\datapath_0|JTU_0|internal_mux|output_0[20]~20_combout  $ (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20] $ (!\datapath_0|JTU_0|internal_adder|Add0~39 )))) # (GND)
// \datapath_0|JTU_0|internal_adder|Add0~41  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[20]~20_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]) # (!\datapath_0|JTU_0|internal_adder|Add0~39 ))) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[20]~20_combout  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20] & !\datapath_0|JTU_0|internal_adder|Add0~39 )))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[20]~20_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~39 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~40_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~41 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~40 .lut_mask = 16'h698E;
defparam \datapath_0|JTU_0|internal_adder|Add0~40 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[20]~66_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~40_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[21]~68 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[21]~68_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [21] & (!\datapath_0|program_counter_0|internal_register|internal_value[20]~67 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [21] & ((\datapath_0|program_counter_0|internal_register|internal_value[20]~67 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[21]~69  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[20]~67 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [21]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [21]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[20]~67 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[21]~68_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[21]~69 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[21]~68 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[21]~68 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector63~0 (
// Equation(s):
// \controller_0|Selector63~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21] & ((\controller_0|decoded_cluster.LUI_1810~combout ) # (\controller_0|decoded_cluster.AUIPC_1816~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21]),
	.datab(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datac(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector63~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector63~0 .lut_mask = 16'hA8A8;
defparam \controller_0|Selector63~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[21] (
// Equation(s):
// \controller_0|internal_immediate [21] = (\controller_0|WideNor1~combout  & (\controller_0|Selector63~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [21])))

	.dataa(gnd),
	.datab(\controller_0|Selector63~0_combout ),
	.datac(\controller_0|internal_immediate [21]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [21]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[21] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[21] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [21]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~42 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~42_combout  = (\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21] & (\datapath_0|JTU_0|internal_adder|Add0~41  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21] & (!\datapath_0|JTU_0|internal_adder|Add0~41 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~41 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21] & ((\datapath_0|JTU_0|internal_adder|Add0~41 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~43  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21] & !\datapath_0|JTU_0|internal_adder|Add0~41 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~41 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[21]~21_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~41 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~42_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~43 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~42 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~42 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[21]~68_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~42_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[22]~70 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[22]~70_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [22] & (\datapath_0|program_counter_0|internal_register|internal_value[21]~69  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [22] & (!\datapath_0|program_counter_0|internal_register|internal_value[21]~69  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[22]~71  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [22] & !\datapath_0|program_counter_0|internal_register|internal_value[21]~69 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [22]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[21]~69 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[22]~70_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[22]~71 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[22]~70 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[22]~70 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~44 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~44_combout  = (\datapath_0|JTU_0|internal_mux|output_0[22]~22_combout  & (\datapath_0|JTU_0|internal_adder|Add0~43  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[22]~22_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~43  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~45  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[22]~22_combout  & !\datapath_0|JTU_0|internal_adder|Add0~43 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[22]~22_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~43 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~44_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~45 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~44 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~44 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[22]~70_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~44_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[23]~72 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[23]~72_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [23] & (!\datapath_0|program_counter_0|internal_register|internal_value[22]~71 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [23] & ((\datapath_0|program_counter_0|internal_register|internal_value[22]~71 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[23]~73  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[22]~71 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [23]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [23]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[22]~71 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[23]~72_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[23]~73 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[23]~72 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[23]~72 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector65~0 (
// Equation(s):
// \controller_0|Selector65~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & ((\controller_0|decoded_cluster.LUI_1810~combout ) # (\controller_0|decoded_cluster.AUIPC_1816~combout )))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datac(\controller_0|decoded_cluster.AUIPC_1816~combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\controller_0|Selector65~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector65~0 .lut_mask = 16'hA8A8;
defparam \controller_0|Selector65~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_immediate[23] (
// Equation(s):
// \controller_0|internal_immediate [23] = (\controller_0|WideNor1~combout  & (\controller_0|Selector65~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_immediate [23])))

	.dataa(gnd),
	.datab(\controller_0|Selector65~0_combout ),
	.datac(\controller_0|internal_immediate [23]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_immediate [23]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_immediate[23] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_immediate[23] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|immediate_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_immediate [23]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|immediate_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~46 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~46_combout  = (\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23] & (\datapath_0|JTU_0|internal_adder|Add0~45  & VCC)) # 
// (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23] & (!\datapath_0|JTU_0|internal_adder|Add0~45 )))) # (!\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout  & ((\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23] & 
// (!\datapath_0|JTU_0|internal_adder|Add0~45 )) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23] & ((\datapath_0|JTU_0|internal_adder|Add0~45 ) # (GND)))))
// \datapath_0|JTU_0|internal_adder|Add0~47  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout  & (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23] & !\datapath_0|JTU_0|internal_adder|Add0~45 )) # 
// (!\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout  & ((!\datapath_0|JTU_0|internal_adder|Add0~45 ) # (!\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]))))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[23]~23_combout ),
	.datab(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~45 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~46_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~47 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~46 .lut_mask = 16'h9617;
defparam \datapath_0|JTU_0|internal_adder|Add0~46 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[23]~72_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~46_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[24]~74 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[24]~74_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [24] & (\datapath_0|program_counter_0|internal_register|internal_value[23]~73  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [24] & (!\datapath_0|program_counter_0|internal_register|internal_value[23]~73  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[24]~75  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [24] & !\datapath_0|program_counter_0|internal_register|internal_value[23]~73 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [24]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[23]~73 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[24]~74_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[24]~75 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[24]~74 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[24]~74 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~48 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~48_combout  = (\datapath_0|JTU_0|internal_mux|output_0[24]~24_combout  & (\datapath_0|JTU_0|internal_adder|Add0~47  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[24]~24_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~47  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~49  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[24]~24_combout  & !\datapath_0|JTU_0|internal_adder|Add0~47 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[24]~24_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~47 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~48_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~49 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~48 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~48 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[24]~74_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~48_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[25]~76 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[25]~76_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [25] & (!\datapath_0|program_counter_0|internal_register|internal_value[24]~75 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [25] & ((\datapath_0|program_counter_0|internal_register|internal_value[24]~75 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[25]~77  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[24]~75 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [25]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [25]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[24]~75 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[25]~76_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[25]~77 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[25]~76 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[25]~76 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~50 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~50_combout  = (\datapath_0|JTU_0|internal_mux|output_0[25]~25_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~49 )) # (!\datapath_0|JTU_0|internal_mux|output_0[25]~25_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~49 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~51  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~49 ) # (!\datapath_0|JTU_0|internal_mux|output_0[25]~25_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[25]~25_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~49 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~50_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~51 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~50 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~50 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[25]~76_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~50_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[26]~78 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[26]~78_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [26] & (\datapath_0|program_counter_0|internal_register|internal_value[25]~77  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [26] & (!\datapath_0|program_counter_0|internal_register|internal_value[25]~77  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[26]~79  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [26] & !\datapath_0|program_counter_0|internal_register|internal_value[25]~77 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [26]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[25]~77 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[26]~78_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[26]~79 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[26]~78 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[26]~78 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~52 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~52_combout  = (\datapath_0|JTU_0|internal_mux|output_0[26]~26_combout  & (\datapath_0|JTU_0|internal_adder|Add0~51  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[26]~26_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~51  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~53  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[26]~26_combout  & !\datapath_0|JTU_0|internal_adder|Add0~51 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[26]~26_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~51 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~52_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~53 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~52 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~52 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[26]~78_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~52_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[27]~80 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[27]~80_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [27] & (!\datapath_0|program_counter_0|internal_register|internal_value[26]~79 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [27] & ((\datapath_0|program_counter_0|internal_register|internal_value[26]~79 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[27]~81  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[26]~79 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [27]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [27]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[26]~79 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[27]~80_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[27]~81 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[27]~80 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[27]~80 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~54 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~54_combout  = (\datapath_0|JTU_0|internal_mux|output_0[27]~27_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~53 )) # (!\datapath_0|JTU_0|internal_mux|output_0[27]~27_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~53 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~55  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~53 ) # (!\datapath_0|JTU_0|internal_mux|output_0[27]~27_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[27]~27_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~53 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~54_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~55 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~54 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~54 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[27]~80_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~54_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[28]~82 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[28]~82_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [28] & (\datapath_0|program_counter_0|internal_register|internal_value[27]~81  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [28] & (!\datapath_0|program_counter_0|internal_register|internal_value[27]~81  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[28]~83  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [28] & !\datapath_0|program_counter_0|internal_register|internal_value[27]~81 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [28]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[27]~81 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[28]~82_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[28]~83 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[28]~82 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[28]~82 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~56 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~56_combout  = (\datapath_0|JTU_0|internal_mux|output_0[28]~28_combout  & (\datapath_0|JTU_0|internal_adder|Add0~55  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[28]~28_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~55  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~57  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[28]~28_combout  & !\datapath_0|JTU_0|internal_adder|Add0~55 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[28]~28_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~55 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~56_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~57 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~56 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~56 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[28]~82_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~56_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[29]~84 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[29]~84_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [29] & (!\datapath_0|program_counter_0|internal_register|internal_value[28]~83 )) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [29] & ((\datapath_0|program_counter_0|internal_register|internal_value[28]~83 ) # (GND)))
// \datapath_0|program_counter_0|internal_register|internal_value[29]~85  = CARRY((!\datapath_0|program_counter_0|internal_register|internal_value[28]~83 ) # (!\datapath_0|program_counter_0|internal_register|internal_value [29]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [29]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[28]~83 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[29]~84_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[29]~85 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[29]~84 .lut_mask = 16'h5A5F;
defparam \datapath_0|program_counter_0|internal_register|internal_value[29]~84 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~58 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~58_combout  = (\datapath_0|JTU_0|internal_mux|output_0[29]~29_combout  & (!\datapath_0|JTU_0|internal_adder|Add0~57 )) # (!\datapath_0|JTU_0|internal_mux|output_0[29]~29_combout  & 
// ((\datapath_0|JTU_0|internal_adder|Add0~57 ) # (GND)))
// \datapath_0|JTU_0|internal_adder|Add0~59  = CARRY((!\datapath_0|JTU_0|internal_adder|Add0~57 ) # (!\datapath_0|JTU_0|internal_mux|output_0[29]~29_combout ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[29]~29_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~57 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~58_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~59 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~58 .lut_mask = 16'h5A5F;
defparam \datapath_0|JTU_0|internal_adder|Add0~58 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[29]~84_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~58_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[30]~86 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[30]~86_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [30] & (\datapath_0|program_counter_0|internal_register|internal_value[29]~85  $ (GND))) # 
// (!\datapath_0|program_counter_0|internal_register|internal_value [30] & (!\datapath_0|program_counter_0|internal_register|internal_value[29]~85  & VCC))
// \datapath_0|program_counter_0|internal_register|internal_value[30]~87  = CARRY((\datapath_0|program_counter_0|internal_register|internal_value [30] & !\datapath_0|program_counter_0|internal_register|internal_value[29]~85 ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [30]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[29]~85 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[30]~86_combout ),
	.cout(\datapath_0|program_counter_0|internal_register|internal_value[30]~87 ));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[30]~86 .lut_mask = 16'hA50A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[30]~86 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~60 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~60_combout  = (\datapath_0|JTU_0|internal_mux|output_0[30]~30_combout  & (\datapath_0|JTU_0|internal_adder|Add0~59  $ (GND))) # (!\datapath_0|JTU_0|internal_mux|output_0[30]~30_combout  & 
// (!\datapath_0|JTU_0|internal_adder|Add0~59  & VCC))
// \datapath_0|JTU_0|internal_adder|Add0~61  = CARRY((\datapath_0|JTU_0|internal_mux|output_0[30]~30_combout  & !\datapath_0|JTU_0|internal_adder|Add0~59 ))

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[30]~30_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~59 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~60_combout ),
	.cout(\datapath_0|JTU_0|internal_adder|Add0~61 ));
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~60 .lut_mask = 16'hA50A;
defparam \datapath_0|JTU_0|internal_adder|Add0~60 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[30]~86_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~60_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|program_counter_0|internal_register|internal_value[31]~88 (
// Equation(s):
// \datapath_0|program_counter_0|internal_register|internal_value[31]~88_combout  = \datapath_0|program_counter_0|internal_register|internal_value [31] $ (\datapath_0|program_counter_0|internal_register|internal_value[30]~87 )

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [31]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\datapath_0|program_counter_0|internal_register|internal_value[30]~87 ),
	.combout(\datapath_0|program_counter_0|internal_register|internal_value[31]~88_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[31]~88 .lut_mask = 16'h5A5A;
defparam \datapath_0|program_counter_0|internal_register|internal_value[31]~88 .sum_lutc_input = "cin";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|JTU_0|internal_adder|Add0~62 (
// Equation(s):
// \datapath_0|JTU_0|internal_adder|Add0~62_combout  = \datapath_0|JTU_0|internal_mux|output_0[31]~31_combout  $ (\datapath_0|JTU_0|internal_adder|Add0~61 )

	.dataa(\datapath_0|JTU_0|internal_mux|output_0[31]~31_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\datapath_0|JTU_0|internal_adder|Add0~61 ),
	.combout(\datapath_0|JTU_0|internal_adder|Add0~62_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|JTU_0|internal_adder|Add0~62 .lut_mask = 16'h5A5A;
defparam \datapath_0|JTU_0|internal_adder|Add0~62 .sum_lutc_input = "cin";
// synopsys translate_on

dffeas \datapath_0|program_counter_0|internal_register|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|program_counter_0|internal_register|internal_value[31]~88_combout ),
	.asdata(\datapath_0|JTU_0|internal_adder|Add0~62_combout ),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\datapath_0|comb~2_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|program_counter_0|internal_register|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|program_counter_0|internal_register|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|program_counter_0|internal_register|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[31]~2 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[31]~2_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q  & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4] & 
// (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[31]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[31]~2 .lut_mask = 16'h8000;
defparam \datapath_0|register_file_0|internal_reg_load[31]~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[31]~3 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[31]~3_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2] & 
// \datapath_0|register_file_0|internal_reg_load[31]~2_combout ))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]),
	.datac(\datapath_0|register_file_0|internal_reg_load[31]~2_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[31]~3 .lut_mask = 16'h8080;
defparam \datapath_0|register_file_0|internal_reg_load[31]~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x31|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[31]~3_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x31|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x31|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x31|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[1]~4 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[1]~4_combout  = (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))

	.dataa(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[1]~4 .lut_mask = 16'h0008;
defparam \datapath_0|register_file_0|internal_reg_load[1]~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x1|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[1]~4_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x1|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x1|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x1|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector87~0 (
// Equation(s):
// \controller_0|Selector87~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21] & ((\controller_0|decoded_cluster.OP_1834~combout ) # ((\controller_0|decoded_cluster.OP_IMM_1840~combout ) # (!\controller_0|WideNor1~4_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [21]),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datad(\controller_0|WideNor1~4_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector87~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector87~0 .lut_mask = 16'hA8AA;
defparam \controller_0|Selector87~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_read_address_1[1] (
// Equation(s):
// \controller_0|internal_reg_file_read_address_1 [1] = (\controller_0|WideNor1~combout  & (\controller_0|Selector87~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_read_address_1 [1])))

	.dataa(gnd),
	.datab(\controller_0|Selector87~0_combout ),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_read_address_1 [1]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_read_address_1[1] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_read_address_1[1] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_read_address_1 [1]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector86~0 (
// Equation(s):
// \controller_0|Selector86~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20] & ((\controller_0|decoded_cluster.OP_1834~combout ) # ((\controller_0|decoded_cluster.OP_IMM_1840~combout ) # (!\controller_0|WideNor1~4_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [20]),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datad(\controller_0|WideNor1~4_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector86~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector86~0 .lut_mask = 16'hA8AA;
defparam \controller_0|Selector86~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_read_address_1[0] (
// Equation(s):
// \controller_0|internal_reg_file_read_address_1 [0] = (\controller_0|WideNor1~combout  & (\controller_0|Selector86~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_read_address_1 [0])))

	.dataa(gnd),
	.datab(\controller_0|Selector86~0_combout ),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_read_address_1 [0]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_read_address_1[0] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_read_address_1[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_read_address_1 [0]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal7~0 (
// Equation(s):
// \datapath_0|FU_0|Equal7~0_combout  = (\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0] & (\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0] & (\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1] 
// $ (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1])))) # (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0] & (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0] & 
// (\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1] $ (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]))))

	.dataa(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [1]),
	.datac(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]),
	.datad(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal7~0 .lut_mask = 16'h8241;
defparam \datapath_0|FU_0|Equal7~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|Selector89~0 (
// Equation(s):
// \controller_0|Selector89~0_combout  = (\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23] & ((\controller_0|decoded_cluster.OP_1834~combout ) # ((\controller_0|decoded_cluster.OP_IMM_1840~combout ) # (!\controller_0|WideNor1~4_combout ))))

	.dataa(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.datab(\controller_0|decoded_cluster.OP_1834~combout ),
	.datac(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datad(\controller_0|WideNor1~4_combout ),
	.cin(gnd),
	.combout(\controller_0|Selector89~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|Selector89~0 .lut_mask = 16'hA8AA;
defparam \controller_0|Selector89~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_reg_file_read_address_1[3] (
// Equation(s):
// \controller_0|internal_reg_file_read_address_1 [3] = (\controller_0|WideNor1~combout  & (\controller_0|Selector89~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_reg_file_read_address_1 [3])))

	.dataa(gnd),
	.datab(\controller_0|Selector89~0_combout ),
	.datac(\controller_0|internal_reg_file_read_address_1 [3]),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_reg_file_read_address_1 [3]),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_reg_file_read_address_1[3] .lut_mask = 16'hCCF0;
defparam \controller_0|internal_reg_file_read_address_1[3] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_reg_file_read_address_1 [3]),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal7~1 (
// Equation(s):
// \datapath_0|FU_0|Equal7~1_combout  = (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4] & (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3] $ 
// (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]))))

	.dataa(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal7~1 .lut_mask = 16'h0009;
defparam \datapath_0|FU_0|Equal7~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal9~0 (
// Equation(s):
// \datapath_0|FU_0|Equal9~0_combout  = (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0] & (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1] & 
// !\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]))

	.dataa(gnd),
	.datab(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0]),
	.datac(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]),
	.datad(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal9~0 .lut_mask = 16'h0003;
defparam \datapath_0|FU_0|Equal9~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~3 (
// Equation(s):
// \datapath_0|FU_0|forward_1~3_combout  = (\datapath_0|FU_0|forward_1~0_combout  & (\datapath_0|FU_0|Equal7~0_combout  & (\datapath_0|FU_0|Equal7~1_combout  & !\datapath_0|FU_0|Equal9~0_combout )))

	.dataa(\datapath_0|FU_0|forward_1~0_combout ),
	.datab(\datapath_0|FU_0|Equal7~0_combout ),
	.datac(\datapath_0|FU_0|Equal7~1_combout ),
	.datad(\datapath_0|FU_0|Equal9~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~3 .lut_mask = 16'h0080;
defparam \datapath_0|FU_0|forward_1~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[11]~1 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[11]~1_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q  & (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4] & 
// !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ),
	.datab(gnd),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [4]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[11]~1 .lut_mask = 16'h000A;
defparam \datapath_0|register_file_0|internal_reg_load[11]~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~4 (
// Equation(s):
// \datapath_0|FU_0|forward_1~4_combout  = (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1] & (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & (\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1] $ 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]))))

	.dataa(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.datad(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~4 .lut_mask = 16'h2100;
defparam \datapath_0|FU_0|forward_1~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~5 (
// Equation(s):
// \datapath_0|FU_0|forward_1~5_combout  = (\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] $ ((\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value 
// [3])))) # (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3] & ((\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3])) # 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & \datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]))))

	.dataa(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [3]),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datad(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~5 .lut_mask = 16'h6968;
defparam \datapath_0|FU_0|forward_1~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~6 (
// Equation(s):
// \datapath_0|FU_0|forward_1~6_combout  = (\datapath_0|FU_0|forward_1~4_combout  & ((\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0] & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & 
// !\datapath_0|FU_0|forward_1~5_combout )) # (!\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0] & (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & \datapath_0|FU_0|forward_1~5_combout ))))

	.dataa(\datapath_0|ID_EX_PLR|register_file_read_address_1_reg|internal_value [0]),
	.datab(\datapath_0|FU_0|forward_1~4_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datad(\datapath_0|FU_0|forward_1~5_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~6 .lut_mask = 16'h0480;
defparam \datapath_0|FU_0|forward_1~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_1_control[1]~0 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_1_control[1]~0_combout  = (\datapath_0|FU_0|forward_1~2_combout  & ((\datapath_0|FU_0|forward_1~3_combout ) # ((\datapath_0|FU_0|forward_1~6_combout  & !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]))))

	.dataa(\datapath_0|FU_0|forward_1~2_combout ),
	.datab(\datapath_0|FU_0|forward_1~3_combout ),
	.datac(\datapath_0|FU_0|forward_1~6_combout ),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_1_control[1]~0 .lut_mask = 16'h88A8;
defparam \datapath_0|FU_0|forward_mux_1_control[1]~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~2 (
// Equation(s):
// \datapath_0|FU_0|forward_1~2_combout  = (\datapath_0|FU_0|Equal9~0_combout ) # (((!\datapath_0|FU_0|Equal7~1_combout ) # (!\datapath_0|FU_0|Equal7~0_combout )) # (!\datapath_0|FU_0|forward_1~1_combout ))

	.dataa(\datapath_0|FU_0|Equal9~0_combout ),
	.datab(\datapath_0|FU_0|forward_1~1_combout ),
	.datac(\datapath_0|FU_0|Equal7~0_combout ),
	.datad(\datapath_0|FU_0|Equal7~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~2 .lut_mask = 16'hBFFF;
defparam \datapath_0|FU_0|forward_1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_1_control[0]~1 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_1_control[0]~1_combout  = ((\datapath_0|FU_0|forward_1~6_combout  & (!\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & !\datapath_0|FU_0|forward_1~3_combout ))) # (!\datapath_0|FU_0|forward_1~2_combout )

	.dataa(\datapath_0|FU_0|forward_1~6_combout ),
	.datab(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datac(\datapath_0|FU_0|forward_1~3_combout ),
	.datad(\datapath_0|FU_0|forward_1~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_1_control[0]~1 .lut_mask = 16'h02FF;
defparam \datapath_0|FU_0|forward_mux_1_control[0]~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[3]~6 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[3]~6_combout  = (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & 
// (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3])))

	.dataa(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datab(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[3]~6 .lut_mask = 16'h0080;
defparam \datapath_0|register_file_0|internal_reg_load[3]~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & !\controller_0|internal_reg_file_read_address_1 [3])

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(gnd),
	.datac(gnd),
	.datad(\controller_0|internal_reg_file_read_address_1 [3]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~0 .lut_mask = 16'h00AA;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[9]~8 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[9]~8_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & 
// (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[9]~8 .lut_mask = 16'h0080;
defparam \datapath_0|register_file_0|internal_reg_load[9]~8 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[8]~9 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[8]~9_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & 
// (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[8]~9 .lut_mask = 16'h0008;
defparam \datapath_0|register_file_0|internal_reg_load[8]~9 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux31~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux31~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [0])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [0])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [0]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux31~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[11]~10 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[11]~10_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & 
// (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0] & \datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[11]~10 .lut_mask = 16'h8000;
defparam \datapath_0|register_file_0|internal_reg_load[11]~10 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux31~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux31~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux31~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [0]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux31~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux31~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [0]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux31~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux31~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~1_combout  = (\controller_0|internal_reg_file_read_address_1 [3]) # ((\controller_0|internal_reg_file_read_address_1 [0] & !\controller_0|internal_reg_file_read_address_1 [1]))

	.dataa(\controller_0|internal_reg_file_read_address_1 [3]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(gnd),
	.datad(\controller_0|internal_reg_file_read_address_1 [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~1 .lut_mask = 16'hAAEE;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~2_combout  = (\controller_0|internal_reg_file_read_address_1 [3]) # ((\controller_0|internal_reg_file_read_address_1 [0] & \controller_0|internal_reg_file_read_address_1 [1]))

	.dataa(\controller_0|internal_reg_file_read_address_1 [3]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~2 .lut_mask = 16'hEAEA;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux31~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux31~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux31~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [0])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [0]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux31~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux31~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux31~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux31~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux31~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux31~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux31~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [0]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux31~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [0])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux31~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [0]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux31~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux31~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux31~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux31~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux31~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux31~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [0])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux31~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux31~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux31~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux31~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux31~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux31~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]))) # (!\datapath_0|forward_mux_1|Mux31~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [0])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux31~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [0]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux31~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux31~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux31~2_combout  = (\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|FU_0|forward_1~6_combout  & (\datapath_0|FU_0|forward_1~2_combout  & !\datapath_0|FU_0|forward_1~3_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datab(\datapath_0|FU_0|forward_1~6_combout ),
	.datac(\datapath_0|FU_0|forward_1~2_combout ),
	.datad(\datapath_0|FU_0|forward_1~3_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux31~2 .lut_mask = 16'h0080;
defparam \datapath_0|forward_mux_1|Mux31~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux31~3 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux31~3_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux31~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [0]),
	.datab(\datapath_0|forward_mux_1|Mux31~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux31~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux31~3 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux31~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|WideOr29~0 (
// Equation(s):
// \controller_0|WideOr29~0_combout  = (\controller_0|decoded_cluster.LUI_1810~combout ) # ((\controller_0|decoded_cluster.OP_IMM_1840~combout ) # ((\controller_0|decoded_cluster.LOAD_1918~combout ) # (\controller_0|decoded_cluster.STORE_1912~combout )))

	.dataa(\controller_0|decoded_cluster.LUI_1810~combout ),
	.datab(\controller_0|decoded_cluster.OP_IMM_1840~combout ),
	.datac(\controller_0|decoded_cluster.LOAD_1918~combout ),
	.datad(\controller_0|decoded_cluster.STORE_1912~combout ),
	.cin(gnd),
	.combout(\controller_0|WideOr29~0_combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|WideOr29~0 .lut_mask = 16'hFFFE;
defparam \controller_0|WideOr29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \controller_0|internal_mux1_sel (
// Equation(s):
// \controller_0|internal_mux1_sel~combout  = (\controller_0|WideNor1~combout  & (\controller_0|WideOr29~0_combout )) # (!\controller_0|WideNor1~combout  & ((\controller_0|internal_mux1_sel~combout )))

	.dataa(gnd),
	.datab(\controller_0|WideOr29~0_combout ),
	.datac(\controller_0|internal_mux1_sel~combout ),
	.datad(\controller_0|WideNor1~combout ),
	.cin(gnd),
	.combout(\controller_0|internal_mux1_sel~combout ),
	.cout());
// synopsys translate_off
defparam \controller_0|internal_mux1_sel .lut_mask = 16'hCCF0;
defparam \controller_0|internal_mux1_sel .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\controller_0|internal_mux1_sel~combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[0]~0 (
// Equation(s):
// \datapath_0|mux_1|output_0[0]~0_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~3_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [0]),
	.datab(\datapath_0|forward_mux_1|Mux31~3_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[0]~0 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|internal_reg_load[10]~7 (
// Equation(s):
// \datapath_0|register_file_0|internal_reg_load[10]~7_combout  = (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & 
// (\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1] & !\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0])))

	.dataa(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datab(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [1]),
	.datad(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|internal_reg_load[10]~7 .lut_mask = 16'h0080;
defparam \datapath_0|register_file_0|internal_reg_load[10]~7 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[1] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux30~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux30~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [1])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [1])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [1]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux30~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[1] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux30~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux30~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux30~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux30~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [1]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux30~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux30~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [1]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux30~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux30~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux30~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux30~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux30~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [1])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [1]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux30~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux30~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux30~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux30~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux30~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux30~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux30~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [1]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux30~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [1])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux30~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [1]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux30~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux30~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux30~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux30~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[1] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux30~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [1]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[1] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[1] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux30~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux30~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [1])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [1])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [1]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux30~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux30~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux30~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux30~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux30~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux30~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]))) # (!\datapath_0|forward_mux_1|Mux30~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux30~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux30~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux30~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux30~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux30~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux30~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux30~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux30~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [1]),
	.datab(\datapath_0|forward_mux_1|Mux30~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux30~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux30~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux30~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[1]~1 (
// Equation(s):
// \datapath_0|mux_1|output_0[1]~1_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux30~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [1]),
	.datab(\datapath_0|forward_mux_1|Mux30~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[1]~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[1]~1 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[1]~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux29~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux29~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [2])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [2])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [2]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux29~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux29~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux29~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux29~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [2]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux29~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [2])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux29~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [2]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux29~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux29~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux29~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux29~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux29~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [2])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [2]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux29~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux29~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux29~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux29~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux29~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux29~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux29~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [2]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux29~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [2])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux29~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [2]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [2]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux29~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux29~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux29~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux29~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux29~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux29~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux29~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [2])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux29~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux29~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux29~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux29~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]))) # (!\datapath_0|forward_mux_1|Mux29~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [2])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux29~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [2]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux29~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux29~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux29~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux29~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux29~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [2]),
	.datab(\datapath_0|forward_mux_1|Mux29~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux29~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux29~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux29~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[2]~2 (
// Equation(s):
// \datapath_0|mux_1|output_0[2]~2_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux29~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [2]),
	.datab(\datapath_0|forward_mux_1|Mux29~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[2]~2 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[3] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux28~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux28~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [3])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [3])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [3]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux28~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux28~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux28~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[3] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux28~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux28~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux28~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux28~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [3]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux28~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [3])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux28~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [3]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux28~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux28~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux28~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux28~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux28~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux28~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux28~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [3])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [3]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux28~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux28~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux28~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux28~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux28~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux28~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux28~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [3]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux28~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [3])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux28~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [3]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [3]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux28~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux28~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux28~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux28~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[3] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux28~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [3]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[3] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[3] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux28~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux28~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [3])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [3])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [3]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux28~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux28~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux28~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux28~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux28~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux28~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]))) # (!\datapath_0|forward_mux_1|Mux28~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux28~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux28~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux28~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux28~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux28~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux28~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux28~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux28~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [3]),
	.datab(\datapath_0|forward_mux_1|Mux28~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux28~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux28~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux28~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[3]~3 (
// Equation(s):
// \datapath_0|mux_1|output_0[3]~3_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux28~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [3]),
	.datab(\datapath_0|forward_mux_1|Mux28~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[3]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[3]~3 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[3]~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux27~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux27~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [4])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [4])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [4]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux27~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux27~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux27~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux27~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux27~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [4]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux27~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [4])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux27~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [4]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux27~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux27~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux27~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux27~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux27~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [4])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [4]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux27~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux27~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux27~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux27~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux27~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux27~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux27~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [4]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux27~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [4])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux27~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [4]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [4]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux27~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux27~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux27~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux27~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[4] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux27~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux27~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux27~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [4])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux27~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux27~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux27~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux27~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux27~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux27~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]))) # (!\datapath_0|forward_mux_1|Mux27~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [4])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux27~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [4]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux27~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux27~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux27~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux27~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux27~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux27~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux27~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [4]),
	.datab(\datapath_0|forward_mux_1|Mux27~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux27~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux27~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux27~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[4]~4 (
// Equation(s):
// \datapath_0|mux_1|output_0[4]~4_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux27~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [4]),
	.datab(\datapath_0|forward_mux_1|Mux27~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[4]~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[4]~4 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[4]~4 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[5] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux26~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux26~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [5])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [5])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [5]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux26~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[5] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux26~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux26~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux26~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux26~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [5]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux26~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [5])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux26~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [5]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux26~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux26~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux26~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux26~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux26~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [5])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [5]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux26~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux26~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux26~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux26~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux26~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux26~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux26~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [5]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux26~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [5])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux26~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [5]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [5]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux26~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux26~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux26~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux26~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux26~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux26~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux26~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [5])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [5])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [5]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux26~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux26~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux26~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux26~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux26~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux26~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]))) # (!\datapath_0|forward_mux_1|Mux26~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux26~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux26~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux26~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux26~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux26~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux26~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux26~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux26~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [5]),
	.datab(\datapath_0|forward_mux_1|Mux26~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux26~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux26~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux26~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[5]~5 (
// Equation(s):
// \datapath_0|mux_1|output_0[5]~5_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux26~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [5]),
	.datab(\datapath_0|forward_mux_1|Mux26~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[5]~5 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux25~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux25~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [6])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [6])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [6]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux25~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux25~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux25~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux25~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux25~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [6]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux25~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [6])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux25~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [6]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux25~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux25~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux25~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux25~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux25~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux25~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux25~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [6])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [6]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux25~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux25~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux25~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux25~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux25~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux25~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux25~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [6]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux25~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [6])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux25~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [6]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [6]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux25~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux25~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux25~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux25~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[6] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux25~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux25~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux25~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [6])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux25~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux25~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux25~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux25~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux25~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux25~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]))) # (!\datapath_0|forward_mux_1|Mux25~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [6])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux25~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [6]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux25~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux25~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux25~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux25~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux25~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux25~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux25~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [6]),
	.datab(\datapath_0|forward_mux_1|Mux25~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux25~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux25~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux25~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[6]~6 (
// Equation(s):
// \datapath_0|mux_1|output_0[6]~6_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux25~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [6]),
	.datab(\datapath_0|forward_mux_1|Mux25~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[6]~6 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [7]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[7] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux24~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux24~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [7])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [7])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [7]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux24~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[7] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux24~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux24~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux24~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux24~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [7]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux24~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [7])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux24~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [7]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux24~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux24~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux24~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux24~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux24~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [7])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [7]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux24~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux24~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux24~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux24~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux24~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux24~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux24~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [7]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux24~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [7])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux24~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [7]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [7]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux24~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux24~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux24~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux24~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[7] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux24~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [7]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[7] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[7] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux24~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux24~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [7])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [7])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [7]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux24~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux24~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux24~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux24~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux24~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux24~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]))) # (!\datapath_0|forward_mux_1|Mux24~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux24~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [7]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux24~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [7]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux24~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux24~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux24~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[7]~7 (
// Equation(s):
// \datapath_0|mux_1|output_0[7]~7_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux24~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [7]),
	.datab(\datapath_0|forward_mux_1|Mux24~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[7]~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[7]~7 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[7]~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~0 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~0_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [8] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [8]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~0 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[0] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [0] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~0_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [0])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~0_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[0] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[0] .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~0 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~0_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~0 .lut_mask = 16'h0040;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~0_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~0_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~8 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~8_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~8 .lut_mask = 16'h0010;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~8 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~8_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~8_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~180 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~180_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~180_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~180 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~180 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~13 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~13_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~13 .lut_mask = 16'h0080;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~13 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~13_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~13_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~181 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~181_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~180_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~180_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~180_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~180_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~181_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~181 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~181 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~6 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~6_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~6 .lut_mask = 16'h0002;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~6_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~6_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~182 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~182_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~182_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~182 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~182 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~183 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~183_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~182_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~182_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~182_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~182_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~183_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~183 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~183 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~184 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~184_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~181_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~183_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~181_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~183_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~184_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~184 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~184 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|Ram0~3 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|Ram0~3_combout  = (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & 
// \datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5])))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|Ram0~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~3 .lut_mask = 16'h4000;
defparam \datapath_0|datamem_module_0|datamem_0|Ram0~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29 (
// Equation(s):
// \datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout  = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|datamem_0|Ram0~3_combout  & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & 
// !\datapath_0|datamem_module_0|Equal0~0_combout )))

	.dataa(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.datab(\datapath_0|datamem_module_0|datamem_0|Ram0~3_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29 .lut_mask = 16'h0008;
defparam \datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~185 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~185_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~185_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~185 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~185 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~186 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~186_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~185_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~185_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~185_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~185_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~186_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~186 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~186 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~187 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~187_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~184_combout  & ((\datapath_0|datamem_module_0|output_data~186_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~184_combout  & (\datapath_0|datamem_module_0|output_data~179_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~184_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~179_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~184_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~186_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~187_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~187 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~187 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~188 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~188_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~177_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~187_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~177_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~187_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~188_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~188 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~188 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[8] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [8] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [8]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~188_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~188_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [8]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [8]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[8] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[8] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [8]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[8] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux23~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux23~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [8])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [8])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [8]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux23~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[8] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux23~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux23~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux23~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux23~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [8]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux23~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [8])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux23~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [8]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux23~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux23~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux23~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux23~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux23~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux23~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux23~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [8])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [8]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux23~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux23~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux23~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux23~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux23~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux23~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux23~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [8]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux23~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [8])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux23~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [8]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [8]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux23~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux23~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux23~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux23~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[8] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux23~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [8]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[8] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[8] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux23~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux23~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [8])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [8]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux23~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux23~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux23~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux23~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux23~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux23~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]))) # (!\datapath_0|forward_mux_1|Mux23~0_combout 
//  & (\datapath_0|datamem_module_0|output_data [8])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux23~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [8]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux23~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [8]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux23~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux23~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux23~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[8]~8 (
// Equation(s):
// \datapath_0|mux_1|output_0[8]~8_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux23~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [8]),
	.datab(\datapath_0|forward_mux_1|Mux23~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[8]~8_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[8]~8 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[8]~8 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [9]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[9] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux22~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux22~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [9])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [9])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [9]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux22~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux22~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux22~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[9] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux22~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux22~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux22~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux22~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [9]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux22~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [9])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux22~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [9]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux22~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux22~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux22~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux22~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux22~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux22~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux22~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [9])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [9]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux22~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux22~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux22~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux22~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux22~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux22~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux22~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [9]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux22~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [9])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux22~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [9]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [9]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux22~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux22~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux22~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux22~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[9] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux22~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [9]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[9] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[9] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux22~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux22~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [9])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [9])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [9]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux22~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux22~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux22~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux22~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux22~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux22~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]))) # (!\datapath_0|forward_mux_1|Mux22~0_combout 
//  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux22~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [9]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux22~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [9]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux22~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux22~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux22~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[9]~9 (
// Equation(s):
// \datapath_0|mux_1|output_0[9]~9_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux22~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [9]),
	.datab(\datapath_0|forward_mux_1|Mux22~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[9]~9_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[9]~9 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[9]~9 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~2 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~2_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [10] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [10]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~2 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[2] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [2] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~2_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [2])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~2_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[2] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[2] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~222 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~222_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~222_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~222 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~222 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~223 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~223_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~222_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~222_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~222_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~222_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~223_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~223 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~223 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~224 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~224_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~224_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~224 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~224 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~225 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~225_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~224_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~224_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~224_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~224_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~225_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~225 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~225 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~226 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~226_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~223_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~225_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~223_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~225_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~226_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~226 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~226 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~227 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~227_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~227_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~227 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~227 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~228 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~228_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~227_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~227_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~227_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~227_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~228_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~228 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~228 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~229 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~229_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~226_combout  & ((\datapath_0|datamem_module_0|output_data~228_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~226_combout  & (\datapath_0|datamem_module_0|output_data~221_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~226_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~221_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~226_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~228_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~229_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~229 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~229 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~230 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~230_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~219_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~229_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~219_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~229_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~230_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~230 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~230 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[10] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [10] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [10]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~230_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~230_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [10]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [10]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[10] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[10] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [10]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[10] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux21~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux21~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [10])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [10])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [10]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux21~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[10] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux21~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux21~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux21~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux21~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [10]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux21~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [10])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux21~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [10]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux21~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux21~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux21~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux21~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux21~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux21~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux21~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [10])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [10]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux21~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux21~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux21~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux21~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux21~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux21~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux21~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [10]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux21~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [10])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux21~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [10]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [10]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux21~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux21~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux21~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux21~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[10] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux21~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [10]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[10] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[10] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux21~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux21~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [10])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [10]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux21~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux21~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux21~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux21~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux21~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux21~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]))) # 
// (!\datapath_0|forward_mux_1|Mux21~0_combout  & (\datapath_0|datamem_module_0|output_data [10])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux21~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [10]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux21~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [10]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux21~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux21~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux21~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[10]~10 (
// Equation(s):
// \datapath_0|mux_1|output_0[10]~10_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux21~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [10]),
	.datab(\datapath_0|forward_mux_1|Mux21~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[10]~10_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[10]~10 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[10]~10 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[11] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~3_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [11])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [11])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [11]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~3 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[11] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux20~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~4 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~4_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux20~3_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [11]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~3_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [11])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux20~3_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [11]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~3_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~4 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~5 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~5_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~4_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [11])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [11]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux20~4_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~5_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~5 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~5 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux20~6 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux20~6_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~5_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [11]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~5_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [11])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~5_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [11]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [11]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~5_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux20~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux20~6 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux20~6 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[11] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux20~6_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [11]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[11] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[11] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux20~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux20~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [11])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [11])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [11]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux20~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux20~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux20~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux20~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux20~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux20~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]))) # 
// (!\datapath_0|forward_mux_1|Mux20~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux20~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [11]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux20~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [11]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux20~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux20~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux20~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux20~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux20~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux20~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [11]),
	.datab(\datapath_0|forward_mux_1|Mux20~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux20~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux20~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux20~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[11]~11 (
// Equation(s):
// \datapath_0|mux_1|output_0[11]~11_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux20~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [11]),
	.datab(\datapath_0|forward_mux_1|Mux20~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[11]~11_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[11]~11 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[11]~11 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~4 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~4_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [12] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [12]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~4 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[4] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [4] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~4_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [4])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~4_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[4] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[4] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~264 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~264_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~264_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~264 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~264 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~265 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~265_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~264_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~264_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~264_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~264_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~265_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~265 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~265 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~266 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~266_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~266_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~266 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~266 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~267 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~267_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~266_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~266_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~266_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~266_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~267_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~267 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~267 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~268 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~268_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~265_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~267_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~265_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~267_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~268_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~268 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~268 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~269 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~269_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~269_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~269 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~269 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~270 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~270_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~269_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~269_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~269_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~269_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~270_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~270 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~270 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~271 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~271_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~268_combout  & ((\datapath_0|datamem_module_0|output_data~270_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~268_combout  & (\datapath_0|datamem_module_0|output_data~263_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~268_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~263_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~268_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~270_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~271_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~271 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~271 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~272 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~272_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~261_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~271_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~261_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~271_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~272_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~272 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~272 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[12] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [12] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [12]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~272_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~272_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [12]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [12]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[12] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[12] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [12]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[12] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux19~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux19~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [12])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [12])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [12]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux19~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux19~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux19~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[12] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux19~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux19~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux19~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux19~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [12]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux19~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [12])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux19~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [12]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux19~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux19~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux19~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux19~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux19~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux19~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux19~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [12])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [12]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux19~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux19~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux19~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux19~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux19~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux19~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux19~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [12]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux19~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [12])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux19~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [12]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [12]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux19~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux19~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux19~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux19~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[12] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux19~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [12]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[12] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[12] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux19~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux19~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [12])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [12]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux19~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux19~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux19~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux19~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux19~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux19~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]))) # 
// (!\datapath_0|forward_mux_1|Mux19~0_combout  & (\datapath_0|datamem_module_0|output_data [12])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux19~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [12]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux19~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [12]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux19~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux19~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux19~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[12]~12 (
// Equation(s):
// \datapath_0|mux_1|output_0[12]~12_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux19~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [12]),
	.datab(\datapath_0|forward_mux_1|Mux19~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[12]~12_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[12]~12 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[12]~12 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[13] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux18~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux18~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [13])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [13])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [13]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux18~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux18~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux18~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[13] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux18~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux18~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux18~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux18~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [13]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux18~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [13])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux18~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [13]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux18~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux18~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux18~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux18~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux18~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux18~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux18~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [13])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [13]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux18~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux18~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux18~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux18~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux18~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux18~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux18~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [13]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux18~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [13])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux18~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [13]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [13]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux18~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux18~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux18~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux18~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[13] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux18~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [13]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[13] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[13] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux18~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux18~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [13])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [13])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [13]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux18~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux18~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux18~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux18~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux18~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux18~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]))) # 
// (!\datapath_0|forward_mux_1|Mux18~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux18~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [13]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux18~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [13]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux18~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux18~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux18~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux18~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux18~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux18~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [13]),
	.datab(\datapath_0|forward_mux_1|Mux18~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux18~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux18~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux18~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[13]~13 (
// Equation(s):
// \datapath_0|mux_1|output_0[13]~13_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux18~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [13]),
	.datab(\datapath_0|forward_mux_1|Mux18~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[13]~13_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[13]~13 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[13]~13 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1~6 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1~6_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [14] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [14]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1~6 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_1~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_1[6] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_1 [6] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_1~6_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_1 [6])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_1~6_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_1[6] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_1[6] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~306 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~306_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x6|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x4|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~306_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~306 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~306 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~307 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~307_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~306_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~306_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~306_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x5|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~306_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x7|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~307_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~307 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~307 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~308 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~308_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x1|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x0|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~308_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~308 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~308 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~309 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~309_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~308_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~308_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~308_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x2|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~308_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x3|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~309_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~309 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~309 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~310 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~310_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~307_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~309_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~307_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~309_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~310_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~310 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~310 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~311 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~311_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_1|reg_x14|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x12|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~311_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~311 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~311 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_1 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~312 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~312_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~311_combout  & ((\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~311_combout  & (\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~311_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_1|reg_x13|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~311_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_1|reg_x15|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~312_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~312 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~312 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~313 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~313_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~310_combout  & ((\datapath_0|datamem_module_0|output_data~312_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~310_combout  & (\datapath_0|datamem_module_0|output_data~305_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~310_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~305_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~310_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~312_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~313_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~313 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~313 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~314 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~314_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~303_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~313_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~303_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~313_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~314_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~314 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~314 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[14] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [14] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [14]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~314_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~314_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [14]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [14]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[14] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[14] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [14]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[14] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux17~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux17~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [14])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [14])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [14]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux17~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux17~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux17~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[14] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux17~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux17~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux17~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux17~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [14]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux17~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [14])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux17~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [14]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux17~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux17~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux17~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux17~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux17~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux17~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux17~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [14])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [14]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux17~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux17~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux17~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux17~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux17~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux17~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux17~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [14]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux17~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [14])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux17~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [14]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [14]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux17~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux17~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux17~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux17~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[14] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux17~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [14]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[14] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[14] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux17~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux17~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [14])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [14]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux17~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux17~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux17~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux17~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux17~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux17~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]))) # 
// (!\datapath_0|forward_mux_1|Mux17~0_combout  & (\datapath_0|datamem_module_0|output_data [14])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux17~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [14]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux17~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [14]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux17~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux17~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux17~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[14]~14 (
// Equation(s):
// \datapath_0|mux_1|output_0[14]~14_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux17~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [14]),
	.datab(\datapath_0|forward_mux_1|Mux17~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[14]~14_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[14]~14 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[14]~14 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[15] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux16~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux16~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [15])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [15])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [15]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux16~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[15] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux16~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux16~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux16~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux16~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [15]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux16~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [15])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux16~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [15]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux16~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux16~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux16~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux16~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux16~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux16~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux16~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [15])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [15]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux16~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux16~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux16~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux16~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux16~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux16~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux16~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [15]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux16~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [15])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux16~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [15]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [15]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux16~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux16~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux16~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux16~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux16~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux16~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux16~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [15])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [15])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [15]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux16~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux16~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux16~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux16~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]))) # 
// (!\datapath_0|forward_mux_1|Mux16~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux16~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [15]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux16~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [15]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux16~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux16~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux16~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux16~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux16~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux16~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [15]),
	.datab(\datapath_0|forward_mux_1|Mux16~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux16~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux16~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux16~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[15]~15 (
// Equation(s):
// \datapath_0|mux_1|output_0[15]~15_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux16~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [15]),
	.datab(\datapath_0|forward_mux_1|Mux16~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[15]~15_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[15]~15 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[15]~15 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[16] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux15~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux15~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [16])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [16])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [16]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux15~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[16] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux15~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux15~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux15~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux15~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [16]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux15~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [16])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux15~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [16]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux15~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux15~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux15~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux15~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux15~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux15~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux15~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [16])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [16]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux15~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux15~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux15~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux15~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux15~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux15~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux15~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [16]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux15~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [16])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux15~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [16]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [16]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux15~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux15~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux15~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux15~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux15~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux15~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux15~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [16])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [16]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux15~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux15~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux15~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux15~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]))) # 
// (!\datapath_0|forward_mux_1|Mux15~0_combout  & (\datapath_0|datamem_module_0|output_data [16])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux15~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [16]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux15~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [16]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux15~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux15~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux15~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux15~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux15~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux15~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [16]),
	.datab(\datapath_0|forward_mux_1|Mux15~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux15~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux15~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux15~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[16]~16 (
// Equation(s):
// \datapath_0|mux_1|output_0[16]~16_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux15~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [16]),
	.datab(\datapath_0|forward_mux_1|Mux15~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[16]~16_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[16]~16 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[16]~16 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [17]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[17] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux14~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux14~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [17])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [17])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [17]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux14~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux14~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux14~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[17] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux14~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux14~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux14~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux14~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [17]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux14~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [17])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux14~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [17]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux14~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux14~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux14~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux14~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux14~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux14~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux14~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [17])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [17]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux14~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux14~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux14~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux14~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux14~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux14~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux14~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [17]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux14~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [17])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux14~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [17]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [17]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux14~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux14~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux14~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux14~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[17] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux14~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [17]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[17] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[17] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux14~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux14~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [17])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [17])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [17]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux14~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux14~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux14~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux14~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux14~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux14~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]))) # 
// (!\datapath_0|forward_mux_1|Mux14~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux14~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [17]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux14~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [17]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux14~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux14~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux14~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[17]~17 (
// Equation(s):
// \datapath_0|mux_1|output_0[17]~17_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux14~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [17]),
	.datab(\datapath_0|forward_mux_1|Mux14~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[17]~17_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[17]~17 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[17]~17 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~2 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~2_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [18] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [18]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~2 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[2] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [2] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~2_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [2])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~2_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[2] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[2] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~390 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~390_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~390_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~390 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~390 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~391 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~391_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~390_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~390_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~390_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~390_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~391_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~391 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~391 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~392 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~392_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~392_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~392 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~392 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~393 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~393_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~392_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~392_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~392_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~392_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~393_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~393 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~393 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~394 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~394_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~391_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~393_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~391_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~393_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~394_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~394 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~394 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~395 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~395_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~395_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~395 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~395 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~396 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~396_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~395_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~395_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~395_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~395_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~396_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~396 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~396 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~397 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~397_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~394_combout  & ((\datapath_0|datamem_module_0|output_data~396_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~394_combout  & (\datapath_0|datamem_module_0|output_data~389_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~394_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~389_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~394_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~396_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~397_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~397 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~397 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~398 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~398_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~387_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~397_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~387_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~397_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~398_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~398 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~398 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[18] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [18] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [18]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~398_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~398_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [18]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [18]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[18] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[18] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [18]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[18] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux13~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux13~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [18])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [18])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [18]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux13~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux13~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux13~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[18] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux13~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux13~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux13~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux13~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [18]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux13~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [18])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux13~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [18]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux13~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux13~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux13~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux13~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux13~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux13~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux13~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [18])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [18]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux13~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux13~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux13~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux13~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux13~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux13~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux13~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [18]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux13~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [18])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux13~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [18]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [18]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux13~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux13~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux13~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux13~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[18] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux13~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [18]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[18] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[18] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux13~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux13~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [18])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [18]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux13~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux13~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux13~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux13~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux13~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux13~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]))) # 
// (!\datapath_0|forward_mux_1|Mux13~0_combout  & (\datapath_0|datamem_module_0|output_data [18])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux13~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [18]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux13~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [18]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux13~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux13~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux13~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[18]~18 (
// Equation(s):
// \datapath_0|mux_1|output_0[18]~18_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux13~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [18]),
	.datab(\datapath_0|forward_mux_1|Mux13~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[18]~18_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[18]~18 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[18]~18 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [19]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[19] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux12~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux12~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [19])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [19])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [19]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux12~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux12~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux12~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[19] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux12~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux12~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux12~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux12~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [19]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux12~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [19])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux12~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [19]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux12~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux12~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux12~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux12~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux12~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux12~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux12~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [19])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [19]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux12~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux12~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux12~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux12~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux12~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux12~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux12~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [19]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux12~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [19])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux12~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [19]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [19]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux12~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux12~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux12~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux12~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[19] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux12~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [19]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[19] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[19] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux12~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux12~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [19])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [19])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [19]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux12~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux12~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux12~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux12~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux12~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux12~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]))) # 
// (!\datapath_0|forward_mux_1|Mux12~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux12~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [19]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux12~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [19]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux12~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux12~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux12~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[19]~19 (
// Equation(s):
// \datapath_0|mux_1|output_0[19]~19_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux12~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [19]),
	.datab(\datapath_0|forward_mux_1|Mux12~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[19]~19_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[19]~19 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[19]~19 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[20] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux11~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux11~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [20])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [20])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [20]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux11~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[20] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux11~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux11~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux11~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux11~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [20]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux11~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [20])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux11~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [20]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux11~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux11~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux11~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux11~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux11~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux11~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux11~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [20])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [20]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux11~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux11~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux11~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux11~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux11~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux11~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux11~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [20]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux11~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [20])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux11~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [20]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [20]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux11~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux11~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux11~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux11~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[20] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux11~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [20]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[20] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[20] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux11~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux11~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [20])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [20]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux11~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux11~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux11~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux11~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux11~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux11~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]))) # 
// (!\datapath_0|forward_mux_1|Mux11~0_combout  & (\datapath_0|datamem_module_0|output_data [20])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux11~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [20]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux11~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [20]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux11~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux11~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux11~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux11~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux11~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux11~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [20]),
	.datab(\datapath_0|forward_mux_1|Mux11~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux11~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux11~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux11~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[20]~20 (
// Equation(s):
// \datapath_0|mux_1|output_0[20]~20_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux11~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [20]),
	.datab(\datapath_0|forward_mux_1|Mux11~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[20]~20_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[20]~20 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[20]~20 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[21] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux10~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux10~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [21])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [21])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [21]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux10~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[21] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux10~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux10~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux10~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux10~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [21]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux10~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [21])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux10~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [21]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux10~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux10~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux10~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux10~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux10~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux10~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux10~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [21])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [21]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux10~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux10~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux10~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux10~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux10~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux10~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux10~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [21]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux10~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [21])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux10~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [21]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [21]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux10~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux10~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux10~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux10~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[21] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux10~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [21]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[21] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[21] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux10~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux10~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [21])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [21])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [21]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux10~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux10~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux10~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux10~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux10~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux10~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]))) # 
// (!\datapath_0|forward_mux_1|Mux10~0_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux10~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [21]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux10~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [21]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux10~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux10~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux10~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux10~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux10~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux10~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [21]),
	.datab(\datapath_0|forward_mux_1|Mux10~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux10~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux10~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux10~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[21]~21 (
// Equation(s):
// \datapath_0|mux_1|output_0[21]~21_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux10~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [21]),
	.datab(\datapath_0|forward_mux_1|Mux10~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[21]~21_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[21]~21 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[21]~21 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2~6 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2~6_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [22] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [22]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2~6 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_2~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_2[6] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_2 [6] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_2~6_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_2 [6])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_2~6_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_2[6] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_2[6] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~474 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~474_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x6|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x4|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~474_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~474 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~474 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~475 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~475_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~474_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~474_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~474_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x5|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~474_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x7|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~475_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~475 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~475 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~476 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~476_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x1|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x0|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~476_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~476 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~476 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~477 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~477_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~476_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~476_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~476_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x2|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~476_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x3|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~477_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~477 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~477 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~478 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~478_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~475_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~477_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~475_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~477_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~478_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~478 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~478 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~479 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~479_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_2|reg_x14|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x12|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~479_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~479 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~479 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_2 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~480 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~480_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~479_combout  & ((\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~479_combout  & (\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~479_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_2|reg_x13|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~479_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_2|reg_x15|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~480_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~480 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~480 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~481 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~481_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~478_combout  & ((\datapath_0|datamem_module_0|output_data~480_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~478_combout  & (\datapath_0|datamem_module_0|output_data~473_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~478_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~473_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~478_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~480_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~481_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~481 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~481 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~482 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~482_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~471_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~481_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~471_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~481_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~482_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~482 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~482 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[22] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [22] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [22]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~482_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~482_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [22]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [22]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[22] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[22] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [22]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[22] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux9~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux9~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [22])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [22])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [22]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux9~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux9~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[22] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux9~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux9~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux9~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux9~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [22]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux9~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [22])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux9~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [22]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux9~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux9~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux9~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux9~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux9~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux9~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux9~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [22])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [22]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux9~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux9~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux9~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux9~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux9~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux9~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux9~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [22]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux9~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [22])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux9~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [22]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [22]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux9~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux9~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux9~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux9~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[22] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux9~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [22]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[22] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[22] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux9~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux9~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [22])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [22]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux9~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux9~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux9~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux9~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux9~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux9~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]))) # (!\datapath_0|forward_mux_1|Mux9~0_combout  
// & (\datapath_0|datamem_module_0|output_data [22])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux9~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [22]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux9~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [22]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux9~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux9~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux9~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[22]~22 (
// Equation(s):
// \datapath_0|mux_1|output_0[22]~22_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux9~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [22]),
	.datab(\datapath_0|forward_mux_1|Mux9~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[22]~22_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[22]~22 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[22]~22 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[23] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux8~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux8~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [23])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [23])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [23]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux8~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[23] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux8~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux8~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux8~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [23]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux8~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [23])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux8~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [23]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux8~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux8~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux8~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux8~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux8~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [23])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [23]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux8~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux8~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux8~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux8~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux8~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux8~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux8~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [23]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux8~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [23])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux8~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [23]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [23]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux8~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux8~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux8~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux8~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux8~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux8~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux8~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [23])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [23])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [23]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux8~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux8~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux8~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux8~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux8~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux8~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]))) # (!\datapath_0|forward_mux_1|Mux8~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux8~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [23]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux8~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [23]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux8~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux8~2 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux8~2_combout  = (\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & ((\datapath_0|forward_mux_1|Mux8~1_combout )))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [23]),
	.datab(\datapath_0|forward_mux_1|Mux8~1_combout ),
	.datac(gnd),
	.datad(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux8~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux8~2 .lut_mask = 16'hAACC;
defparam \datapath_0|forward_mux_1|Mux8~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[23]~23 (
// Equation(s):
// \datapath_0|mux_1|output_0[23]~23_combout  = (\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & (\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23])) # (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux8~2_combout )))

	.dataa(\datapath_0|ID_EX_PLR|immediate_reg|internal_value [23]),
	.datab(\datapath_0|forward_mux_1|Mux8~2_combout ),
	.datac(gnd),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[23]~23_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[23]~23 .lut_mask = 16'hAACC;
defparam \datapath_0|mux_1|output_0[23]~23 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~0 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~0_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [24] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [24]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~0 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[0] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [0] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~0_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [0])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~0_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[0] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[0] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~516 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~516_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~516_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~516 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~516 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~517 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~517_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~516_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~516_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~516_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~516_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~517_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~517 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~517 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~518 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~518_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~518_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~518 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~518 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~519 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~519_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~518_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~518_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~518_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~518_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~519_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~519 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~519 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~520 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~520_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~517_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~519_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~517_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~519_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~520_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~520 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~520 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[0] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~521 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~521_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [0])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [0])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [0]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~521_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~521 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~521 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[0] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [0]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~522 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~522_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~521_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [0]))) # 
// (!\datapath_0|datamem_module_0|output_data~521_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [0])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~521_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [0]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~521_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [0]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~522_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~522 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~522 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~523 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~523_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~520_combout  & ((\datapath_0|datamem_module_0|output_data~522_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~520_combout  & (\datapath_0|datamem_module_0|output_data~515_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~520_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~515_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~520_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~522_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~523_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~523 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~523 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~524 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~524_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~513_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~523_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~513_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~523_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~524_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~524 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~524 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[24] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [24] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [24]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~524_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~524_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [24]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [24]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[24] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[24] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [24]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[24] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux7~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux7~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [24])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [24])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [24]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux7~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux7~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[24] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux7~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux7~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux7~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux7~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [24]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux7~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [24])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux7~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [24]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux7~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux7~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux7~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux7~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux7~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux7~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [24])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [24]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux7~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux7~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux7~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux7~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux7~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux7~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux7~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [24]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux7~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [24])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux7~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [24]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [24]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux7~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux7~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux7~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux7~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[24] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux7~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [24]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[24] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[24] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux7~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux7~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [24])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [24]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux7~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux7~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux7~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux7~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux7~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux7~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]))) # (!\datapath_0|forward_mux_1|Mux7~0_combout  
// & (\datapath_0|datamem_module_0|output_data [24])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux7~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [24]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux7~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [24]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux7~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux7~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux7~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[24]~24 (
// Equation(s):
// \datapath_0|mux_1|output_0[24]~24_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux7~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [24]),
	.datab(\datapath_0|forward_mux_1|Mux7~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[24]~24_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[24]~24 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[24]~24 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [25]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[25] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux6~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux6~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [25])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [25])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [25]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux6~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux6~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux6~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[25] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux6~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux6~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux6~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux6~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [25]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux6~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [25])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux6~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [25]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux6~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux6~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux6~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux6~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux6~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux6~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux6~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [25])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [25]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux6~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux6~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux6~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux6~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux6~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux6~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux6~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [25]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux6~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [25])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux6~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [25]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [25]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux6~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux6~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux6~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux6~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[25] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux6~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [25]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[25] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[25] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux6~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux6~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [25])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [25])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [25]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux6~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux6~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux6~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux6~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux6~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux6~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]))) # (!\datapath_0|forward_mux_1|Mux6~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux6~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [25]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux6~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [25]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux6~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux6~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux6~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[25]~25 (
// Equation(s):
// \datapath_0|mux_1|output_0[25]~25_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux6~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [25]),
	.datab(\datapath_0|forward_mux_1|Mux6~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[25]~25_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[25]~25 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[25]~25 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~2 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~2_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [26] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [26]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~2 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[2] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [2] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~2_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [2])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~2_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[2] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[2] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~558 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~558_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~558_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~558 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~558 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~559 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~559_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~558_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~558_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~558_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~558_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~559_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~559 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~559 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~560 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~560_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~560_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~560 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~560 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~561 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~561_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~560_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~560_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~560_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~560_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~561_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~561 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~561 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~562 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~562_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~559_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~561_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~559_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~561_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~562_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~562 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~562 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[2] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~563 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~563_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [2])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [2])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [2]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~563_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~563 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~563 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[2] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [2]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~564 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~564_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~563_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [2]))) # 
// (!\datapath_0|datamem_module_0|output_data~563_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~563_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [2]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~563_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~564_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~564 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~564 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~565 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~565_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~562_combout  & ((\datapath_0|datamem_module_0|output_data~564_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~562_combout  & (\datapath_0|datamem_module_0|output_data~557_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~562_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~557_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~562_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~564_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~565_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~565 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~565 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~566 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~566_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~555_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~565_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~555_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~565_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~566_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~566 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~566 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[26] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [26] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [26]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~566_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~566_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [26]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [26]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[26] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[26] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [26]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[26] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux5~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux5~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [26])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [26])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [26]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux5~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux5~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux5~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[26] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux5~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux5~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux5~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux5~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [26]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux5~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [26])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux5~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [26]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux5~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux5~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux5~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux5~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux5~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux5~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux5~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [26])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [26]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux5~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux5~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux5~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux5~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux5~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux5~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux5~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [26]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux5~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [26])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux5~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [26]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [26]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux5~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux5~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux5~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux5~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[26] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux5~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [26]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[26] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[26] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux5~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux5~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [26])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [26]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux5~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux5~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux5~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux5~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux5~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux5~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]))) # (!\datapath_0|forward_mux_1|Mux5~0_combout  
// & (\datapath_0|datamem_module_0|output_data [26])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux5~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [26]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux5~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [26]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux5~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux5~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux5~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[26]~26 (
// Equation(s):
// \datapath_0|mux_1|output_0[26]~26_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux5~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [26]),
	.datab(\datapath_0|forward_mux_1|Mux5~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[26]~26_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[26]~26 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[26]~26 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [27]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[27] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux4~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux4~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [27])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [27])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [27]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux4~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux4~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux4~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[27] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux4~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux4~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux4~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux4~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [27]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux4~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [27])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux4~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [27]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux4~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux4~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux4~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux4~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux4~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux4~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux4~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [27])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [27]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux4~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux4~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux4~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux4~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux4~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux4~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux4~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [27]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux4~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [27])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux4~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [27]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [27]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux4~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux4~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux4~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux4~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[27] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux4~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [27]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[27] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[27] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux4~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux4~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [27])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [27])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [27]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux4~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux4~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux4~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux4~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux4~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux4~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]))) # (!\datapath_0|forward_mux_1|Mux4~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux4~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [27]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux4~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [27]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux4~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux4~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux4~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[27]~27 (
// Equation(s):
// \datapath_0|mux_1|output_0[27]~27_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux4~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [27]),
	.datab(\datapath_0|forward_mux_1|Mux4~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[27]~27_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[27]~27 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[27]~27 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~4 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~4_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [28] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [28]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~4_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~4 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~4 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[4] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [4] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~4_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [4])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~4_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[4] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[4] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~600 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~600_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~600_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~600 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~600 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~601 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~601_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~600_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~600_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~600_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~600_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~601_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~601 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~601 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~602 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~602_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~602_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~602 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~602 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~603 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~603_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~602_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~602_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~602_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~602_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~603_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~603 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~603 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~604 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~604_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~601_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~603_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~601_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~603_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~604_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~604 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~604 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[4] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~605 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~605_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [4])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [4])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [4]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~605_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~605 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~605 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[4] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [4]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [4]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[4] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[4] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~606 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~606_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~605_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [4]))) # 
// (!\datapath_0|datamem_module_0|output_data~605_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~605_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [4]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~605_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~606_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~606 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~606 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~607 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~607_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~604_combout  & ((\datapath_0|datamem_module_0|output_data~606_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~604_combout  & (\datapath_0|datamem_module_0|output_data~599_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~604_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~599_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~604_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~606_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~607_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~607 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~607 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~608 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~608_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~597_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~607_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~597_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~607_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~608_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~608 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~608 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[28] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [28] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [28]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~608_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~608_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [28]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [28]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[28] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[28] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [28]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[28] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux3~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux3~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [28])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [28])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [28]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux3~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux3~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[28] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux3~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux3~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux3~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux3~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [28]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux3~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [28])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux3~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [28]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux3~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux3~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux3~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux3~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux3~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux3~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [28])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [28]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux3~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux3~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux3~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux3~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux3~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux3~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux3~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [28]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux3~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [28])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux3~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [28]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [28]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux3~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux3~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux3~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux3~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[28] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux3~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [28]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[28] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[28] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux3~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux3~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [28])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [28]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux3~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux3~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux3~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux3~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux3~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux3~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]))) # (!\datapath_0|forward_mux_1|Mux3~0_combout  
// & (\datapath_0|datamem_module_0|output_data [28])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux3~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [28]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux3~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [28]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux3~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux3~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux3~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[28]~28 (
// Equation(s):
// \datapath_0|mux_1|output_0[28]~28_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux3~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [28]),
	.datab(\datapath_0|forward_mux_1|Mux3~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[28]~28_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[28]~28 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[28]~28 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [29]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[29] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux2~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux2~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [29])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [29])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [29]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux2~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux2~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[29] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux2~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux2~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux2~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux2~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [29]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux2~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [29])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux2~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [29]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux2~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux2~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux2~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux2~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux2~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux2~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [29])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [29]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux2~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux2~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux2~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux2~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux2~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux2~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux2~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [29]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux2~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [29])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux2~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [29]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [29]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux2~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux2~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux2~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux2~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[29] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux2~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [29]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[29] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[29] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux2~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux2~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [29])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [29])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [29]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux2~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux2~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux2~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux2~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux2~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux2~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]))) # (!\datapath_0|forward_mux_1|Mux2~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux2~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [29]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux2~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [29]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux2~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux2~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux2~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[29]~29 (
// Equation(s):
// \datapath_0|mux_1|output_0[29]~29_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux2~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [29]),
	.datab(\datapath_0|forward_mux_1|Mux2~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[29]~29_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[29]~29 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[29]~29 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3~6 (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3~6_combout  = (\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [30] & (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0] & !\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]))

	.dataa(\datapath_0|EX_MEM_PLR|register_file_output_1_reg|internal_value [30]),
	.datab(gnd),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [0]),
	.datad(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3~6_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3~6 .lut_mask = 16'h000A;
defparam \datapath_0|datamem_module_0|memory_input_3~6 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|memory_input_3[6] (
// Equation(s):
// \datapath_0|datamem_module_0|memory_input_3 [6] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & (\datapath_0|datamem_module_0|memory_input_3~6_combout )) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// ((\datapath_0|datamem_module_0|memory_input_3 [6])))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|memory_input_3~6_combout ),
	.datac(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|memory_input_3[6] .lut_mask = 16'hCCF0;
defparam \datapath_0|datamem_module_0|memory_input_3[6] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[6]~21_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[4]~22_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~642 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~642_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x6|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x4|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~642_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~642 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~642 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[7]~23_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~643 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~643_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~642_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~642_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~642_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x5|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~642_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x7|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~643_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~643 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~643 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[1]~25_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[0]~26_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~644 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~644_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value 
// [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x1|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x0|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~644_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~644 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~644 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[3]~27_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~645 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~645_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & ((\datapath_0|datamem_module_0|output_data~644_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~644_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (((\datapath_0|datamem_module_0|output_data~644_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x2|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datac(\datapath_0|datamem_module_0|output_data~644_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x3|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~645_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~645 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~645 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~646 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~646_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & (\datapath_0|datamem_module_0|output_data~643_combout )) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4] & ((\datapath_0|datamem_module_0|output_data~645_combout )))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datab(\datapath_0|datamem_module_0|output_data~643_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [4]),
	.datad(\datapath_0|datamem_module_0|output_data~645_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~646_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~646 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~646 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[14]~29_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value[6] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[12]~30_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~647 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~647_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & 
// ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & (\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [6])) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3] & 
// ((\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [6])))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datab(\datapath_0|datamem_module_0|datamem_3|reg_x14|internal_value [6]),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [3]),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x12|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~647_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~647 .lut_mask = 16'hE5E0;
defparam \datapath_0|datamem_module_0|output_data~647 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[6] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|datamem_module_0|memory_input_3 [6]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|datamem_module_0|datamem_0|internal_reg_load[15]~31_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [6]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[6] .is_wysiwyg = "true";
defparam \datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value[6] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~648 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~648_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & ((\datapath_0|datamem_module_0|output_data~647_combout  & ((\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [6]))) # 
// (!\datapath_0|datamem_module_0|output_data~647_combout  & (\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [6])))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2] & (((\datapath_0|datamem_module_0|output_data~647_combout ))))

	.dataa(\datapath_0|datamem_module_0|datamem_3|reg_x13|internal_value [6]),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [2]),
	.datac(\datapath_0|datamem_module_0|output_data~647_combout ),
	.datad(\datapath_0|datamem_module_0|datamem_3|reg_x15|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~648_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~648 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~648 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~649 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~649_combout  = (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & ((\datapath_0|datamem_module_0|output_data~646_combout  & ((\datapath_0|datamem_module_0|output_data~648_combout ))) # 
// (!\datapath_0|datamem_module_0|output_data~646_combout  & (\datapath_0|datamem_module_0|output_data~641_combout )))) # (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5] & (((\datapath_0|datamem_module_0|output_data~646_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data~641_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [5]),
	.datac(\datapath_0|datamem_module_0|output_data~646_combout ),
	.datad(\datapath_0|datamem_module_0|output_data~648_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~649_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~649 .lut_mask = 16'hF838;
defparam \datapath_0|datamem_module_0|output_data~649 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data~650 (
// Equation(s):
// \datapath_0|datamem_module_0|output_data~650_combout  = (!\datapath_0|datamem_module_0|Equal0~0_combout  & ((\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & (\datapath_0|datamem_module_0|output_data~639_combout )) # 
// (!\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6] & ((\datapath_0|datamem_module_0|output_data~649_combout )))))

	.dataa(\datapath_0|datamem_module_0|output_data~639_combout ),
	.datab(\datapath_0|datamem_module_0|output_data~649_combout ),
	.datac(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [6]),
	.datad(\datapath_0|datamem_module_0|Equal0~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data~650_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data~650 .lut_mask = 16'h00AC;
defparam \datapath_0|datamem_module_0|output_data~650 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|datamem_module_0|output_data[30] (
// Equation(s):
// \datapath_0|datamem_module_0|output_data [30] = (\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & ((\datapath_0|datamem_module_0|output_data [30]))) # (!\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q  & 
// (\datapath_0|datamem_module_0|output_data~650_combout ))

	.dataa(gnd),
	.datab(\datapath_0|datamem_module_0|output_data~650_combout ),
	.datac(\datapath_0|datamem_module_0|output_data [30]),
	.datad(\datapath_0|EX_MEM_PLR|datamem_write_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|datamem_module_0|output_data [30]),
	.cout());
// synopsys translate_off
defparam \datapath_0|datamem_module_0|output_data[30] .lut_mask = 16'hF0CC;
defparam \datapath_0|datamem_module_0|output_data[30] .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [30]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x9|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[9]~8_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x9|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x9|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x9|internal_value[30] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux1~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux1~0_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & (((\controller_0|internal_reg_file_read_address_1 [0])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & 
// ((\controller_0|internal_reg_file_read_address_1 [0] & (\datapath_0|register_file_0|reg_x9|internal_value [30])) # (!\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|reg_x8|internal_value [30])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [1]),
	.datab(\datapath_0|register_file_0|reg_x9|internal_value [30]),
	.datac(\controller_0|internal_reg_file_read_address_1 [0]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux1~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux1~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[30] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux1~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux1~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux1~1_combout  = (\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|output_2_mux|Mux1~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [30]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux1~0_combout  & (\datapath_0|register_file_0|reg_x10|internal_value [30])))) # (!\controller_0|internal_reg_file_read_address_1 [1] & (((\datapath_0|register_file_0|output_2_mux|Mux1~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x10|internal_value [30]),
	.datab(\controller_0|internal_reg_file_read_address_1 [1]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux1~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux1~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux1~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux1~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux1~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux1~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [30])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [30]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux1~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux1~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux1~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux1~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux1~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux1~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux1~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [30]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux1~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [30])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux1~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [30]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [30]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux1~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux1~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux1~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux1~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[30] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux1~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [30]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[30] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[30] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux1~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux1~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30])) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [30])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [30]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux1~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux1~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux1~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux1~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux1~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|forward_mux_1|Mux1~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]))) # (!\datapath_0|forward_mux_1|Mux1~0_combout  
// & (\datapath_0|datamem_module_0|output_data [30])))) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (((\datapath_0|forward_mux_1|Mux1~0_combout ))))

	.dataa(\datapath_0|datamem_module_0|output_data [30]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datac(\datapath_0|forward_mux_1|Mux1~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [30]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux1~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux1~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux1~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[30]~30 (
// Equation(s):
// \datapath_0|mux_1|output_0[30]~30_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux1~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [30]),
	.datab(\datapath_0|forward_mux_1|Mux1~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[30]~30_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[30]~30 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[30]~30 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|datamem_module_0|output_data [31]),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x3|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[3]~6_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x3|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x3|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x3|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x10|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[10]~7_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x10|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x10|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x10|internal_value[31] .power_up = "low";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x8|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[8]~9_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x8|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x8|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x8|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux0~0 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux0~0_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & (((\controller_0|internal_reg_file_read_address_1 [1])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & 
// ((\controller_0|internal_reg_file_read_address_1 [1] & (\datapath_0|register_file_0|reg_x10|internal_value [31])) # (!\controller_0|internal_reg_file_read_address_1 [1] & ((\datapath_0|register_file_0|reg_x8|internal_value [31])))))

	.dataa(\controller_0|internal_reg_file_read_address_1 [0]),
	.datab(\datapath_0|register_file_0|reg_x10|internal_value [31]),
	.datac(\controller_0|internal_reg_file_read_address_1 [1]),
	.datad(\datapath_0|register_file_0|reg_x8|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux0~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|register_file_0|output_2_mux|Mux0~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|register_file_0|reg_x11|internal_value[31] (
	.clk(!\clock~input_o ),
	.d(\datapath_0|mux_0|Mux0~1_combout ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\datapath_0|register_file_0|internal_reg_load[11]~10_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|register_file_0|reg_x11|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|register_file_0|reg_x11|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|register_file_0|reg_x11|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux0~1 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux0~1_combout  = (\controller_0|internal_reg_file_read_address_1 [0] & ((\datapath_0|register_file_0|output_2_mux|Mux0~0_combout  & ((\datapath_0|register_file_0|reg_x11|internal_value [31]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux0~0_combout  & (\datapath_0|register_file_0|reg_x9|internal_value [31])))) # (!\controller_0|internal_reg_file_read_address_1 [0] & (((\datapath_0|register_file_0|output_2_mux|Mux0~0_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x9|internal_value [31]),
	.datab(\controller_0|internal_reg_file_read_address_1 [0]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux0~0_combout ),
	.datad(\datapath_0|register_file_0|reg_x11|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux0~1 .lut_mask = 16'hF838;
defparam \datapath_0|register_file_0|output_2_mux|Mux0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux0~2 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux0~2_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux0~1_combout ))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux20~2_combout  & (\datapath_0|register_file_0|reg_x1|internal_value [31])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~1_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x1|internal_value [31]),
	.datab(\datapath_0|register_file_0|output_2_mux|Mux0~1_combout ),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~1_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux20~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux0~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux0~2 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux0~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|register_file_0|output_2_mux|Mux0~3 (
// Equation(s):
// \datapath_0|register_file_0|output_2_mux|Mux0~3_combout  = (\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & ((\datapath_0|register_file_0|output_2_mux|Mux0~2_combout  & ((\datapath_0|register_file_0|reg_x3|internal_value [31]))) # 
// (!\datapath_0|register_file_0|output_2_mux|Mux0~2_combout  & (\datapath_0|register_file_0|reg_x2|internal_value [31])))) # (!\datapath_0|register_file_0|output_2_mux|Mux20~0_combout  & (((\datapath_0|register_file_0|output_2_mux|Mux0~2_combout ))))

	.dataa(\datapath_0|register_file_0|reg_x2|internal_value [31]),
	.datab(\datapath_0|register_file_0|reg_x3|internal_value [31]),
	.datac(\datapath_0|register_file_0|output_2_mux|Mux20~0_combout ),
	.datad(\datapath_0|register_file_0|output_2_mux|Mux0~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|register_file_0|output_2_mux|Mux0~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|register_file_0|output_2_mux|Mux0~3 .lut_mask = 16'hCFA0;
defparam \datapath_0|register_file_0|output_2_mux|Mux0~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[31] (
	.clk(\clock~input_o ),
	.d(\datapath_0|register_file_0|output_2_mux|Mux0~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [31]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[31] .is_wysiwyg = "true";
defparam \datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value[31] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux0~0 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux0~0_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout )))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & 
// ((\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & (\datapath_0|datamem_module_0|output_data [31])) # (!\datapath_0|FU_0|forward_mux_1_control[1]~0_combout  & ((\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [31])))))

	.dataa(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datab(\datapath_0|datamem_module_0|output_data [31]),
	.datac(\datapath_0|FU_0|forward_mux_1_control[1]~0_combout ),
	.datad(\datapath_0|ID_EX_PLR|register_file_output_1_reg|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux0~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux0~0 .lut_mask = 16'hE5E0;
defparam \datapath_0|forward_mux_1|Mux0~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|forward_mux_1|Mux0~1 (
// Equation(s):
// \datapath_0|forward_mux_1|Mux0~1_combout  = (\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & ((\datapath_0|forward_mux_1|Mux0~0_combout  & ((\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]))) # (!\datapath_0|forward_mux_1|Mux0~0_combout  
// & (\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31])))) # (!\datapath_0|FU_0|forward_mux_1_control[0]~1_combout  & (((\datapath_0|forward_mux_1|Mux0~0_combout ))))

	.dataa(\datapath_0|EX_MEM_PLR|ALU_output_reg|internal_value [31]),
	.datab(\datapath_0|FU_0|forward_mux_1_control[0]~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux0~0_combout ),
	.datad(\datapath_0|MEM_WB_PLR|ALU_output_reg|internal_value [31]),
	.cin(gnd),
	.combout(\datapath_0|forward_mux_1|Mux0~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|forward_mux_1|Mux0~1 .lut_mask = 16'hF838;
defparam \datapath_0|forward_mux_1|Mux0~1 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|mux_1|output_0[31]~31 (
// Equation(s):
// \datapath_0|mux_1|output_0[31]~31_combout  = (!\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q  & ((\datapath_0|forward_mux_1|Mux31~2_combout  & (\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31])) # (!\datapath_0|forward_mux_1|Mux31~2_combout  & 
// ((\datapath_0|forward_mux_1|Mux0~1_combout )))))

	.dataa(\datapath_0|MEM_WB_PLR|datamem_output_reg|internal_value [31]),
	.datab(\datapath_0|forward_mux_1|Mux0~1_combout ),
	.datac(\datapath_0|forward_mux_1|Mux31~2_combout ),
	.datad(\datapath_0|ID_EX_PLR|mux1_sel_reg|reg_out~q ),
	.cin(gnd),
	.combout(\datapath_0|mux_1|output_0[31]~31_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|mux_1|output_0[31]~31 .lut_mask = 16'h00AC;
defparam \datapath_0|mux_1|output_0[31]~31 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_0~3 (
// Equation(s):
// \datapath_0|FU_0|forward_0~3_combout  = (\datapath_0|register_file_0|internal_reg_load[11]~1_combout  & (\datapath_0|FU_0|forward_0~0_combout  & (!\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3] & 
// !\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1])))

	.dataa(\datapath_0|register_file_0|internal_reg_load[11]~1_combout ),
	.datab(\datapath_0|FU_0|forward_0~0_combout ),
	.datac(\datapath_0|MEM_WB_PLR|reg_file_write_address_reg|internal_value [3]),
	.datad(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_0~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_0~3 .lut_mask = 16'h0008;
defparam \datapath_0|FU_0|forward_0~3 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_1~7 (
// Equation(s):
// \datapath_0|FU_0|forward_1~7_combout  = (\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q  & !\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1])

	.dataa(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_1~7_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_1~7 .lut_mask = 16'h00AA;
defparam \datapath_0|FU_0|forward_1~7 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|Equal2~2 (
// Equation(s):
// \datapath_0|FU_0|Equal2~2_combout  = (\datapath_0|FU_0|Equal2~0_combout  & (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3] & (!\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4] & 
// !\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2])))

	.dataa(\datapath_0|FU_0|Equal2~0_combout ),
	.datab(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [3]),
	.datac(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [4]),
	.datad(\datapath_0|EX_MEM_PLR|reg_file_write_address_reg|internal_value [2]),
	.cin(gnd),
	.combout(\datapath_0|FU_0|Equal2~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|Equal2~2 .lut_mask = 16'h0002;
defparam \datapath_0|FU_0|Equal2~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_0_control[2]~2 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_0_control[2]~2_combout  = (\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|FU_0|forward_0~3_combout  & ((!\datapath_0|FU_0|Equal2~2_combout ) # (!\datapath_0|FU_0|forward_1~7_combout ))))

	.dataa(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datab(\datapath_0|FU_0|forward_0~3_combout ),
	.datac(\datapath_0|FU_0|forward_1~7_combout ),
	.datad(\datapath_0|FU_0|Equal2~2_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_0_control[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_0_control[2]~2 .lut_mask = 16'h0888;
defparam \datapath_0|FU_0|forward_mux_0_control[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_1_control[2]~2 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_1_control[2]~2_combout  = (\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]) # (((!\datapath_0|FU_0|Equal7~1_combout ) # (!\datapath_0|FU_0|Equal7~0_combout )) # (!\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ))

	.dataa(\datapath_0|EX_MEM_PLR|mux0_sel_reg|internal_value [1]),
	.datab(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.datac(\datapath_0|FU_0|Equal7~0_combout ),
	.datad(\datapath_0|FU_0|Equal7~1_combout ),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_1_control[2]~2_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_1_control[2]~2 .lut_mask = 16'hBFFF;
defparam \datapath_0|FU_0|forward_mux_1_control[2]~2 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|FU_0|forward_mux_1_control[2]~3 (
// Equation(s):
// \datapath_0|FU_0|forward_mux_1_control[2]~3_combout  = (\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0] & (\datapath_0|FU_0|forward_1~6_combout  & \datapath_0|FU_0|forward_mux_1_control[2]~2_combout ))

	.dataa(\datapath_0|MEM_WB_PLR|mux0_sel_reg|internal_value [0]),
	.datab(\datapath_0|FU_0|forward_1~6_combout ),
	.datac(\datapath_0|FU_0|forward_mux_1_control[2]~2_combout ),
	.datad(gnd),
	.cin(gnd),
	.combout(\datapath_0|FU_0|forward_mux_1_control[2]~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|FU_0|forward_mux_1_control[2]~3 .lut_mask = 16'h8080;
defparam \datapath_0|FU_0|forward_mux_1_control[2]~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out (
	.clk(\clock~input_o ),
	.d(\datapath_0|EX_MEM_PLR|reg_file_write_reg|reg_out~q ),
	.asdata(vcc),
	.clrn(!\reset~input_o ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out~q ),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out .is_wysiwyg = "true";
defparam \datapath_0|MEM_WB_PLR|reg_file_write_reg|reg_out .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & ((\datapath_0|program_counter_0|internal_register|internal_value [2]) # 
// (!\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout )))

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datac(gnd),
	.datad(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1 .lut_mask = 16'h88AA;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[0] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [0]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[0] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[0] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0_combout  = (!\datapath_0|program_counter_0|internal_register|internal_value [5] & (!\datapath_0|program_counter_0|internal_register|internal_value [6] & 
// ((!\datapath_0|program_counter_0|internal_register|internal_value [3]) # (!\datapath_0|program_counter_0|internal_register|internal_value [2]))))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [5]),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [6]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0 .lut_mask = 16'h0007;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0 .sum_lutc_input = "datac";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [4] & (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & 
// !\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0_combout ))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datab(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datac(gnd),
	.datad(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1 .lut_mask = 16'h0088;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[2] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux29~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [2]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[2] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[2] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3_combout  = (\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1] & !\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout )

	.dataa(\datapath_0|progmem_module_0|progmem_0|reg_x10|internal_value [1]),
	.datab(gnd),
	.datac(gnd),
	.datad(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3 .lut_mask = 16'h00AA;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[5] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux31~3_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [5]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[5] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[5] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [2] & (\datapath_0|program_counter_0|internal_register|internal_value [3] & 
// (\datapath_0|program_counter_0|internal_register|internal_value [4] & \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout )))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.datad(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1 .lut_mask = 16'h8000;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[23] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~1_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [23]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[23] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[23] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [2] & (\datapath_0|program_counter_0|internal_register|internal_value [3] & 
// (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & !\datapath_0|program_counter_0|internal_register|internal_value [4])))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.datac(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [4]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0 .lut_mask = 16'h0080;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[15] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux16~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [15]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[15] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[15] .power_up = "low";
// synopsys translate_on

cycloneiv_lcell_comb \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0 (
// Equation(s):
// \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0_combout  = (\datapath_0|program_counter_0|internal_register|internal_value [2] & (\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout  & 
// !\datapath_0|program_counter_0|internal_register|internal_value [3]))

	.dataa(\datapath_0|program_counter_0|internal_register|internal_value [2]),
	.datab(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux8~0_combout ),
	.datac(gnd),
	.datad(\datapath_0|program_counter_0|internal_register|internal_value [3]),
	.cin(gnd),
	.combout(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0_combout ),
	.cout());
// synopsys translate_off
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0 .lut_mask = 16'h0088;
defparam \datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0 .sum_lutc_input = "datac";
// synopsys translate_on

dffeas \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[16] (
	.clk(\clock~input_o ),
	.d(\datapath_0|progmem_module_0|progmem_0|output_1_mux|Mux15~0_combout ),
	.asdata(vcc),
	.clrn(!\datapath_0|comb~3_combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\datapath_0|IF_ID_PLR|instruction_data_reg|internal_value [16]),
	.prn(vcc));
// synopsys translate_off
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[16] .is_wysiwyg = "true";
defparam \datapath_0|IF_ID_PLR|instruction_data_reg|internal_value[16] .power_up = "low";
// synopsys translate_on

assign debug_pc_output[0] = \debug_pc_output[0]~output_o ;

assign debug_pc_output[1] = \debug_pc_output[1]~output_o ;

assign debug_pc_output[2] = \debug_pc_output[2]~output_o ;

assign debug_pc_output[3] = \debug_pc_output[3]~output_o ;

assign debug_pc_output[4] = \debug_pc_output[4]~output_o ;

assign debug_pc_output[5] = \debug_pc_output[5]~output_o ;

assign debug_pc_output[6] = \debug_pc_output[6]~output_o ;

assign debug_pc_output[7] = \debug_pc_output[7]~output_o ;

assign debug_pc_output[8] = \debug_pc_output[8]~output_o ;

assign debug_pc_output[9] = \debug_pc_output[9]~output_o ;

assign debug_pc_output[10] = \debug_pc_output[10]~output_o ;

assign debug_pc_output[11] = \debug_pc_output[11]~output_o ;

assign debug_pc_output[12] = \debug_pc_output[12]~output_o ;

assign debug_pc_output[13] = \debug_pc_output[13]~output_o ;

assign debug_pc_output[14] = \debug_pc_output[14]~output_o ;

assign debug_pc_output[15] = \debug_pc_output[15]~output_o ;

assign debug_pc_output[16] = \debug_pc_output[16]~output_o ;

assign debug_pc_output[17] = \debug_pc_output[17]~output_o ;

assign debug_pc_output[18] = \debug_pc_output[18]~output_o ;

assign debug_pc_output[19] = \debug_pc_output[19]~output_o ;

assign debug_pc_output[20] = \debug_pc_output[20]~output_o ;

assign debug_pc_output[21] = \debug_pc_output[21]~output_o ;

assign debug_pc_output[22] = \debug_pc_output[22]~output_o ;

assign debug_pc_output[23] = \debug_pc_output[23]~output_o ;

assign debug_pc_output[24] = \debug_pc_output[24]~output_o ;

assign debug_pc_output[25] = \debug_pc_output[25]~output_o ;

assign debug_pc_output[26] = \debug_pc_output[26]~output_o ;

assign debug_pc_output[27] = \debug_pc_output[27]~output_o ;

assign debug_pc_output[28] = \debug_pc_output[28]~output_o ;

assign debug_pc_output[29] = \debug_pc_output[29]~output_o ;

assign debug_pc_output[30] = \debug_pc_output[30]~output_o ;

assign debug_pc_output[31] = \debug_pc_output[31]~output_o ;

assign debug_regfile_x31_output[0] = \debug_regfile_x31_output[0]~output_o ;

assign debug_regfile_x31_output[1] = \debug_regfile_x31_output[1]~output_o ;

assign debug_regfile_x31_output[2] = \debug_regfile_x31_output[2]~output_o ;

assign debug_regfile_x31_output[3] = \debug_regfile_x31_output[3]~output_o ;

assign debug_regfile_x31_output[4] = \debug_regfile_x31_output[4]~output_o ;

assign debug_regfile_x31_output[5] = \debug_regfile_x31_output[5]~output_o ;

assign debug_regfile_x31_output[6] = \debug_regfile_x31_output[6]~output_o ;

assign debug_regfile_x31_output[7] = \debug_regfile_x31_output[7]~output_o ;

assign debug_regfile_x31_output[8] = \debug_regfile_x31_output[8]~output_o ;

assign debug_regfile_x31_output[9] = \debug_regfile_x31_output[9]~output_o ;

assign debug_regfile_x31_output[10] = \debug_regfile_x31_output[10]~output_o ;

assign debug_regfile_x31_output[11] = \debug_regfile_x31_output[11]~output_o ;

assign debug_regfile_x31_output[12] = \debug_regfile_x31_output[12]~output_o ;

assign debug_regfile_x31_output[13] = \debug_regfile_x31_output[13]~output_o ;

assign debug_regfile_x31_output[14] = \debug_regfile_x31_output[14]~output_o ;

assign debug_regfile_x31_output[15] = \debug_regfile_x31_output[15]~output_o ;

assign debug_regfile_x31_output[16] = \debug_regfile_x31_output[16]~output_o ;

assign debug_regfile_x31_output[17] = \debug_regfile_x31_output[17]~output_o ;

assign debug_regfile_x31_output[18] = \debug_regfile_x31_output[18]~output_o ;

assign debug_regfile_x31_output[19] = \debug_regfile_x31_output[19]~output_o ;

assign debug_regfile_x31_output[20] = \debug_regfile_x31_output[20]~output_o ;

assign debug_regfile_x31_output[21] = \debug_regfile_x31_output[21]~output_o ;

assign debug_regfile_x31_output[22] = \debug_regfile_x31_output[22]~output_o ;

assign debug_regfile_x31_output[23] = \debug_regfile_x31_output[23]~output_o ;

assign debug_regfile_x31_output[24] = \debug_regfile_x31_output[24]~output_o ;

assign debug_regfile_x31_output[25] = \debug_regfile_x31_output[25]~output_o ;

assign debug_regfile_x31_output[26] = \debug_regfile_x31_output[26]~output_o ;

assign debug_regfile_x31_output[27] = \debug_regfile_x31_output[27]~output_o ;

assign debug_regfile_x31_output[28] = \debug_regfile_x31_output[28]~output_o ;

assign debug_regfile_x31_output[29] = \debug_regfile_x31_output[29]~output_o ;

assign debug_regfile_x31_output[30] = \debug_regfile_x31_output[30]~output_o ;

assign debug_regfile_x31_output[31] = \debug_regfile_x31_output[31]~output_o ;

assign debug_regfile_x1_output[0] = \debug_regfile_x1_output[0]~output_o ;

assign debug_regfile_x1_output[1] = \debug_regfile_x1_output[1]~output_o ;

assign debug_regfile_x1_output[2] = \debug_regfile_x1_output[2]~output_o ;

assign debug_regfile_x1_output[3] = \debug_regfile_x1_output[3]~output_o ;

assign debug_regfile_x1_output[4] = \debug_regfile_x1_output[4]~output_o ;

assign debug_regfile_x1_output[5] = \debug_regfile_x1_output[5]~output_o ;

assign debug_regfile_x1_output[6] = \debug_regfile_x1_output[6]~output_o ;

assign debug_regfile_x1_output[7] = \debug_regfile_x1_output[7]~output_o ;

assign debug_regfile_x1_output[8] = \debug_regfile_x1_output[8]~output_o ;

assign debug_regfile_x1_output[9] = \debug_regfile_x1_output[9]~output_o ;

assign debug_regfile_x1_output[10] = \debug_regfile_x1_output[10]~output_o ;

assign debug_regfile_x1_output[11] = \debug_regfile_x1_output[11]~output_o ;

assign debug_regfile_x1_output[12] = \debug_regfile_x1_output[12]~output_o ;

assign debug_regfile_x1_output[13] = \debug_regfile_x1_output[13]~output_o ;

assign debug_regfile_x1_output[14] = \debug_regfile_x1_output[14]~output_o ;

assign debug_regfile_x1_output[15] = \debug_regfile_x1_output[15]~output_o ;

assign debug_regfile_x1_output[16] = \debug_regfile_x1_output[16]~output_o ;

assign debug_regfile_x1_output[17] = \debug_regfile_x1_output[17]~output_o ;

assign debug_regfile_x1_output[18] = \debug_regfile_x1_output[18]~output_o ;

assign debug_regfile_x1_output[19] = \debug_regfile_x1_output[19]~output_o ;

assign debug_regfile_x1_output[20] = \debug_regfile_x1_output[20]~output_o ;

assign debug_regfile_x1_output[21] = \debug_regfile_x1_output[21]~output_o ;

assign debug_regfile_x1_output[22] = \debug_regfile_x1_output[22]~output_o ;

assign debug_regfile_x1_output[23] = \debug_regfile_x1_output[23]~output_o ;

assign debug_regfile_x1_output[24] = \debug_regfile_x1_output[24]~output_o ;

assign debug_regfile_x1_output[25] = \debug_regfile_x1_output[25]~output_o ;

assign debug_regfile_x1_output[26] = \debug_regfile_x1_output[26]~output_o ;

assign debug_regfile_x1_output[27] = \debug_regfile_x1_output[27]~output_o ;

assign debug_regfile_x1_output[28] = \debug_regfile_x1_output[28]~output_o ;

assign debug_regfile_x1_output[29] = \debug_regfile_x1_output[29]~output_o ;

assign debug_regfile_x1_output[30] = \debug_regfile_x1_output[30]~output_o ;

assign debug_regfile_x1_output[31] = \debug_regfile_x1_output[31]~output_o ;

assign debug_regfile_x2_output[0] = \debug_regfile_x2_output[0]~output_o ;

assign debug_regfile_x2_output[1] = \debug_regfile_x2_output[1]~output_o ;

assign debug_regfile_x2_output[2] = \debug_regfile_x2_output[2]~output_o ;

assign debug_regfile_x2_output[3] = \debug_regfile_x2_output[3]~output_o ;

assign debug_regfile_x2_output[4] = \debug_regfile_x2_output[4]~output_o ;

assign debug_regfile_x2_output[5] = \debug_regfile_x2_output[5]~output_o ;

assign debug_regfile_x2_output[6] = \debug_regfile_x2_output[6]~output_o ;

assign debug_regfile_x2_output[7] = \debug_regfile_x2_output[7]~output_o ;

assign debug_regfile_x2_output[8] = \debug_regfile_x2_output[8]~output_o ;

assign debug_regfile_x2_output[9] = \debug_regfile_x2_output[9]~output_o ;

assign debug_regfile_x2_output[10] = \debug_regfile_x2_output[10]~output_o ;

assign debug_regfile_x2_output[11] = \debug_regfile_x2_output[11]~output_o ;

assign debug_regfile_x2_output[12] = \debug_regfile_x2_output[12]~output_o ;

assign debug_regfile_x2_output[13] = \debug_regfile_x2_output[13]~output_o ;

assign debug_regfile_x2_output[14] = \debug_regfile_x2_output[14]~output_o ;

assign debug_regfile_x2_output[15] = \debug_regfile_x2_output[15]~output_o ;

assign debug_regfile_x2_output[16] = \debug_regfile_x2_output[16]~output_o ;

assign debug_regfile_x2_output[17] = \debug_regfile_x2_output[17]~output_o ;

assign debug_regfile_x2_output[18] = \debug_regfile_x2_output[18]~output_o ;

assign debug_regfile_x2_output[19] = \debug_regfile_x2_output[19]~output_o ;

assign debug_regfile_x2_output[20] = \debug_regfile_x2_output[20]~output_o ;

assign debug_regfile_x2_output[21] = \debug_regfile_x2_output[21]~output_o ;

assign debug_regfile_x2_output[22] = \debug_regfile_x2_output[22]~output_o ;

assign debug_regfile_x2_output[23] = \debug_regfile_x2_output[23]~output_o ;

assign debug_regfile_x2_output[24] = \debug_regfile_x2_output[24]~output_o ;

assign debug_regfile_x2_output[25] = \debug_regfile_x2_output[25]~output_o ;

assign debug_regfile_x2_output[26] = \debug_regfile_x2_output[26]~output_o ;

assign debug_regfile_x2_output[27] = \debug_regfile_x2_output[27]~output_o ;

assign debug_regfile_x2_output[28] = \debug_regfile_x2_output[28]~output_o ;

assign debug_regfile_x2_output[29] = \debug_regfile_x2_output[29]~output_o ;

assign debug_regfile_x2_output[30] = \debug_regfile_x2_output[30]~output_o ;

assign debug_regfile_x2_output[31] = \debug_regfile_x2_output[31]~output_o ;

assign debug_ALU_output[0] = \debug_ALU_output[0]~output_o ;

assign debug_ALU_output[1] = \debug_ALU_output[1]~output_o ;

assign debug_ALU_output[2] = \debug_ALU_output[2]~output_o ;

assign debug_ALU_output[3] = \debug_ALU_output[3]~output_o ;

assign debug_ALU_output[4] = \debug_ALU_output[4]~output_o ;

assign debug_ALU_output[5] = \debug_ALU_output[5]~output_o ;

assign debug_ALU_output[6] = \debug_ALU_output[6]~output_o ;

assign debug_ALU_output[7] = \debug_ALU_output[7]~output_o ;

assign debug_ALU_output[8] = \debug_ALU_output[8]~output_o ;

assign debug_ALU_output[9] = \debug_ALU_output[9]~output_o ;

assign debug_ALU_output[10] = \debug_ALU_output[10]~output_o ;

assign debug_ALU_output[11] = \debug_ALU_output[11]~output_o ;

assign debug_ALU_output[12] = \debug_ALU_output[12]~output_o ;

assign debug_ALU_output[13] = \debug_ALU_output[13]~output_o ;

assign debug_ALU_output[14] = \debug_ALU_output[14]~output_o ;

assign debug_ALU_output[15] = \debug_ALU_output[15]~output_o ;

assign debug_ALU_output[16] = \debug_ALU_output[16]~output_o ;

assign debug_ALU_output[17] = \debug_ALU_output[17]~output_o ;

assign debug_ALU_output[18] = \debug_ALU_output[18]~output_o ;

assign debug_ALU_output[19] = \debug_ALU_output[19]~output_o ;

assign debug_ALU_output[20] = \debug_ALU_output[20]~output_o ;

assign debug_ALU_output[21] = \debug_ALU_output[21]~output_o ;

assign debug_ALU_output[22] = \debug_ALU_output[22]~output_o ;

assign debug_ALU_output[23] = \debug_ALU_output[23]~output_o ;

assign debug_ALU_output[24] = \debug_ALU_output[24]~output_o ;

assign debug_ALU_output[25] = \debug_ALU_output[25]~output_o ;

assign debug_ALU_output[26] = \debug_ALU_output[26]~output_o ;

assign debug_ALU_output[27] = \debug_ALU_output[27]~output_o ;

assign debug_ALU_output[28] = \debug_ALU_output[28]~output_o ;

assign debug_ALU_output[29] = \debug_ALU_output[29]~output_o ;

assign debug_ALU_output[30] = \debug_ALU_output[30]~output_o ;

assign debug_ALU_output[31] = \debug_ALU_output[31]~output_o ;

assign debug_regfile_write = \debug_regfile_write~output_o ;

assign debug_ALU_input_0[0] = \debug_ALU_input_0[0]~output_o ;

assign debug_ALU_input_0[1] = \debug_ALU_input_0[1]~output_o ;

assign debug_ALU_input_0[2] = \debug_ALU_input_0[2]~output_o ;

assign debug_ALU_input_0[3] = \debug_ALU_input_0[3]~output_o ;

assign debug_ALU_input_0[4] = \debug_ALU_input_0[4]~output_o ;

assign debug_ALU_input_0[5] = \debug_ALU_input_0[5]~output_o ;

assign debug_ALU_input_0[6] = \debug_ALU_input_0[6]~output_o ;

assign debug_ALU_input_0[7] = \debug_ALU_input_0[7]~output_o ;

assign debug_ALU_input_0[8] = \debug_ALU_input_0[8]~output_o ;

assign debug_ALU_input_0[9] = \debug_ALU_input_0[9]~output_o ;

assign debug_ALU_input_0[10] = \debug_ALU_input_0[10]~output_o ;

assign debug_ALU_input_0[11] = \debug_ALU_input_0[11]~output_o ;

assign debug_ALU_input_0[12] = \debug_ALU_input_0[12]~output_o ;

assign debug_ALU_input_0[13] = \debug_ALU_input_0[13]~output_o ;

assign debug_ALU_input_0[14] = \debug_ALU_input_0[14]~output_o ;

assign debug_ALU_input_0[15] = \debug_ALU_input_0[15]~output_o ;

assign debug_ALU_input_0[16] = \debug_ALU_input_0[16]~output_o ;

assign debug_ALU_input_0[17] = \debug_ALU_input_0[17]~output_o ;

assign debug_ALU_input_0[18] = \debug_ALU_input_0[18]~output_o ;

assign debug_ALU_input_0[19] = \debug_ALU_input_0[19]~output_o ;

assign debug_ALU_input_0[20] = \debug_ALU_input_0[20]~output_o ;

assign debug_ALU_input_0[21] = \debug_ALU_input_0[21]~output_o ;

assign debug_ALU_input_0[22] = \debug_ALU_input_0[22]~output_o ;

assign debug_ALU_input_0[23] = \debug_ALU_input_0[23]~output_o ;

assign debug_ALU_input_0[24] = \debug_ALU_input_0[24]~output_o ;

assign debug_ALU_input_0[25] = \debug_ALU_input_0[25]~output_o ;

assign debug_ALU_input_0[26] = \debug_ALU_input_0[26]~output_o ;

assign debug_ALU_input_0[27] = \debug_ALU_input_0[27]~output_o ;

assign debug_ALU_input_0[28] = \debug_ALU_input_0[28]~output_o ;

assign debug_ALU_input_0[29] = \debug_ALU_input_0[29]~output_o ;

assign debug_ALU_input_0[30] = \debug_ALU_input_0[30]~output_o ;

assign debug_ALU_input_0[31] = \debug_ALU_input_0[31]~output_o ;

assign debug_ALU_input_1[0] = \debug_ALU_input_1[0]~output_o ;

assign debug_ALU_input_1[1] = \debug_ALU_input_1[1]~output_o ;

assign debug_ALU_input_1[2] = \debug_ALU_input_1[2]~output_o ;

assign debug_ALU_input_1[3] = \debug_ALU_input_1[3]~output_o ;

assign debug_ALU_input_1[4] = \debug_ALU_input_1[4]~output_o ;

assign debug_ALU_input_1[5] = \debug_ALU_input_1[5]~output_o ;

assign debug_ALU_input_1[6] = \debug_ALU_input_1[6]~output_o ;

assign debug_ALU_input_1[7] = \debug_ALU_input_1[7]~output_o ;

assign debug_ALU_input_1[8] = \debug_ALU_input_1[8]~output_o ;

assign debug_ALU_input_1[9] = \debug_ALU_input_1[9]~output_o ;

assign debug_ALU_input_1[10] = \debug_ALU_input_1[10]~output_o ;

assign debug_ALU_input_1[11] = \debug_ALU_input_1[11]~output_o ;

assign debug_ALU_input_1[12] = \debug_ALU_input_1[12]~output_o ;

assign debug_ALU_input_1[13] = \debug_ALU_input_1[13]~output_o ;

assign debug_ALU_input_1[14] = \debug_ALU_input_1[14]~output_o ;

assign debug_ALU_input_1[15] = \debug_ALU_input_1[15]~output_o ;

assign debug_ALU_input_1[16] = \debug_ALU_input_1[16]~output_o ;

assign debug_ALU_input_1[17] = \debug_ALU_input_1[17]~output_o ;

assign debug_ALU_input_1[18] = \debug_ALU_input_1[18]~output_o ;

assign debug_ALU_input_1[19] = \debug_ALU_input_1[19]~output_o ;

assign debug_ALU_input_1[20] = \debug_ALU_input_1[20]~output_o ;

assign debug_ALU_input_1[21] = \debug_ALU_input_1[21]~output_o ;

assign debug_ALU_input_1[22] = \debug_ALU_input_1[22]~output_o ;

assign debug_ALU_input_1[23] = \debug_ALU_input_1[23]~output_o ;

assign debug_ALU_input_1[24] = \debug_ALU_input_1[24]~output_o ;

assign debug_ALU_input_1[25] = \debug_ALU_input_1[25]~output_o ;

assign debug_ALU_input_1[26] = \debug_ALU_input_1[26]~output_o ;

assign debug_ALU_input_1[27] = \debug_ALU_input_1[27]~output_o ;

assign debug_ALU_input_1[28] = \debug_ALU_input_1[28]~output_o ;

assign debug_ALU_input_1[29] = \debug_ALU_input_1[29]~output_o ;

assign debug_ALU_input_1[30] = \debug_ALU_input_1[30]~output_o ;

assign debug_ALU_input_1[31] = \debug_ALU_input_1[31]~output_o ;

assign debug_reg_file_read_address_0[0] = \debug_reg_file_read_address_0[0]~output_o ;

assign debug_reg_file_read_address_0[1] = \debug_reg_file_read_address_0[1]~output_o ;

assign debug_reg_file_read_address_0[2] = \debug_reg_file_read_address_0[2]~output_o ;

assign debug_reg_file_read_address_0[3] = \debug_reg_file_read_address_0[3]~output_o ;

assign debug_reg_file_read_address_0[4] = \debug_reg_file_read_address_0[4]~output_o ;

assign debug_reg_file_read_address_1[0] = \debug_reg_file_read_address_1[0]~output_o ;

assign debug_reg_file_read_address_1[1] = \debug_reg_file_read_address_1[1]~output_o ;

assign debug_reg_file_read_address_1[2] = \debug_reg_file_read_address_1[2]~output_o ;

assign debug_reg_file_read_address_1[3] = \debug_reg_file_read_address_1[3]~output_o ;

assign debug_reg_file_read_address_1[4] = \debug_reg_file_read_address_1[4]~output_o ;

assign debug_mux0_sel[0] = \debug_mux0_sel[0]~output_o ;

assign debug_mux0_sel[1] = \debug_mux0_sel[1]~output_o ;

assign debug_immediate[0] = \debug_immediate[0]~output_o ;

assign debug_immediate[1] = \debug_immediate[1]~output_o ;

assign debug_immediate[2] = \debug_immediate[2]~output_o ;

assign debug_immediate[3] = \debug_immediate[3]~output_o ;

assign debug_immediate[4] = \debug_immediate[4]~output_o ;

assign debug_immediate[5] = \debug_immediate[5]~output_o ;

assign debug_immediate[6] = \debug_immediate[6]~output_o ;

assign debug_immediate[7] = \debug_immediate[7]~output_o ;

assign debug_immediate[8] = \debug_immediate[8]~output_o ;

assign debug_immediate[9] = \debug_immediate[9]~output_o ;

assign debug_immediate[10] = \debug_immediate[10]~output_o ;

assign debug_immediate[11] = \debug_immediate[11]~output_o ;

assign debug_immediate[12] = \debug_immediate[12]~output_o ;

assign debug_immediate[13] = \debug_immediate[13]~output_o ;

assign debug_immediate[14] = \debug_immediate[14]~output_o ;

assign debug_immediate[15] = \debug_immediate[15]~output_o ;

assign debug_immediate[16] = \debug_immediate[16]~output_o ;

assign debug_immediate[17] = \debug_immediate[17]~output_o ;

assign debug_immediate[18] = \debug_immediate[18]~output_o ;

assign debug_immediate[19] = \debug_immediate[19]~output_o ;

assign debug_immediate[20] = \debug_immediate[20]~output_o ;

assign debug_immediate[21] = \debug_immediate[21]~output_o ;

assign debug_immediate[22] = \debug_immediate[22]~output_o ;

assign debug_immediate[23] = \debug_immediate[23]~output_o ;

assign debug_immediate[24] = \debug_immediate[24]~output_o ;

assign debug_immediate[25] = \debug_immediate[25]~output_o ;

assign debug_immediate[26] = \debug_immediate[26]~output_o ;

assign debug_immediate[27] = \debug_immediate[27]~output_o ;

assign debug_immediate[28] = \debug_immediate[28]~output_o ;

assign debug_immediate[29] = \debug_immediate[29]~output_o ;

assign debug_immediate[30] = \debug_immediate[30]~output_o ;

assign debug_immediate[31] = \debug_immediate[31]~output_o ;

assign debug_ALU_operation[0] = \debug_ALU_operation[0]~output_o ;

assign debug_ALU_operation[1] = \debug_ALU_operation[1]~output_o ;

assign debug_ALU_operation[2] = \debug_ALU_operation[2]~output_o ;

assign debug_ALU_operation[3] = \debug_ALU_operation[3]~output_o ;

assign debug_forward_mux_0[0] = \debug_forward_mux_0[0]~output_o ;

assign debug_forward_mux_0[1] = \debug_forward_mux_0[1]~output_o ;

assign debug_forward_mux_0[2] = \debug_forward_mux_0[2]~output_o ;

assign debug_forward_mux_1[0] = \debug_forward_mux_1[0]~output_o ;

assign debug_forward_mux_1[1] = \debug_forward_mux_1[1]~output_o ;

assign debug_forward_mux_1[2] = \debug_forward_mux_1[2]~output_o ;

assign debug_reg_file_read_address_0_ID_EXE[0] = \debug_reg_file_read_address_0_ID_EXE[0]~output_o ;

assign debug_reg_file_read_address_0_ID_EXE[1] = \debug_reg_file_read_address_0_ID_EXE[1]~output_o ;

assign debug_reg_file_read_address_0_ID_EXE[2] = \debug_reg_file_read_address_0_ID_EXE[2]~output_o ;

assign debug_reg_file_read_address_0_ID_EXE[3] = \debug_reg_file_read_address_0_ID_EXE[3]~output_o ;

assign debug_reg_file_read_address_0_ID_EXE[4] = \debug_reg_file_read_address_0_ID_EXE[4]~output_o ;

assign debug_reg_file_write_address_EX_MEM[0] = \debug_reg_file_write_address_EX_MEM[0]~output_o ;

assign debug_reg_file_write_address_EX_MEM[1] = \debug_reg_file_write_address_EX_MEM[1]~output_o ;

assign debug_reg_file_write_address_EX_MEM[2] = \debug_reg_file_write_address_EX_MEM[2]~output_o ;

assign debug_reg_file_write_address_EX_MEM[3] = \debug_reg_file_write_address_EX_MEM[3]~output_o ;

assign debug_reg_file_write_address_EX_MEM[4] = \debug_reg_file_write_address_EX_MEM[4]~output_o ;

assign debug_mux0_sel_MEM_WB[0] = \debug_mux0_sel_MEM_WB[0]~output_o ;

assign debug_mux0_sel_MEM_WB[1] = \debug_mux0_sel_MEM_WB[1]~output_o ;

assign debug_reg_file_write_MEM_WB = \debug_reg_file_write_MEM_WB~output_o ;

assign debug_reg_file_write_address_MEM_WB[0] = \debug_reg_file_write_address_MEM_WB[0]~output_o ;

assign debug_reg_file_write_address_MEM_WB[1] = \debug_reg_file_write_address_MEM_WB[1]~output_o ;

assign debug_reg_file_write_address_MEM_WB[2] = \debug_reg_file_write_address_MEM_WB[2]~output_o ;

assign debug_reg_file_write_address_MEM_WB[3] = \debug_reg_file_write_address_MEM_WB[3]~output_o ;

assign debug_reg_file_write_address_MEM_WB[4] = \debug_reg_file_write_address_MEM_WB[4]~output_o ;

assign debug_ALU_output_MEM_WB[0] = \debug_ALU_output_MEM_WB[0]~output_o ;

assign debug_ALU_output_MEM_WB[1] = \debug_ALU_output_MEM_WB[1]~output_o ;

assign debug_ALU_output_MEM_WB[2] = \debug_ALU_output_MEM_WB[2]~output_o ;

assign debug_ALU_output_MEM_WB[3] = \debug_ALU_output_MEM_WB[3]~output_o ;

assign debug_ALU_output_MEM_WB[4] = \debug_ALU_output_MEM_WB[4]~output_o ;

assign debug_ALU_output_MEM_WB[5] = \debug_ALU_output_MEM_WB[5]~output_o ;

assign debug_ALU_output_MEM_WB[6] = \debug_ALU_output_MEM_WB[6]~output_o ;

assign debug_ALU_output_MEM_WB[7] = \debug_ALU_output_MEM_WB[7]~output_o ;

assign debug_ALU_output_MEM_WB[8] = \debug_ALU_output_MEM_WB[8]~output_o ;

assign debug_ALU_output_MEM_WB[9] = \debug_ALU_output_MEM_WB[9]~output_o ;

assign debug_ALU_output_MEM_WB[10] = \debug_ALU_output_MEM_WB[10]~output_o ;

assign debug_ALU_output_MEM_WB[11] = \debug_ALU_output_MEM_WB[11]~output_o ;

assign debug_ALU_output_MEM_WB[12] = \debug_ALU_output_MEM_WB[12]~output_o ;

assign debug_ALU_output_MEM_WB[13] = \debug_ALU_output_MEM_WB[13]~output_o ;

assign debug_ALU_output_MEM_WB[14] = \debug_ALU_output_MEM_WB[14]~output_o ;

assign debug_ALU_output_MEM_WB[15] = \debug_ALU_output_MEM_WB[15]~output_o ;

assign debug_ALU_output_MEM_WB[16] = \debug_ALU_output_MEM_WB[16]~output_o ;

assign debug_ALU_output_MEM_WB[17] = \debug_ALU_output_MEM_WB[17]~output_o ;

assign debug_ALU_output_MEM_WB[18] = \debug_ALU_output_MEM_WB[18]~output_o ;

assign debug_ALU_output_MEM_WB[19] = \debug_ALU_output_MEM_WB[19]~output_o ;

assign debug_ALU_output_MEM_WB[20] = \debug_ALU_output_MEM_WB[20]~output_o ;

assign debug_ALU_output_MEM_WB[21] = \debug_ALU_output_MEM_WB[21]~output_o ;

assign debug_ALU_output_MEM_WB[22] = \debug_ALU_output_MEM_WB[22]~output_o ;

assign debug_ALU_output_MEM_WB[23] = \debug_ALU_output_MEM_WB[23]~output_o ;

assign debug_ALU_output_MEM_WB[24] = \debug_ALU_output_MEM_WB[24]~output_o ;

assign debug_ALU_output_MEM_WB[25] = \debug_ALU_output_MEM_WB[25]~output_o ;

assign debug_ALU_output_MEM_WB[26] = \debug_ALU_output_MEM_WB[26]~output_o ;

assign debug_ALU_output_MEM_WB[27] = \debug_ALU_output_MEM_WB[27]~output_o ;

assign debug_ALU_output_MEM_WB[28] = \debug_ALU_output_MEM_WB[28]~output_o ;

assign debug_ALU_output_MEM_WB[29] = \debug_ALU_output_MEM_WB[29]~output_o ;

assign debug_ALU_output_MEM_WB[30] = \debug_ALU_output_MEM_WB[30]~output_o ;

assign debug_ALU_output_MEM_WB[31] = \debug_ALU_output_MEM_WB[31]~output_o ;

assign debug_ALU_output_EX_MEM[0] = \debug_ALU_output_EX_MEM[0]~output_o ;

assign debug_ALU_output_EX_MEM[1] = \debug_ALU_output_EX_MEM[1]~output_o ;

assign debug_ALU_output_EX_MEM[2] = \debug_ALU_output_EX_MEM[2]~output_o ;

assign debug_ALU_output_EX_MEM[3] = \debug_ALU_output_EX_MEM[3]~output_o ;

assign debug_ALU_output_EX_MEM[4] = \debug_ALU_output_EX_MEM[4]~output_o ;

assign debug_ALU_output_EX_MEM[5] = \debug_ALU_output_EX_MEM[5]~output_o ;

assign debug_ALU_output_EX_MEM[6] = \debug_ALU_output_EX_MEM[6]~output_o ;

assign debug_ALU_output_EX_MEM[7] = \debug_ALU_output_EX_MEM[7]~output_o ;

assign debug_ALU_output_EX_MEM[8] = \debug_ALU_output_EX_MEM[8]~output_o ;

assign debug_ALU_output_EX_MEM[9] = \debug_ALU_output_EX_MEM[9]~output_o ;

assign debug_ALU_output_EX_MEM[10] = \debug_ALU_output_EX_MEM[10]~output_o ;

assign debug_ALU_output_EX_MEM[11] = \debug_ALU_output_EX_MEM[11]~output_o ;

assign debug_ALU_output_EX_MEM[12] = \debug_ALU_output_EX_MEM[12]~output_o ;

assign debug_ALU_output_EX_MEM[13] = \debug_ALU_output_EX_MEM[13]~output_o ;

assign debug_ALU_output_EX_MEM[14] = \debug_ALU_output_EX_MEM[14]~output_o ;

assign debug_ALU_output_EX_MEM[15] = \debug_ALU_output_EX_MEM[15]~output_o ;

assign debug_ALU_output_EX_MEM[16] = \debug_ALU_output_EX_MEM[16]~output_o ;

assign debug_ALU_output_EX_MEM[17] = \debug_ALU_output_EX_MEM[17]~output_o ;

assign debug_ALU_output_EX_MEM[18] = \debug_ALU_output_EX_MEM[18]~output_o ;

assign debug_ALU_output_EX_MEM[19] = \debug_ALU_output_EX_MEM[19]~output_o ;

assign debug_ALU_output_EX_MEM[20] = \debug_ALU_output_EX_MEM[20]~output_o ;

assign debug_ALU_output_EX_MEM[21] = \debug_ALU_output_EX_MEM[21]~output_o ;

assign debug_ALU_output_EX_MEM[22] = \debug_ALU_output_EX_MEM[22]~output_o ;

assign debug_ALU_output_EX_MEM[23] = \debug_ALU_output_EX_MEM[23]~output_o ;

assign debug_ALU_output_EX_MEM[24] = \debug_ALU_output_EX_MEM[24]~output_o ;

assign debug_ALU_output_EX_MEM[25] = \debug_ALU_output_EX_MEM[25]~output_o ;

assign debug_ALU_output_EX_MEM[26] = \debug_ALU_output_EX_MEM[26]~output_o ;

assign debug_ALU_output_EX_MEM[27] = \debug_ALU_output_EX_MEM[27]~output_o ;

assign debug_ALU_output_EX_MEM[28] = \debug_ALU_output_EX_MEM[28]~output_o ;

assign debug_ALU_output_EX_MEM[29] = \debug_ALU_output_EX_MEM[29]~output_o ;

assign debug_ALU_output_EX_MEM[30] = \debug_ALU_output_EX_MEM[30]~output_o ;

assign debug_ALU_output_EX_MEM[31] = \debug_ALU_output_EX_MEM[31]~output_o ;

assign debug_register_file_output_0[0] = \debug_register_file_output_0[0]~output_o ;

assign debug_register_file_output_0[1] = \debug_register_file_output_0[1]~output_o ;

assign debug_register_file_output_0[2] = \debug_register_file_output_0[2]~output_o ;

assign debug_register_file_output_0[3] = \debug_register_file_output_0[3]~output_o ;

assign debug_register_file_output_0[4] = \debug_register_file_output_0[4]~output_o ;

assign debug_register_file_output_0[5] = \debug_register_file_output_0[5]~output_o ;

assign debug_register_file_output_0[6] = \debug_register_file_output_0[6]~output_o ;

assign debug_register_file_output_0[7] = \debug_register_file_output_0[7]~output_o ;

assign debug_register_file_output_0[8] = \debug_register_file_output_0[8]~output_o ;

assign debug_register_file_output_0[9] = \debug_register_file_output_0[9]~output_o ;

assign debug_register_file_output_0[10] = \debug_register_file_output_0[10]~output_o ;

assign debug_register_file_output_0[11] = \debug_register_file_output_0[11]~output_o ;

assign debug_register_file_output_0[12] = \debug_register_file_output_0[12]~output_o ;

assign debug_register_file_output_0[13] = \debug_register_file_output_0[13]~output_o ;

assign debug_register_file_output_0[14] = \debug_register_file_output_0[14]~output_o ;

assign debug_register_file_output_0[15] = \debug_register_file_output_0[15]~output_o ;

assign debug_register_file_output_0[16] = \debug_register_file_output_0[16]~output_o ;

assign debug_register_file_output_0[17] = \debug_register_file_output_0[17]~output_o ;

assign debug_register_file_output_0[18] = \debug_register_file_output_0[18]~output_o ;

assign debug_register_file_output_0[19] = \debug_register_file_output_0[19]~output_o ;

assign debug_register_file_output_0[20] = \debug_register_file_output_0[20]~output_o ;

assign debug_register_file_output_0[21] = \debug_register_file_output_0[21]~output_o ;

assign debug_register_file_output_0[22] = \debug_register_file_output_0[22]~output_o ;

assign debug_register_file_output_0[23] = \debug_register_file_output_0[23]~output_o ;

assign debug_register_file_output_0[24] = \debug_register_file_output_0[24]~output_o ;

assign debug_register_file_output_0[25] = \debug_register_file_output_0[25]~output_o ;

assign debug_register_file_output_0[26] = \debug_register_file_output_0[26]~output_o ;

assign debug_register_file_output_0[27] = \debug_register_file_output_0[27]~output_o ;

assign debug_register_file_output_0[28] = \debug_register_file_output_0[28]~output_o ;

assign debug_register_file_output_0[29] = \debug_register_file_output_0[29]~output_o ;

assign debug_register_file_output_0[30] = \debug_register_file_output_0[30]~output_o ;

assign debug_register_file_output_0[31] = \debug_register_file_output_0[31]~output_o ;

assign debug_register_file_output_1[0] = \debug_register_file_output_1[0]~output_o ;

assign debug_register_file_output_1[1] = \debug_register_file_output_1[1]~output_o ;

assign debug_register_file_output_1[2] = \debug_register_file_output_1[2]~output_o ;

assign debug_register_file_output_1[3] = \debug_register_file_output_1[3]~output_o ;

assign debug_register_file_output_1[4] = \debug_register_file_output_1[4]~output_o ;

assign debug_register_file_output_1[5] = \debug_register_file_output_1[5]~output_o ;

assign debug_register_file_output_1[6] = \debug_register_file_output_1[6]~output_o ;

assign debug_register_file_output_1[7] = \debug_register_file_output_1[7]~output_o ;

assign debug_register_file_output_1[8] = \debug_register_file_output_1[8]~output_o ;

assign debug_register_file_output_1[9] = \debug_register_file_output_1[9]~output_o ;

assign debug_register_file_output_1[10] = \debug_register_file_output_1[10]~output_o ;

assign debug_register_file_output_1[11] = \debug_register_file_output_1[11]~output_o ;

assign debug_register_file_output_1[12] = \debug_register_file_output_1[12]~output_o ;

assign debug_register_file_output_1[13] = \debug_register_file_output_1[13]~output_o ;

assign debug_register_file_output_1[14] = \debug_register_file_output_1[14]~output_o ;

assign debug_register_file_output_1[15] = \debug_register_file_output_1[15]~output_o ;

assign debug_register_file_output_1[16] = \debug_register_file_output_1[16]~output_o ;

assign debug_register_file_output_1[17] = \debug_register_file_output_1[17]~output_o ;

assign debug_register_file_output_1[18] = \debug_register_file_output_1[18]~output_o ;

assign debug_register_file_output_1[19] = \debug_register_file_output_1[19]~output_o ;

assign debug_register_file_output_1[20] = \debug_register_file_output_1[20]~output_o ;

assign debug_register_file_output_1[21] = \debug_register_file_output_1[21]~output_o ;

assign debug_register_file_output_1[22] = \debug_register_file_output_1[22]~output_o ;

assign debug_register_file_output_1[23] = \debug_register_file_output_1[23]~output_o ;

assign debug_register_file_output_1[24] = \debug_register_file_output_1[24]~output_o ;

assign debug_register_file_output_1[25] = \debug_register_file_output_1[25]~output_o ;

assign debug_register_file_output_1[26] = \debug_register_file_output_1[26]~output_o ;

assign debug_register_file_output_1[27] = \debug_register_file_output_1[27]~output_o ;

assign debug_register_file_output_1[28] = \debug_register_file_output_1[28]~output_o ;

assign debug_register_file_output_1[29] = \debug_register_file_output_1[29]~output_o ;

assign debug_register_file_output_1[30] = \debug_register_file_output_1[30]~output_o ;

assign debug_register_file_output_1[31] = \debug_register_file_output_1[31]~output_o ;

assign debug_register_file_output_0_ID_EX[0] = \debug_register_file_output_0_ID_EX[0]~output_o ;

assign debug_register_file_output_0_ID_EX[1] = \debug_register_file_output_0_ID_EX[1]~output_o ;

assign debug_register_file_output_0_ID_EX[2] = \debug_register_file_output_0_ID_EX[2]~output_o ;

assign debug_register_file_output_0_ID_EX[3] = \debug_register_file_output_0_ID_EX[3]~output_o ;

assign debug_register_file_output_0_ID_EX[4] = \debug_register_file_output_0_ID_EX[4]~output_o ;

assign debug_register_file_output_0_ID_EX[5] = \debug_register_file_output_0_ID_EX[5]~output_o ;

assign debug_register_file_output_0_ID_EX[6] = \debug_register_file_output_0_ID_EX[6]~output_o ;

assign debug_register_file_output_0_ID_EX[7] = \debug_register_file_output_0_ID_EX[7]~output_o ;

assign debug_register_file_output_0_ID_EX[8] = \debug_register_file_output_0_ID_EX[8]~output_o ;

assign debug_register_file_output_0_ID_EX[9] = \debug_register_file_output_0_ID_EX[9]~output_o ;

assign debug_register_file_output_0_ID_EX[10] = \debug_register_file_output_0_ID_EX[10]~output_o ;

assign debug_register_file_output_0_ID_EX[11] = \debug_register_file_output_0_ID_EX[11]~output_o ;

assign debug_register_file_output_0_ID_EX[12] = \debug_register_file_output_0_ID_EX[12]~output_o ;

assign debug_register_file_output_0_ID_EX[13] = \debug_register_file_output_0_ID_EX[13]~output_o ;

assign debug_register_file_output_0_ID_EX[14] = \debug_register_file_output_0_ID_EX[14]~output_o ;

assign debug_register_file_output_0_ID_EX[15] = \debug_register_file_output_0_ID_EX[15]~output_o ;

assign debug_register_file_output_0_ID_EX[16] = \debug_register_file_output_0_ID_EX[16]~output_o ;

assign debug_register_file_output_0_ID_EX[17] = \debug_register_file_output_0_ID_EX[17]~output_o ;

assign debug_register_file_output_0_ID_EX[18] = \debug_register_file_output_0_ID_EX[18]~output_o ;

assign debug_register_file_output_0_ID_EX[19] = \debug_register_file_output_0_ID_EX[19]~output_o ;

assign debug_register_file_output_0_ID_EX[20] = \debug_register_file_output_0_ID_EX[20]~output_o ;

assign debug_register_file_output_0_ID_EX[21] = \debug_register_file_output_0_ID_EX[21]~output_o ;

assign debug_register_file_output_0_ID_EX[22] = \debug_register_file_output_0_ID_EX[22]~output_o ;

assign debug_register_file_output_0_ID_EX[23] = \debug_register_file_output_0_ID_EX[23]~output_o ;

assign debug_register_file_output_0_ID_EX[24] = \debug_register_file_output_0_ID_EX[24]~output_o ;

assign debug_register_file_output_0_ID_EX[25] = \debug_register_file_output_0_ID_EX[25]~output_o ;

assign debug_register_file_output_0_ID_EX[26] = \debug_register_file_output_0_ID_EX[26]~output_o ;

assign debug_register_file_output_0_ID_EX[27] = \debug_register_file_output_0_ID_EX[27]~output_o ;

assign debug_register_file_output_0_ID_EX[28] = \debug_register_file_output_0_ID_EX[28]~output_o ;

assign debug_register_file_output_0_ID_EX[29] = \debug_register_file_output_0_ID_EX[29]~output_o ;

assign debug_register_file_output_0_ID_EX[30] = \debug_register_file_output_0_ID_EX[30]~output_o ;

assign debug_register_file_output_0_ID_EX[31] = \debug_register_file_output_0_ID_EX[31]~output_o ;

assign debug_register_file_output_1_ID_EX[0] = \debug_register_file_output_1_ID_EX[0]~output_o ;

assign debug_register_file_output_1_ID_EX[1] = \debug_register_file_output_1_ID_EX[1]~output_o ;

assign debug_register_file_output_1_ID_EX[2] = \debug_register_file_output_1_ID_EX[2]~output_o ;

assign debug_register_file_output_1_ID_EX[3] = \debug_register_file_output_1_ID_EX[3]~output_o ;

assign debug_register_file_output_1_ID_EX[4] = \debug_register_file_output_1_ID_EX[4]~output_o ;

assign debug_register_file_output_1_ID_EX[5] = \debug_register_file_output_1_ID_EX[5]~output_o ;

assign debug_register_file_output_1_ID_EX[6] = \debug_register_file_output_1_ID_EX[6]~output_o ;

assign debug_register_file_output_1_ID_EX[7] = \debug_register_file_output_1_ID_EX[7]~output_o ;

assign debug_register_file_output_1_ID_EX[8] = \debug_register_file_output_1_ID_EX[8]~output_o ;

assign debug_register_file_output_1_ID_EX[9] = \debug_register_file_output_1_ID_EX[9]~output_o ;

assign debug_register_file_output_1_ID_EX[10] = \debug_register_file_output_1_ID_EX[10]~output_o ;

assign debug_register_file_output_1_ID_EX[11] = \debug_register_file_output_1_ID_EX[11]~output_o ;

assign debug_register_file_output_1_ID_EX[12] = \debug_register_file_output_1_ID_EX[12]~output_o ;

assign debug_register_file_output_1_ID_EX[13] = \debug_register_file_output_1_ID_EX[13]~output_o ;

assign debug_register_file_output_1_ID_EX[14] = \debug_register_file_output_1_ID_EX[14]~output_o ;

assign debug_register_file_output_1_ID_EX[15] = \debug_register_file_output_1_ID_EX[15]~output_o ;

assign debug_register_file_output_1_ID_EX[16] = \debug_register_file_output_1_ID_EX[16]~output_o ;

assign debug_register_file_output_1_ID_EX[17] = \debug_register_file_output_1_ID_EX[17]~output_o ;

assign debug_register_file_output_1_ID_EX[18] = \debug_register_file_output_1_ID_EX[18]~output_o ;

assign debug_register_file_output_1_ID_EX[19] = \debug_register_file_output_1_ID_EX[19]~output_o ;

assign debug_register_file_output_1_ID_EX[20] = \debug_register_file_output_1_ID_EX[20]~output_o ;

assign debug_register_file_output_1_ID_EX[21] = \debug_register_file_output_1_ID_EX[21]~output_o ;

assign debug_register_file_output_1_ID_EX[22] = \debug_register_file_output_1_ID_EX[22]~output_o ;

assign debug_register_file_output_1_ID_EX[23] = \debug_register_file_output_1_ID_EX[23]~output_o ;

assign debug_register_file_output_1_ID_EX[24] = \debug_register_file_output_1_ID_EX[24]~output_o ;

assign debug_register_file_output_1_ID_EX[25] = \debug_register_file_output_1_ID_EX[25]~output_o ;

assign debug_register_file_output_1_ID_EX[26] = \debug_register_file_output_1_ID_EX[26]~output_o ;

assign debug_register_file_output_1_ID_EX[27] = \debug_register_file_output_1_ID_EX[27]~output_o ;

assign debug_register_file_output_1_ID_EX[28] = \debug_register_file_output_1_ID_EX[28]~output_o ;

assign debug_register_file_output_1_ID_EX[29] = \debug_register_file_output_1_ID_EX[29]~output_o ;

assign debug_register_file_output_1_ID_EX[30] = \debug_register_file_output_1_ID_EX[30]~output_o ;

assign debug_register_file_output_1_ID_EX[31] = \debug_register_file_output_1_ID_EX[31]~output_o ;

assign debug_instruction[0] = \debug_instruction[0]~output_o ;

assign debug_instruction[1] = \debug_instruction[1]~output_o ;

assign debug_instruction[2] = \debug_instruction[2]~output_o ;

assign debug_instruction[3] = \debug_instruction[3]~output_o ;

assign debug_instruction[4] = \debug_instruction[4]~output_o ;

assign debug_instruction[5] = \debug_instruction[5]~output_o ;

assign debug_instruction[6] = \debug_instruction[6]~output_o ;

assign debug_instruction[7] = \debug_instruction[7]~output_o ;

assign debug_instruction[8] = \debug_instruction[8]~output_o ;

assign debug_instruction[9] = \debug_instruction[9]~output_o ;

assign debug_instruction[10] = \debug_instruction[10]~output_o ;

assign debug_instruction[11] = \debug_instruction[11]~output_o ;

assign debug_instruction[12] = \debug_instruction[12]~output_o ;

assign debug_instruction[13] = \debug_instruction[13]~output_o ;

assign debug_instruction[14] = \debug_instruction[14]~output_o ;

assign debug_instruction[15] = \debug_instruction[15]~output_o ;

assign debug_instruction[16] = \debug_instruction[16]~output_o ;

assign debug_instruction[17] = \debug_instruction[17]~output_o ;

assign debug_instruction[18] = \debug_instruction[18]~output_o ;

assign debug_instruction[19] = \debug_instruction[19]~output_o ;

assign debug_instruction[20] = \debug_instruction[20]~output_o ;

assign debug_instruction[21] = \debug_instruction[21]~output_o ;

assign debug_instruction[22] = \debug_instruction[22]~output_o ;

assign debug_instruction[23] = \debug_instruction[23]~output_o ;

assign debug_instruction[24] = \debug_instruction[24]~output_o ;

assign debug_instruction[25] = \debug_instruction[25]~output_o ;

assign debug_instruction[26] = \debug_instruction[26]~output_o ;

assign debug_instruction[27] = \debug_instruction[27]~output_o ;

assign debug_instruction[28] = \debug_instruction[28]~output_o ;

assign debug_instruction[29] = \debug_instruction[29]~output_o ;

assign debug_instruction[30] = \debug_instruction[30]~output_o ;

assign debug_instruction[31] = \debug_instruction[31]~output_o ;

endmodule