wip

bench/servant_sim.v

@@ -10,13 +10,14 @@ module servant_sim
    parameter compressed = 0;
    parameter align = compressed;
 
+/*
    reg [1023:0] firmware_file;
    initial
      if ($value$plusargs("firmware=%s", firmware_file)) begin
 	$display("Loading RAM from %0s", firmware_file);
 	$readmemh(firmware_file, dut.ram.mem);
      end
-
+*/
    servant
      #(.memfile  (memfile),
        .memsize  (memsize),

servant.core

@@ -10,11 +10,16 @@ filesets:
       - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
     file_type : user
 
+  ice40_cells:
+    files:
+      - cells_sim.v : {file_type : verilogSource, tags : [simulation]}
+
   servant_tb:
     files:
       - bench/servant_sim.v
       - bench/uart_decoder.v
       - bench/servant_tb.v
+    tags : [simulation]
     file_type : verilogSource
     depend : [vlog_tb_utils]
 
@@ -185,6 +190,12 @@ filesets:
       - servant/servus.v : {file_type : verilogSource}
       - data/zcu106.xdc : {file_type : xdc}
 
+  vivado_cells:
+    files:
+      - /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
+    tags : [simulation]
+    file_type : verilogSource
+
 targets:
   default:
     filesets : [soc]
@@ -433,6 +444,32 @@ targets:
         speed   : -3
     toplevel : servis
 
+  gatesim:
+    filesets : [mem_files, soc, servant_tb, ice40_cells]
+    flow: gls
+    flow_options:
+      arch : ice40
+      synth: yosys
+      synth_top : servant
+      sim: icarus
+      iverilog_options : [-g2012]
+    parameters :
+      - memfile
+    toplevel : [servant_tb]
+
+  vivadogls:
+    filesets : [mem_files, soc, servant_tb, vivado_cells]
+    flow: gls
+    flow_options:
+      synth: vivado
+      synth_top : servant
+      sim: icarus
+      iverilog_options : [-g2012, -y/opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims]
+    parameters :
+      - memfile
+    toplevel : [servant_tb, glbl]
+
+
   sim:
     default_tool: icarus
     filesets : [soc, servant_tb]

vlog_tb_utils-1.1-r2.core

@@ -0,0 +1,50 @@
+CAPI=2:
+
+name : ::vlog_tb_utils:1.1-r2
+description : Verilog test bench utilities
+
+filesets:
+  tb_files:
+    files:
+      - vlog_functions.v
+      - vlog_tap_generator.v
+      - vlog_tb_utils.v
+    file_type : verilogSource
+    tags : [simulation]
+
+targets:
+  default:
+    filesets : [tb_files]
+    parameters : [heartbeat, tapfile, testcase, timeout, vcd]
+
+parameters:
+  heartbeat:
+    datatype    : int
+    description : Display a heartbeat message every n*heartbeat time unit
+    paramtype   : plusarg
+
+  tapfile:
+    datatype    : str
+    description : Name of TAP file
+    paramtype   : plusarg
+
+  testcase:
+    datatype    : str
+    description : Name of testcase (Used for VCD filename)
+    paramtype   : plusarg
+
+  timeout:
+    datatype    : int
+    description : Abort test case after n cycles
+    paramtype   : plusarg
+
+  vcd:
+    datatype    : bool
+    description : Enable VCD logging
+    paramtype   : plusarg
+
+provider:
+  name : github
+  user : fusesoc
+  repo : vlog_tb_utils
+  version : v1.1