Separate state and decode from CSR signals

rtl/serv_csr.v

@@ -2,6 +2,7 @@
 module serv_csr
   (
    input wire 	    i_clk,
+   input wire 	    i_run,
    input wire [4:2] i_cnt,
    input wire [3:2] i_cnt_r,
    //From mpram
@@ -39,9 +40,9 @@ module serv_csr
 		   (i_csr_source == CSR_SOURCE_CSR) ? csr_out :
 		   1'bx;
 
-   assign csr_out = (i_mstatus_en & mstatus) |
+   assign csr_out = (i_mstatus_en & i_run & mstatus) |
 		    i_rf_csr_out |
-		    (i_mcause_en & mcause);
+		    (i_mcause_en & i_run & mcause);
 
    assign o_q = csr_out;
 
@@ -72,7 +73,7 @@ module serv_csr
 	 mcause3_0 <= timer_irq ? 4'd7 : i_mcause[3:0];
       end
 
-      if (i_mcause_en) begin
+      if (i_mcause_en & i_run) begin
 	 if (i_cnt[4:2] == 3'd0)
 	   mcause3_0 <= {csr_in, mcause3_0[3:1]};
 	 if ((i_cnt[4:2] == 3'd7) & i_cnt_r[3])

rtl/serv_decode.v

@@ -8,6 +8,7 @@ module serv_decode
    input wire 	     i_wb_en,
    input wire 	     i_rf_ready,
    output wire 	     o_init,
+   output wire 	     o_run,
    output wire 	     o_cnt_en,
    output reg [4:0]  o_cnt,
    output reg [3:0]  o_cnt_r,
@@ -135,9 +136,9 @@ module serv_decode
 
    wire mret = (i_wb_rdt[6] & i_wb_rdt[4] & i_wb_rdt[21] & !(|i_wb_rdt[14:12]));
 
-   assign o_rf_rd_en = running & (opcode[2] |
-				  (!opcode[2] & opcode[4] & opcode[0]) |
-				  (!opcode[2] & !opcode[3] & !opcode[0]));
+   assign o_rf_rd_en = (opcode[2] |
+			(!opcode[2] & opcode[4] & opcode[0]) |
+			(!opcode[2] & !opcode[3] & !opcode[0]));
 
    reg alu_sub_r;
    assign o_alu_sub = alu_sub_r;
@@ -164,11 +165,15 @@ module serv_decode
    wire csr_op = opcode[4] & opcode[2] & (|o_funct3);
    assign o_rd_csr_en = csr_op;
 
-   assign o_csr_en         = csr_op & (state == RUN) & csr_valid;
-   assign o_csr_mstatus_en = csr_op & (state == RUN) & !op26 & !op22;
-   assign o_csr_mie_en     = csr_op & (state == RUN) & !op26 &  op22 & !op20;
-   assign o_csr_mcause_en  = csr_op & (state == RUN)         &  op21 & !op20;
+   assign o_csr_en         = csr_op & csr_valid;
+   assign o_csr_mstatus_en = csr_op & !op26 & !op22;
+   assign o_csr_mie_en     = csr_op & !op26 &  op22 & !op20;
+   assign o_csr_mcause_en  = csr_op         &  op21 & !op20;
 
+   assign o_csr_source = o_funct3[1:0];
+   assign o_csr_d_sel = o_funct3[2];
+
+   assign o_csr_imm = (o_cnt < 5) ? o_rf_rs1_addr[o_cnt[2:0]] : 1'b0;
 
    assign o_alu_cmp_eq = o_funct3[2:1] == 2'b00;
 
@@ -183,10 +188,6 @@ module serv_decode
       endcase
    end
 
-   assign o_csr_source = o_funct3[1:0];
-   assign o_csr_imm = (o_cnt < 5) ? o_rf_rs1_addr[o_cnt[2:0]] : 1'b0;
-   assign o_csr_d_sel = o_funct3[2];
-
    assign o_alu_shamt_en = (o_cnt < 5) & (state == INIT);
    assign o_alu_sh_signed = imm30;
    assign o_alu_sh_right = o_funct3[2];
@@ -274,6 +275,7 @@ module serv_decode
    assign o_init = (state == INIT);
 
    assign running = (state == RUN);
+   assign o_run = running;
 
    assign o_ctrl_trap = (state == TRAP);
 

rtl/serv_mpram.v

@@ -3,6 +3,7 @@ module serv_mpram
   (
    input wire 	    i_clk,
    input wire 	    i_rst,
+   input wire       i_run,
    //Trap interface
    input wire 	    i_trap,
    input wire 	    i_mepc,
@@ -57,16 +58,16 @@ module serv_mpram
    //rd    0xxxxx
    wire [5:0] waddr0 = trap_3r ? {4'b1000,CSR_MTVAL} : {1'b0,rd_waddr};
    wire [5:0] waddr1 = trap_3r ? {4'b1000,CSR_MEPC}  : {4'b1000,i_csr_addr};
-  
+
    assign waddr[8:3] = wcnt_lo[0] ? waddr0 : waddr1;
- 
+
 //   assign waddr[8] = wcnt_lo[1] | i_trap;
 //   assign waddr[7:5] = (wcnt_lo[1] | i_trap) ? 3'b000 : rd_waddr[4:2];
 //   assign waddr[4:3] = wcnt_lo[0] ? (i_trap ? CSR_MTVAL : rd_waddr[1:0]) :
 //		                    (i_trap ? CSR_MEPC  : i_csr_addr);
    assign waddr[2:0] = wcnt_hi;
 
-   wire 	     wgo = !(|wcnt_lo) & (i_rd_wen | i_csr_en | i_trap);
+   wire 	     wgo = !(|wcnt_lo) & ((i_run & (i_rd_wen | i_csr_en)) | i_trap);
 
    reg 		     trap_r;
    reg 		     trap_2r;
@@ -76,10 +77,10 @@ module serv_mpram
       trap_r <= i_trap;
       trap_2r <= trap_r;
       trap_3r <= trap_2r;
-      
+
       if (wgo) begin
 	 wgo_r <= 1'b1;
-	 wen_r <= {i_csr_en|i_trap,i_rd_wen|i_trap};
+	 wen_r <= {(i_run & i_csr_en)|i_trap,(i_rd_wen & i_run)|i_trap};
 	 rd_waddr <= i_rd_waddr;
       end
       wdata0 <= {i_trap ? i_mtval : i_rd ,wdata0[4:1]};

rtl/serv_top.v

@@ -66,6 +66,7 @@ module serv_top
    wire 	 pc_rel;
 
    wire          init;
+   wire          run;
    wire          cnt_en;
    wire [4:0] 	 cnt;
    wire [3:0] 	 cnt_r;
@@ -135,6 +136,7 @@ module serv_top
       .i_wb_en        (o_ibus_cyc & i_ibus_ack),
       .i_rf_ready     (rf_ready | i_dbus_ack),
       .o_init         (init),
+      .o_run          (run),
       .o_cnt_en       (cnt_en),
       .o_cnt          (cnt),
       .o_cnt_r        (cnt_r),
@@ -286,6 +288,7 @@ module serv_top
      (
       .i_clk       (clk),
       .i_rst       (i_rst),
+      .i_run       (run),
       //Trap interface
       .i_trap      (trap),
       .i_mepc      (o_ibus_adr[0]),
@@ -335,6 +338,7 @@ module serv_top
    serv_csr csr
      (
       .i_clk        (clk),
+      .i_run        (run),
       .i_cnt        (cnt[4:2]),
       .i_cnt_r      (cnt_r[3:2]),
       .i_rf_csr_out (rf_csr_out),