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https://github.com/olofk/serv.git
synced 2025-04-22 21:07:12 -04:00
Move mepc and mtval into RF memory
This commit is contained in:
Olof Kindgren
parent
93f7b582bb
commit
16c93a58ee
4 changed files with 43 additions and 83 deletions
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@ -13,40 +13,22 @@ module serv_csr
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output wire o_timer_irq_en,
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input wire i_mstatus_en,
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input wire i_mie_en,
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input wire i_mip_en,
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input wire i_mepc_en,
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input wire i_mcause_en,
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input wire i_mtval_en,
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input wire [1:0] i_csr_source,
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input wire i_trap,
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input wire i_pc,
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input wire i_mtval,
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input wire [3:0] i_mcause,
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input wire i_d,
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output wire o_q);
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`include "serv_params.vh"
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/*
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300 mstatus RWSC
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304 mie SCWi
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305 mtvec RW
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344 mip CWi
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340 mscratch
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341 mepc RW
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342 mcause R
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343 mtval
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*/
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reg mstatus;
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reg mstatus_mie;
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reg mie_mtie;
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reg [31:0] mepc;
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reg mcause31;
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reg [3:0] mcause3_0;
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wire mcause;
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reg [31:0] mtval;
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wire csr_in;
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wire csr_out;
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@ -59,9 +41,7 @@ module serv_csr
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assign csr_out = (i_mstatus_en & mstatus) |
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i_rf_csr_out |
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(i_mepc_en & mepc[0]) |
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(i_mcause_en & mcause) |
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(i_mtval_en & mtval[0]);
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(i_mcause_en & mcause);
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assign o_q = csr_out;
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@ -87,18 +67,12 @@ module serv_csr
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mcause3_0 <= (i_mtip & o_timer_irq_en) ? 4'd7 : i_mcause[3:0];
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end
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if (i_mepc_en | i_trap)
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mepc <= {i_trap ? i_pc : csr_in, mepc[31:1]};
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if (i_mcause_en) begin
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if (i_cnt[4:2] == 3'd0)
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mcause3_0 <= {csr_in, mcause3_0[3:1]};
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if ((i_cnt[4:2] == 3'd7) & i_cnt_r[3])
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mcause31 <= csr_in;
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end
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if (i_mtval_en | i_trap)
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mtval <= {i_trap ? i_mtval : csr_in, mtval[31:1]};
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end
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endmodule
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@ -22,7 +22,7 @@ module serv_decode
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output wire o_ctrl_utype,
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output wire o_ctrl_lui,
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output wire o_ctrl_trap,
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output wire o_ctrl_mret,
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output reg o_ctrl_mret,
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input wire i_ctrl_misalign,
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output wire o_rf_rs_en,
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output wire o_rf_rd_en,
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@ -47,14 +47,11 @@ module serv_decode
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output wire o_mem_init,
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output wire [1:0] o_mem_bytecnt,
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input wire i_mem_misalign,
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output wire o_csr_en,
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output reg [1:0] o_csr_addr,
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output wire o_csr_mstatus_en,
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output wire o_csr_mie_en,
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output wire o_csr_mtvec_en,
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output wire o_csr_mip_en,
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output wire o_csr_mscratch_en,
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output wire o_csr_mepc_en,
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output wire o_csr_mcause_en,
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output wire o_csr_mtval_en,
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output reg [1:0] o_csr_source,
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output reg [3:0] o_csr_mcause,
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output wire o_csr_imm,
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@ -117,7 +114,8 @@ module serv_decode
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assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
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assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0];
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assign o_ctrl_mret = (opcode[4] & opcode[2]) & op21 & !(|o_funct3);
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wire mret = (i_wb_rdt[6] & i_wb_rdt[4] & i_wb_rdt[21] & !(|i_wb_rdt[14:12]));
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assign o_rf_rd_en = running & (opcode[2] |
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(!opcode[2] & opcode[4] & opcode[0]) |
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@ -148,17 +146,17 @@ module serv_decode
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343 1_011 mtval
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344 1_100 mip CWi
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*/
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//true for mtvec,mscratch,mepc and mtval
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//false for mstatus, mie, mcause, mip
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wire csr_valid = op20 | (op26 & !op22 & !op21);
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assign o_csr_en = (o_ctrl_mret & state[1]) | o_ctrl_trap | (csr_en & csr_valid);
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wire csr_en = opcode[4] & opcode[2] & (|o_funct3) & running;
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assign o_csr_mstatus_en = csr_en & !op26 & !op22;
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assign o_csr_mie_en = csr_en & !op26 & op22 & !op20;
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assign o_csr_mtvec_en = ((!op26 & op20 & opcode[4] & opcode[2]) & state[1]) | (state == TRAP);
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assign o_csr_mscratch_en = csr_en & op26 & !op22 & !op21 & !op20;
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assign o_csr_mepc_en = csr_en & op26 & !op21 & op20 | (o_ctrl_mret & state[1]);
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assign o_csr_mcause_en = csr_en & op21 & !op20;
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assign o_csr_mtval_en = csr_en & op21 & op20;
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assign o_csr_mip_en = csr_en & op26 & op22;
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always @(o_funct3, o_rf_rs1_addr, o_ctrl_trap, o_ctrl_mret) begin
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@ -239,6 +237,13 @@ module serv_decode
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op22 <= i_wb_rdt[22];
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op26 <= i_wb_rdt[26];
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//Default to mtvec to have the correct CSR address loaded in case of trap
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o_csr_addr <= mret ? 2'b10 : //mepc
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(i_wb_rdt[26] & !i_wb_rdt[20]) ? 2'b00 : //mscratch
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(i_wb_rdt[26] & !i_wb_rdt[21]) ? 2'b10 : //mepc
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(i_wb_rdt[26]) ? 2'b11 : //mtval
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2'b01; //mtvec
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o_ctrl_mret <= mret;
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imm[31] <= sign_bit;
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imm[30:20] <= utype ? i_wb_rdt[30:20] : {11{sign_bit}};
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imm[19:12] <= (utype | jtype) ? i_wb_rdt[19:12] : {8{sign_bit}};
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@ -3,15 +3,13 @@ module serv_mpram
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(
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input wire i_clk,
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input wire i_rst,
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//MEPC write port
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input wire i_mepc_wen,
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//Trap interface
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input wire i_trap,
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input wire i_mepc,
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//MTVAL write port
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input wire i_mtval_wen,
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input wire i_mtval,
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//CSR interface
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input wire i_csr_mscratch_en,
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input wire i_csr_mtvec_en,
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input wire i_csr_en,
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input wire [1:0] i_csr_addr,
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input wire i_csr,
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output wire o_csr,
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//RD write port
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@ -28,10 +26,6 @@ module serv_mpram
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input wire [4:0] i_rs2_raddr,
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output wire o_rs2);
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reg [1:0] csr_addr;
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wire csr_en = i_csr_mscratch_en|i_csr_mtvec_en;
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wire [8:0] waddr;
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reg [4:0] wdata0;
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@ -55,24 +49,24 @@ module serv_mpram
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assign wen = !wgo_r & |(wen_r & wcnt_lo);
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reg [4:0] rd_waddr;
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//mepc 100000
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//mepc 100010
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//mtval 100011
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//csr 1000xx
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//rd 0xxxxx
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assign waddr[8] = !wcnt_lo[3];
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assign waddr[7:5] = wcnt_lo[3] ? rd_waddr[4:2] : 3'b000;
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assign waddr[4:3] = wcnt_lo[3] ? rd_waddr[1:0] :
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wcnt_lo[2] ? csr_addr :
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wcnt_lo[1] ? 2'b11 : 2'b00;
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wcnt_lo[2] ? i_csr_addr :
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wcnt_lo[1] ? 2'b11 : 2'b10;
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assign waddr[2:0] = wcnt_hi;
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wire wgo = !(|wcnt_lo) & |({i_rd_wen,csr_en,i_mtval_wen,i_mepc_wen});
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wire wgo = !(|wcnt_lo) & |({i_rd_wen,i_csr_en,i_trap, i_trap});
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always @(posedge i_clk) begin
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if (wgo) begin
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wgo_r <= 1'b1;
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wen_r <= {i_rd_wen,csr_en,i_mtval_wen,i_mepc_wen};
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wen_r <= {i_rd_wen,i_csr_en,i_trap,i_trap};
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rd_waddr <= i_rd_waddr;
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end
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wdata0 <= {i_mepc,wdata0[4:1]};
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@ -120,11 +114,9 @@ module serv_mpram
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if (i_rreq) begin
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rcnt_lo <= 4'd1;
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rcnt_hi <= 3'd0;
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csr_addr <= {1'b0,i_csr_mtvec_en};
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end else
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rcnt_lo <= {rcnt_lo[2:0],rcnt_lo[3]};
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rdata0[4:0] <= rdata0[5:1];
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rdata1[3:0] <= rdata1[4:1];
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rdata2[2:0] <= rdata2[3:1];
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@ -145,12 +137,12 @@ module serv_mpram
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assign raddr[7:5] = rcnt_lo[0] ? i_rs1_raddr[4:2] :
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rcnt_lo[1] ? i_rs2_raddr[4:2] : 3'd0;
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assign raddr[4:3] = rcnt_lo[0] ? i_rs1_raddr[1:0] :
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rcnt_lo[1] ? i_rs2_raddr[1:0] : csr_addr;
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rcnt_lo[1] ? i_rs2_raddr[1:0] : i_csr_addr;
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assign raddr[2:0] = rcnt_hi;
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assign o_rs1 = rdata0[0];
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assign o_rs2 = rdata1[0];
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assign o_csr = rdata2[0] & csr_en;
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assign o_csr = rdata2[0] & i_csr_en;
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reg [3:0] memory [0:511];
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@ -117,15 +117,12 @@ module serv_top
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wire csr_mstatus_en;
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wire csr_mie_en;
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wire csr_mtvec_en;
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wire csr_mip_en;
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wire csr_mscratch_en;
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wire csr_mepc_en;
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wire csr_mcause_en;
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wire csr_mtval_en;
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wire [1:0] csr_source;
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wire csr_imm;
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wire csr_d_sel;
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wire csr_en;
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wire [1:0] csr_addr;
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wire [3:0] mcause;
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@ -184,14 +181,11 @@ module serv_top
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.o_mem_init (mem_init),
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.o_mem_bytecnt (mem_bytecnt),
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.i_mem_misalign (mem_misalign),
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.o_csr_en (csr_en),
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.o_csr_addr (csr_addr),
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.o_csr_mstatus_en (csr_mstatus_en),
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.o_csr_mie_en (csr_mie_en),
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.o_csr_mtvec_en (csr_mtvec_en),
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.o_csr_mip_en (csr_mip_en),
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.o_csr_mscratch_en (csr_mscratch_en),
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.o_csr_mepc_en (csr_mepc_en),
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.o_csr_mcause_en (csr_mcause_en),
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.o_csr_mtval_en (csr_mtval_en),
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.o_csr_source (csr_source),
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.o_csr_mcause (mcause),
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.o_csr_imm (csr_imm),
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@ -300,15 +294,13 @@ module serv_top
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(
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.i_clk (clk),
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.i_rst (i_rst),
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//MEPC write port
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.i_mepc_wen (1'b0),
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.i_mepc (1'b0),
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//MTVAL write port
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.i_mtval_wen (1'b0),
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.i_mtval (1'b0),
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//Trap interface
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.i_trap (trap),
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.i_mepc (o_ibus_adr[0]),
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.i_mtval (mem_misalign ? bad_adr : bad_pc),
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//CSR write port
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.i_csr_mscratch_en (csr_mscratch_en),
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.i_csr_mtvec_en (csr_mtvec_en),
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.i_csr_en (csr_en),
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.i_csr_addr (csr_addr),
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.i_csr (csr_in),
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//RD write port
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.i_rd_wen (rd_en & (|rd_addr)),
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@ -359,14 +351,9 @@ module serv_top
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.o_timer_irq_en ( timer_irq_en),
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.i_mstatus_en (csr_mstatus_en),
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.i_mie_en (csr_mie_en ),
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.i_mip_en (csr_mip_en ),
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.i_mepc_en (csr_mepc_en ),
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.i_mcause_en (csr_mcause_en ),
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.i_mtval_en (csr_mtval_en ),
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.i_csr_source (csr_source),
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.i_trap (trap),
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.i_pc (o_ibus_adr[0]),
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.i_mtval (mem_misalign ? bad_adr : bad_pc),
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.i_mcause (mcause),
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.i_d (csr_d_sel ? csr_imm : rs1),
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.o_q (csr_rd));
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@ -376,7 +363,7 @@ module serv_top
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always @(posedge clk) begin
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rvfi_valid <= cnt_done & ctrl_pc_en;
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rvfi_order <= rvfi_order + rvfi_valid;
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rvfi_order <= rvfi_order + {63'd0,rvfi_valid};
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if (o_ibus_cyc & i_ibus_ack)
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rvfi_insn <= i_ibus_rdt;
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if (rd_en)
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@ -420,8 +407,10 @@ module serv_top
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rvfi_mem_wmask <= 4'b0000;
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end
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end
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/* verilator lint_off COMBDLY */
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always @(o_ibus_adr)
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rvfi_pc_wdata <= o_ibus_adr;
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/* verilator lint_on COMBDLY */
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`endif
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