Synthesis fixes

bench/serv_arbiter.v

@@ -1,26 +1,26 @@
 module serv_arbiter
   (
-   input 	 i_ibus_active,
-   input [31:0]  i_wb_cpu_dbus_adr,
-   input [31:0]  i_wb_cpu_dbus_dat,
-   input [3:0] 	 i_wb_cpu_dbus_sel,
-   input 	 i_wb_cpu_dbus_we,
-   input 	 i_wb_cpu_dbus_cyc,
-   output [31:0] o_wb_cpu_dbus_rdt,
-   output 	 o_wb_cpu_dbus_ack,
+   input wire 	      i_ibus_active,
+   input wire [31:0]  i_wb_cpu_dbus_adr,
+   input wire [31:0]  i_wb_cpu_dbus_dat,
+   input wire [3:0]   i_wb_cpu_dbus_sel,
+   input wire 	      i_wb_cpu_dbus_we,
+   input wire 	      i_wb_cpu_dbus_cyc,
+   output wire [31:0] o_wb_cpu_dbus_rdt,
+   output wire 	      o_wb_cpu_dbus_ack,
 
-   input [31:0]  i_wb_cpu_ibus_adr,
-   input 	 i_wb_cpu_ibus_cyc,
-   output [31:0] o_wb_cpu_ibus_rdt,
-   output 	 o_wb_cpu_ibus_ack,
+   input wire [31:0]  i_wb_cpu_ibus_adr,
+   input wire 	      i_wb_cpu_ibus_cyc,
+   output wire [31:0] o_wb_cpu_ibus_rdt,
+   output wire 	      o_wb_cpu_ibus_ack,
 
-   output [31:0] o_wb_cpu_adr,
-   output [31:0] o_wb_cpu_dat,
-   output [3:0]  o_wb_cpu_sel,
-   output 	 o_wb_cpu_we,
-   output 	 o_wb_cpu_cyc,
-   input [31:0]  i_wb_cpu_rdt,
-   input 	 i_wb_cpu_ack);
+   output wire [31:0] o_wb_cpu_adr,
+   output wire [31:0] o_wb_cpu_dat,
+   output wire [3:0]  o_wb_cpu_sel,
+   output wire 	      o_wb_cpu_we,
+   output wire 	      o_wb_cpu_cyc,
+   input wire [31:0]  i_wb_cpu_rdt,
+   input wire 	      i_wb_cpu_ack);
 
    assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
    assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_ibus_active;

bench/serv_mux.v

@@ -6,30 +6,30 @@
  */
 module serv_mux
   (
-   input 	 i_clk,
-   input 	 i_rst,
-   input [31:0]  i_wb_cpu_adr,
-   input [31:0]  i_wb_cpu_dat,
-   input [3:0] 	 i_wb_cpu_sel,
-   input 	 i_wb_cpu_we,
-   input 	 i_wb_cpu_cyc,
-   output [31:0] o_wb_cpu_rdt,
-   output reg 	 o_wb_cpu_ack,
+   input wire 	      i_clk,
+   input wire 	      i_rst,
+   input wire [31:0]  i_wb_cpu_adr,
+   input wire [31:0]  i_wb_cpu_dat,
+   input wire [3:0]   i_wb_cpu_sel,
+   input wire 	      i_wb_cpu_we,
+   input wire 	      i_wb_cpu_cyc,
+   output wire [31:0] o_wb_cpu_rdt,
+   output reg 	      o_wb_cpu_ack,
 
-   output [31:0] o_wb_mem_adr,
-   output [31:0] o_wb_mem_dat,
-   output [3:0]  o_wb_mem_sel,
-   output 	 o_wb_mem_we,
-   output 	 o_wb_mem_cyc,
-   input [31:0]  i_wb_mem_rdt,
+   output wire [31:0] o_wb_mem_adr,
+   output wire [31:0] o_wb_mem_dat,
+   output wire [3:0]  o_wb_mem_sel,
+   output wire 	      o_wb_mem_we,
+   output wire 	      o_wb_mem_cyc,
+   input wire [31:0]  i_wb_mem_rdt,
 
-   output 	 o_wb_gpio_dat,
-   output 	 o_wb_gpio_cyc,
+   output wire 	      o_wb_gpio_dat,
+   output wire 	      o_wb_gpio_cyc,
 
-   output [31:0] o_wb_timer_dat,
-   output 	 o_wb_timer_we,
-   output 	 o_wb_timer_cyc,
-   input [31:0]  i_wb_timer_rdt);
+   output wire [31:0] o_wb_timer_dat,
+   output wire 	      o_wb_timer_we,
+   output wire 	      o_wb_timer_cyc,
+   input wire [31:0]  i_wb_timer_rdt);
 
    parameter sim = 0;
 

bench/serv_wrapper.v

@@ -131,16 +131,12 @@ serv_arbiter serv_arbiter
       .wb_clk_i (wb_clk),
       .wb_rst_i (wb_rst),
       .wb_adr_i (wb_mem_adr[$clog2(MEMORY_SIZE)-1:0]),
-      .wb_stb_i (1'b1),
       .wb_cyc_i (wb_mem_cyc),
-      .wb_cti_i (3'b000),
-      .wb_bte_i (2'b00),
       .wb_we_i  (wb_mem_we) ,
       .wb_sel_i (wb_mem_sel),
       .wb_dat_i (wb_mem_dat),
       .wb_dat_o (wb_mem_rdt),
-      .wb_ack_o (),
-      .wb_err_o ());
+      .wb_ack_o ());
 
    riscv_timer riscv_timer
      (.i_clk    (wb_clk),
@@ -165,7 +161,6 @@ serv_arbiter serv_arbiter
 
       .o_ibus_adr   (wb_cpu_ibus_adr),
       .o_ibus_cyc   (wb_cpu_ibus_cyc),
-      .o_ibus_stb   (),
       .i_ibus_rdt   (wb_cpu_ibus_rdt),
       .i_ibus_ack   (wb_cpu_ibus_ack),
 
@@ -174,7 +169,6 @@ serv_arbiter serv_arbiter
       .o_dbus_sel   (wb_cpu_dbus_sel),
       .o_dbus_we    (wb_cpu_dbus_we),
       .o_dbus_cyc   (wb_cpu_dbus_cyc),
-      .o_dbus_stb   (),
       .i_dbus_rdt   (wb_cpu_dbus_rdt),
       .i_dbus_ack   (wb_cpu_dbus_ack));
 

cores/wb_ram_1.1/rtl/verilog/wb_ram.v

@@ -30,41 +30,34 @@ module wb_ram
    parameter depth = 256,
    parameter aw    = $clog2(depth),
    parameter memfile = "")
-  (input 	   wb_clk_i,
-   input 	   wb_rst_i,
+  (input  wire 	   wb_clk_i,
+   input wire 		wb_rst_i,
 
-   input [aw-1:0]  wb_adr_i,
-   input [dw-1:0]  wb_dat_i,
-   input [3:0] 	   wb_sel_i,
-   input 	   wb_we_i,
-   input [1:0] 	   wb_bte_i,
-   input [2:0] 	   wb_cti_i,
-   input 	   wb_cyc_i,
-   input 	   wb_stb_i,
+   input wire [aw-1:0] 	wb_adr_i,
+   input wire [dw-1:0] 	wb_dat_i,
+   input wire [3:0] 	wb_sel_i,
+   input wire 		wb_we_i,
+   input wire 		wb_cyc_i,
 
-   output reg 	   wb_ack_o = 1'b0,
-   output 	   wb_err_o,
-   output [dw-1:0] wb_dat_o);
+   output reg 		wb_ack_o = 1'b0,
+   output wire [dw-1:0] wb_dat_o);
 
-   wire [31:0]     wb_rdt;
+   wire [31:0] 		wb_rdt;
    reg [31:0]      wb_rdt_r;
    
    always@(posedge wb_clk_i) begin
       //Ack generation
-      wb_ack_o <= wb_cyc_i & wb_stb_i & !wb_ack_o;
+      wb_ack_o <= wb_cyc_i & !wb_ack_o;
 
-      if (wb_cyc_i & wb_stb_i)
+      if (wb_cyc_i)
         wb_rdt_r <= wb_rdt;
       if (wb_rst_i)
         wb_ack_o <= 1'b0;
    end
 
-   assign wb_dat_o = (wb_cyc_i & wb_stb_i) ? wb_rdt : wb_rdt_r;
+   assign wb_dat_o = (wb_cyc_i) ? wb_rdt : wb_rdt_r;
 
-   wire ram_we = wb_we_i & wb_cyc_i & wb_stb_i & wb_ack_o;
-
-   //TODO:ck for burst address errors
-   assign wb_err_o =  1'b0;
+   wire ram_we = wb_we_i & wb_cyc_i & wb_ack_o;
 
    wb_ram_generic
      #(.depth(depth/4),

cores/wb_ram_1.1/rtl/verilog/wb_ram_generic.v

@@ -26,12 +26,12 @@
 module wb_ram_generic
   #(parameter depth=256,
     parameter memfile = "")
-  (input clk,
-   input [3:0]	 we,
-   input [31:0]  din,
-   input [$clog2(depth)-1:0] 	 waddr,
-   input [$clog2(depth)-1:0] 	 raddr,
-   output reg [31:0] dout);
+  (input wire clk,
+   input wire [3:0] 		  we,
+   input wire [31:0] 		  din,
+   input wire [$clog2(depth)-1:0] waddr,
+   input wire [$clog2(depth)-1:0] raddr,
+   output reg [31:0] 		  dout);
 
    reg [31:0] 	 mem [0:depth-1] /* verilator public */;
 
@@ -52,3 +52,4 @@ module wb_ram_generic
    endgenerate
 
 endmodule
+`default_nettype wire

rtl/serv_alu.v

@@ -33,6 +33,7 @@ module serv_alu
    reg         init_r;
    wire        shamt_l;
    wire        shamt_ser;
+   wire        plus_1;
 
    ser_add ser_add_inv_shamt_plus1
      (
@@ -63,7 +64,6 @@ module serv_alu
       .i_d (i_rs1),
       .o_q (result_sh));
 
-   wire       plus_1 = i_en & !en_r;
    wire       b_inv_plus_1;
 
    ser_add ser_add_inv_plus_1
@@ -107,7 +107,7 @@ module serv_alu
    reg last_eq;
 
    wire       result_lt2 = last_eq ? result_lt : msb_lt;
-
+   assign plus_1 = i_en & !en_r;
    assign o_cmp = i_cmp_neg^((i_cmp_sel == ALU_CMP_EQ) ? result_eq : result_lt2);
 
    assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :

rtl/serv_decode.v

@@ -261,7 +261,7 @@ module serv_decode
    wire gate1  = (cnt == 0) & ((opcode == OP_BRANCH) | (opcode == OP_JAL));
    wire gate12 = (cnt < 12) & utype;
 
-   wire o_imm = (!(gate1 | gate12) & (cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]));
+   assign o_imm = (!(gate1 | gate12) & (cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]));
 
    assign o_op_b_source = (opcode == OP_OPIMM)  ? OP_B_SOURCE_IMM :
                           (opcode == OP_BRANCH) ? OP_B_SOURCE_RS2 :

rtl/serv_mem_if.v

@@ -20,12 +20,10 @@ module serv_mem_if
    output wire [3:0]  o_wb_sel,
    output wire 	      o_wb_we ,
    output reg 	      o_wb_cyc = 1'b0,
-   output wire 	      o_wb_stb,
    input wire [31:0]  i_wb_rdt,
    input wire 	      i_wb_ack);
 
    wire          wb_en = o_wb_cyc & i_wb_ack;
-   assign o_wb_stb = o_wb_cyc;
    reg           init_r;
    reg           en_r;
    reg           en_2r;

rtl/serv_regfile.v

@@ -16,6 +16,7 @@ module serv_regfile
 
    wire [31:0]  rs;
 
+   wire [4:0] 	raddr2 = raddr & {5{i_rs_en}};
    reg [31:0] mask;
 
    always @(i_rd_addr)
@@ -58,7 +59,6 @@ module serv_regfile
       if (i_rs_en)
         raddr <= raddr + 1;
    end
-   wire [4:0] raddr2 = raddr & {5{i_rs_en}};
 
    assign o_rs1 = (|i_rs1_addr) ? rs[i_rs1_addr] : 1'b0;
    assign o_rs2 = (|i_rs2_addr) ? rs[i_rs2_addr] : 1'b0;

rtl/serv_top.v

@@ -34,7 +34,6 @@ module serv_top
 `endif
    output wire [31:0] o_ibus_adr,
    output wire 	      o_ibus_cyc,
-   output wire 	      o_ibus_stb,
    input wire [31:0]  i_ibus_rdt,
    input wire 	      i_ibus_ack,
    output wire [31:0] o_dbus_adr,
@@ -42,12 +41,9 @@ module serv_top
    output wire [3:0]  o_dbus_sel,
    output wire 	      o_dbus_we ,
    output wire 	      o_dbus_cyc,
-   output wire 	      o_dbus_stb,
    input wire [31:0]  i_dbus_rdt,
    input wire 	      i_dbus_ack);
 
-   assign o_ibus_stb = o_ibus_cyc;
-
 `include "serv_params.vh"
 
    wire [4:0]    rd_addr;
@@ -190,7 +186,6 @@ module serv_top
       .o_ibus_cyc (o_ibus_cyc),
       .i_ibus_ack (i_ibus_ack));
 
-   //TODO: Pass imm through alu to avoid 5-way mux
    assign rd = (rd_source == RD_SOURCE_CTRL) ? ctrl_rd :
                (rd_source == RD_SOURCE_ALU)  ? alu_rd  :
                (rd_source == RD_SOURCE_MEM)  ? mem_rd  : csr_rd;
@@ -249,7 +244,6 @@ module serv_top
       .o_wb_sel   (o_dbus_sel),
       .o_wb_we    (o_dbus_we ),
       .o_wb_cyc   (o_dbus_cyc),
-      .o_wb_stb   (o_dbus_stb),
       .i_wb_rdt   (i_dbus_rdt),
       .i_wb_ack   (i_dbus_ack));
 

rtl/shift_reg.v

@@ -1,4 +1,5 @@
 module shift_reg
+  #(parameter LEN = 0)
   (
    input wire 		 clk,
    input wire 		 i_en,
@@ -6,7 +7,6 @@ module shift_reg
    output wire 		 o_q,
    output wire [LEN-2:0] o_par);
 
-   parameter LEN = 0;
    parameter INIT = 0;
 
    reg [LEN-1:0] 	 data = INIT;