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Move CSR immediate decoder to immdec

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Olof Kindgren 2020-06-14 01:07:19 +02:00
parent 8775b321d9
commit 1c4e793885
3 changed files with 10 additions and 12 deletions
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10
rtl/serv_decode.v
View file

@ -3,7 +3,6 @@ module serv_decode
(
input wire clk,
//Input
input wire i_cnt_en,
input wire [31:2] i_wb_rdt,
input wire i_wb_en,
//To state
@ -51,7 +50,7 @@ module serv_decode
output wire o_csr_mcause_en,
output wire [1:0] o_csr_source,
output wire o_csr_d_sel,
output wire o_csr_imm,
output wire o_csr_imm_en,
//To top
output wire [3:0] o_immdec_ctrl,
output wire o_op_b_source,
@ -146,7 +145,7 @@ module serv_decode
assign o_csr_source = funct3[1:0];
assign o_csr_d_sel = funct3[2];
assign o_csr_imm = o_rf_rs1_addr[0];
assign o_csr_imm_en = csr_op & o_csr_d_sel;
assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH :
(op26 & !op21) ? CSR_MEPC :
@ -191,11 +190,6 @@ module serv_decode
op21 <= i_wb_rdt[21];
op22 <= i_wb_rdt[22];
op26 <= i_wb_rdt[26];
end
if (i_cnt_en) begin
if (csr_op & o_csr_d_sel)
o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]};
end
end

5
rtl/serv_immdec.v
View file

@ -4,6 +4,8 @@ module serv_immdec
input wire i_clk,
//Input
input wire i_cnt_en,
input wire i_csr_imm_en,
output wire o_csr_imm,
input wire [31:2] i_wb_rdt,
input wire i_wb_en,
input wire i_cnt_done,
@ -20,10 +22,11 @@ module serv_immdec
assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0];
assign o_csr_imm = imm19_12_20[4];
always @(posedge i_clk) begin
if (i_wb_en) begin
signbit <= i_wb_rdt[31];
signbit <= i_wb_rdt[31] & !i_csr_imm_en;
imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]};
imm7 <= i_wb_rdt[7];
imm30_25 <= i_wb_rdt[30:25];

7
rtl/serv_top.v
View file

@ -143,7 +143,7 @@ module serv_top
wire csr_en;
wire [1:0] csr_addr;
wire csr_pc;
wire csr_imm_en;
wire new_irq;
wire trap_taken;
@ -202,7 +202,6 @@ module serv_top
(
.clk (clk),
//Input
.i_cnt_en (cnt_en),
.i_wb_rdt (i_ibus_rdt[31:2]),
.i_wb_en (o_ibus_cyc & i_ibus_ack),
//To state
@ -251,7 +250,7 @@ module serv_top
.o_csr_mcause_en (csr_mcause_en),
.o_csr_source (csr_source),
.o_csr_d_sel (csr_d_sel),
.o_csr_imm (csr_imm),
.o_csr_imm_en (csr_imm_en),
//To top
.o_immdec_ctrl (immdec_ctrl),
.o_rd_csr_en (rd_csr_en),
@ -261,6 +260,8 @@ module serv_top
(
.i_clk (clk),
.i_cnt_en (cnt_en),
.i_csr_imm_en (csr_imm_en),
.o_csr_imm (csr_imm),
.i_wb_rdt (i_ibus_rdt[31:2]),
.i_wb_en (o_ibus_cyc & i_ibus_ack),
.i_ctrl (immdec_ctrl),