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Declare variables/nets before referenced

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dh73 2020-03-25 11:02:43 -06:00 • committed by Olof Kindgren
parent eff17d2f7c
commit 2a7596b51d
2 changed files with 9 additions and 10 deletions
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4
rtl/serv_alu.v
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@ -73,6 +73,8 @@ module serv_alu
reg lt_r;
reg eq_r;
wire lt_sign = i_cnt_done & !i_cmp_uns;
wire eq = (i_rs1 == op_b);
@ -92,8 +94,6 @@ module serv_alu
(i_rd_sel[3] & result_bool);
reg eq_r;
always @(posedge clk) begin
add_cy_r <= i_en & add_cy;
b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy;

15
rtl/serv_decode.v
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@ -180,6 +180,13 @@ module serv_decode
reg [4:0] imm24_20;
reg [4:0] imm11_7;
wire [1:0] m2;
//True for OP-IMM, LOAD, STORE, JALR
//False for LUI, AUIPC, JAL
assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00);
assign m2[1] = opcode[4] & !opcode[0];
wire m3 = opcode[4];
assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift
assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT*
@ -220,14 +227,6 @@ module serv_decode
//False for J type instructions
wire m1 = opcode[3:0] == 4'b1000;
wire [1:0] m2;
assign m2[1] = opcode[4] & !opcode[0];
//True for OP-IMM, LOAD, STORE, JALR
//False for LUI, AUIPC, JAL
assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00);
wire m3 = opcode[4];
assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0];
//0 (OP_B_SOURCE_IMM) when OPIMM