Make bufreg 4-bit compatible

data/verilator_waiver.vlt

@@ -9,4 +9,6 @@ lint_off -rule UNUSED -file "*/serv_decode.v" -lines 8
 //Some variables are only used when we connect an Extension with serv_decode
 lint_off -rule UNUSED -file "*/serv_top.v" -lines 70
 
-
+//Some bufreg signals are not used in 1-bit mode
+lint_off -rule UNUSED -file "*/serv_bufreg.v" -lines 10
+lint_off -rule UNUSED -file "*/serv_bufreg.v" -lines 19-21

rtl/serv_bufreg.v

@@ -7,6 +7,7 @@ module serv_bufreg #(
    //State
    input wire 	      i_cnt0,
    input wire 	      i_cnt1,
+   input wire 	      i_cnt_done,
    input wire 	      i_en,
    input wire 	      i_init,
    input wire           i_mdu_op,
@@ -15,6 +16,9 @@ module serv_bufreg #(
    input wire 	      i_rs1_en,
    input wire 	      i_imm_en,
    input wire 	      i_clr_lsb,
+   input wire 	      i_shift_op,
+   input wire 	      i_right_shift_op,
+   input wire [2:0]   i_shamt,
    input wire 	      i_sh_signed,
    //Data
    input wire [B:0] i_rs1,
@@ -33,6 +37,12 @@ module serv_bufreg #(
 
    assign clr_lsb[0] = i_cnt0 & i_clr_lsb;
 
+   generate
+      if (W > 1) begin : gen_clr_lsb_w_gt_1
+         assign  clr_lsb[B:1] = {B{1'b0}};
+      end
+   endgenerate
+
    assign {c,q} = {1'b0,(i_rs1 & {W{i_rs1_en}})} + {1'b0,(i_imm & {W{i_imm_en}} & ~clr_lsb)} + c_r;
 
    always @(posedge i_clk) begin
@@ -41,8 +51,6 @@ module serv_bufreg #(
       c_r[0] <= c & i_en;
    end
 
-   reg [1:0] lsb;
-
    generate
       if (W == 1) begin : gen_w_eq_1
 	 always @(posedge i_clk) begin
@@ -52,14 +60,36 @@ module serv_bufreg #(
 	    if (i_init ? (i_cnt0 | i_cnt1) : i_en)
 	      data[1:0] <= {i_init ? q : data[2], data[1]};
 	 end
-	 always @(*) lsb = data[1:0];
+	 assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : data[1:0];
 	 assign o_q = data[0] & {W{i_en}};
+      end else if (W == 4) begin : gen_lsb_w_4
+	 reg [1:0] lsb;
+	 reg [W-2:0] data_tail;
+
+	 wire [2:0] shift_amount
+	   = !i_shift_op ? 3'd3 :
+	     i_right_shift_op ? (3'd3+{1'b0,i_shamt[1:0]}) :
+	     ({1'b0,~i_shamt[1:0]});
+
+	 always @(posedge i_clk) begin
+            if (i_en)
+              if (i_cnt0) lsb <= q[1:0];
+	    if (i_en)
+              data <= {i_init ? q : {W{i_sh_signed & data[31]}}, data[31:W]};
+	    if (i_en)
+	      data_tail <= data[B:1] & {B{~i_cnt_done}};
+	 end
+
+	 wire [2*W+B-2:0] muxdata = {data[W+B-1:0],data_tail};
+	 wire [B:0]	  muxout = muxdata[{1'b0,shift_amount}+:W];
+
+	 assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
+	 assign o_q = i_en ? muxout : {W{1'b0}};
       end
    endgenerate
 
 
    assign o_dbus_adr = {data[31:2], 2'b00};
    assign o_ext_rs1  = data;
-   assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
 
 endmodule

rtl/serv_top.v

@@ -369,13 +369,15 @@ module serv_top
       .i_wb_rdt     (i_wb_rdt[31:7]));
 
    serv_bufreg
-      #(.MDU(MDU))
+      #(.MDU(MDU),
+	.W(W))
    bufreg
      (
       .i_clk    (clk),
       //State
       .i_cnt0   (cnt0),
       .i_cnt1   (cnt1),
+      .i_cnt_done (cnt_done),
       .i_en     (bufreg_en),
       .i_init   (init),
       .i_mdu_op (mdu_op),
@@ -385,6 +387,9 @@ module serv_top
       .i_rs1_en    (bufreg_rs1_en),
       .i_imm_en    (bufreg_imm_en),
       .i_clr_lsb   (bufreg_clr_lsb),
+      .i_shift_op   (shift_op),
+      .i_right_shift_op (sh_right),
+      .i_shamt (o_dbus_dat[26:24]),
       //Data
       .i_rs1    (rs1),
       .i_imm    (imm),