mirror of
https://github.com/olofk/serv.git
synced 2025-04-20 11:57:07 -04:00
Create RAM and RF IF with configurable widths
This commit is contained in:
Olof Kindgren
parent
68d8af71f2
commit
31c138e4a1
6 changed files with 210 additions and 223 deletions
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@ -1,87 +0,0 @@
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`default_nettype none
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module serv_regfile
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_go,
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output reg o_ready,
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input wire i_rd_en,
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input wire [4:0] i_rd_addr,
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input wire i_rd,
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input wire [4:0] i_rs1_addr,
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input wire [4:0] i_rs2_addr,
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output wire o_rs1,
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output wire o_rs2);
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reg t;
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always @(posedge i_clk) begin
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o_ready <= t;
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t <= i_go;
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if (i_rst) begin
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o_ready <= 1'b0;
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t <= 1'b0;
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end
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end
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reg rd_r;
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reg [1:0] rdata;
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reg [4:0] rcnt;
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reg [4:0] wcnt;
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reg rs1;
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reg rs2;
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reg rs1_r;
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wire rs1_en = rcnt[0];
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wire rs1_tmp = (rs1_en ? rdata[0] : rs1);
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wire [1:0] wdata = {i_rd, rd_r};
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always @(posedge i_clk) begin
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rd_r <= i_rd;
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if (i_rd_en)
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wcnt <= wcnt + 5'd1;
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if (i_go)
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rcnt <= 5'd0;
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else
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rcnt <= rcnt + 4'd1;
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if (rs1_en) begin
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rs1 <= rdata[1];
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end else begin
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rs2 <= rdata[1];
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end
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rs1_r <= rs1_tmp;
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if (i_rst) begin
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wcnt <= 5'd0;
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end
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end
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assign o_rs1 = rs1_r;
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assign o_rs2 = (rs1_en ? rs2 : rdata[0]);
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wire [8:0] waddr = {i_rd_addr, wcnt[4:1]};
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wire wr_en = wcnt[0] & i_rd_en & (|i_rd_addr);
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wire [8:0] raddr = {!rs1_en ? i_rs1_addr : i_rs2_addr, rcnt[4:1]};
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reg [1:0] memory [0:511];
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always @(posedge i_clk) begin
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if (wr_en)
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memory[waddr] <= wdata;
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rdata <= memory[raddr];
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end
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`ifdef RISCV_FORMAL
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`define SERV_CLEAR_RAM
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`endif
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<512;i=i+1)
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memory[i] = 2'd0;
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`endif
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endmodule
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@ -1,133 +0,0 @@
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`default_nettype none
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module serv_rf_2bit
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_wreq,
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input wire i_rreq,
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output reg o_rgnt,
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input wire [5:0] i_wreg0,
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input wire [5:0] i_wreg1,
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input wire i_wen0,
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input wire i_wen1,
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input wire i_wdata0,
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input wire i_wdata1,
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input wire [5:0] i_rreg0,
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input wire [5:0] i_rreg1,
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output wire o_rdata0,
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output wire o_rdata1);
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/*
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********** Write side ***********
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*/
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reg [4:0] wcnt;
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reg wgo;
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wire [3:0] wslot = wcnt[4:1];
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wire wport = wcnt[0];
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reg wdata0_r;
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reg wdata1_r;
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reg wdata1_2r;
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wire [1:0] wdata = !wport ?
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{i_wdata0, wdata0_r} :
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{wdata1_r, wdata1_2r};
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wire [5:0] wreg = wport ? i_wreg1 : i_wreg0;
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wire [9:0] waddr = {wreg, wslot};
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wire wen = wgo & (wport ? wen1_r : wen0_r);
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reg wreq_r;
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reg wen0_r;
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reg wen1_r;
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always @(posedge i_clk) begin
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wen0_r <= i_wen0;
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wen1_r <= i_wen1;
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wreq_r <= i_wreq;
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wdata0_r <= i_wdata0;
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wdata1_r <= i_wdata1;
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wdata1_2r <= wdata1_r;
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if (wgo)
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wcnt <= wcnt+5'd1;
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if (wreq_r)
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wgo <= 1'b1;
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if (wcnt == 5'b11111)
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wgo <= 1'b0;
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if (i_rst) begin
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wcnt <= 5'd0;
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end
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end
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/*
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********** Read side ***********
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*/
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reg [4:0] rcnt;
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wire [3:0] rslot = rcnt[4:1];
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wire rport = rcnt[0];
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wire [5:0] rreg = rport ? i_rreg1 : i_rreg0;
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wire [9:0] raddr = {rreg, rslot};
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reg [1:0] rdata;
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reg [1:0] rdata0;
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reg rdata1;
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assign o_rdata0 = !rport ? rdata0[0] : rdata0[1];
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assign o_rdata1 = rport ? rdata1 : rdata[0];
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reg rreq_r;
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always @(posedge i_clk) begin
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rcnt <= rcnt+5'd1;
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if (i_rreq)
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rcnt <= 5'd0;
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rreq_r <= i_rreq;
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o_rgnt <= rreq_r;
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if (rport)
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rdata0 <= rdata;
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if (!rport)
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rdata1 <= rdata[1];
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if (i_rst) begin
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o_rgnt <= 1'b0;
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rreq_r <= 1'b0;
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end
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end
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reg [1:0] memory [0:575];
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always @(posedge i_clk) begin
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if (wen)
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`ifdef RISCV_FORMAL
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if (!i_rst)
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`endif
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memory[waddr] <= wdata;
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rdata <= memory[raddr];
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end
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`ifdef RISCV_FORMAL
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`define SERV_CLEAR_RAM
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`endif
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<512;i=i+1)
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memory[i] = 2'd0;
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`endif
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endmodule
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25
rtl/serv_rf_ram.v
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25
rtl/serv_rf_ram.v
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@ -0,0 +1,25 @@
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module serv_rf_ram
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#(parameter width=0,
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parameter depth=32*36/width)
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(input wire i_clk,
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input wire [$clog2(depth)-1:0] i_waddr,
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input wire [width-1:0] i_wdata,
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input wire i_wen,
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input wire [$clog2(depth)-1:0] i_raddr,
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output reg [width-1:0] o_rdata);
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reg [width-1:0] memory [0:depth-1];
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always @(posedge i_clk) begin
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if (i_wen)
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memory[i_waddr] <= i_wdata;
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o_rdata <= memory[i_raddr];
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end
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<depth;i=i+1)
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memory[i] = {width{1'd0}};
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`endif
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endmodule
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160
rtl/serv_rf_ram_if.v
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160
rtl/serv_rf_ram_if.v
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@ -0,0 +1,160 @@
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`default_nettype none
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module serv_rf_ram_if
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#(parameter width=8,
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parameter depth=32*36/width)
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(
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//SERV side
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input wire i_clk,
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input wire i_rst,
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input wire i_wreq,
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input wire i_rreq,
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output reg o_rgnt,
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input wire [5:0] i_wreg0,
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input wire [5:0] i_wreg1,
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input wire i_wen0,
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input wire i_wen1,
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input wire i_wdata0,
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input wire i_wdata1,
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input wire [5:0] i_rreg0,
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input wire [5:0] i_rreg1,
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output wire o_rdata0,
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output wire o_rdata1,
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//RAM side
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output wire [$clog2(depth)-1:0] o_waddr,
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output wire [width-1:0] o_wdata,
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output wire o_wen,
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output wire [$clog2(depth)-1:0] o_raddr,
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input wire [width-1:0] i_rdata);
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localparam l2w = $clog2(width);
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/*
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********** Write side ***********
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*/
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reg [4:0] wcnt;
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reg wgo;
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reg [width-2:0] wdata0_r;
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reg [width-1:0] wdata1_r;
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reg wen0_r;
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reg wen1_r;
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wire wtrig0;
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wire wtrig1;
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generate if (width == 2) begin
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assign wtrig0 = ~wcnt[0];
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assign wtrig1 = wcnt[0];
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end else begin
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reg wtrig0_r;
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always @(posedge i_clk) wtrig0_r <= wtrig0;
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assign wtrig0 = (wcnt[l2w-1:0] == {{l2w-1{1'b1}},1'b0});
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assign wtrig1 = wtrig0_r;
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end
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endgenerate
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assign o_wdata = wtrig1 ?
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wdata1_r :
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{i_wdata0, wdata0_r};
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wire [5:0] wreg = wtrig1 ? i_wreg1 : i_wreg0;
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generate if (width == 32)
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assign o_waddr = wreg;
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else
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assign o_waddr = {wreg, wcnt[4:l2w]};
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endgenerate
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assign o_wen = wgo & ((wtrig0 & wen0_r) | (wtrig1 & wen1_r));
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reg wreq_r;
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reg wreq_edge;
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generate if (width > 2)
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always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]};
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else
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always @(posedge i_clk) wdata0_r <= i_wdata0;
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endgenerate
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always @(posedge i_clk) begin
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wen0_r <= i_wen0;
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wen1_r <= i_wen1;
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wreq_r <= i_wreq;
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wreq_edge <= i_wreq & !wreq_r;
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wdata1_r <= {i_wdata1,wdata1_r[width-1:1]};
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if (wgo)
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wcnt <= wcnt+5'd1;
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if (wreq_r) begin
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wgo <= 1'b1;
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end
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if (wcnt == 5'b11111)
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wgo <= 1'b0;
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if (i_rst) begin
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wcnt <= 5'd0;
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end
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end
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/*
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********** Read side ***********
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*/
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reg [4:0] rcnt;
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wire rtrig0;
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reg rtrig1;
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wire [5:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
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generate if (width == 32)
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assign o_raddr = rreg;
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else
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assign o_raddr = {rreg, rcnt[4:l2w]};
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endgenerate
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reg [width-1:0] rdata0;
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reg [width-2:0] rdata1;
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assign o_rdata0 = rdata0[0];
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assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0];
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assign rtrig0 = (rcnt[l2w-1:0] == 1);
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reg rreq_r;
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generate if (width>2)
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always @(posedge i_clk) begin
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rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize?
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if (rtrig1)
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rdata1[width-2:0] <= i_rdata[width-1:1];
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end
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else
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always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
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endgenerate
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always @(posedge i_clk) begin
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rtrig1 <= rtrig0;
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rcnt <= rcnt+5'd1;
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if (i_rreq)
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rcnt <= 5'd0;
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rreq_r <= i_rreq;
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o_rgnt <= rreq_r;
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rdata0 <= {1'b0,rdata0[width-1:1]};
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if (rtrig0)
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rdata0 <= i_rdata;
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if (i_rst) begin
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o_rgnt <= 1'b0;
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rreq_r <= 1'b0;
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end
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end
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endmodule
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@ -41,6 +41,8 @@ module serv_rf_top
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input wire i_dbus_ack);
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parameter RESET_PC = 32'd0;
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parameter RF_WIDTH = 2;
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localparam RF_L2W = $clog2(RF_WIDTH);
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wire rf_wreq;
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wire rf_rreq;
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@ -56,7 +58,13 @@ module serv_rf_top
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wire rdata0;
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wire rdata1;
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serv_rf_2bit rf
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wire [10-RF_L2W:0] waddr;
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wire [RF_WIDTH-1:0] wdata;
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wire wen;
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wire [10-RF_L2W:0] raddr;
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wire [RF_WIDTH-1:0] rdata;
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serv_rf_ram_if #(.width (RF_WIDTH)) rf_ram_if
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(.i_clk (clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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@ -71,7 +79,20 @@ module serv_rf_top
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1));
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.o_rdata1 (rdata1),
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.o_waddr (waddr),
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.o_wdata (wdata),
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.o_wen (wen),
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.o_raddr (raddr),
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.i_rdata (rdata));
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serv_rf_ram #(.width (RF_WIDTH)) rf_ram
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(.i_clk (clk),
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.i_waddr (waddr),
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.i_wdata (wdata),
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.i_wen (wen),
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.i_raddr (raddr),
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.o_rdata (rdata));
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serv_top
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#(.RESET_PC (RESET_PC))
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@ -17,7 +17,8 @@ filesets:
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- rtl/serv_decode.v
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- rtl/serv_mem_if.v
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- rtl/serv_rf_if.v
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- rtl/serv_rf_2bit.v
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- rtl/serv_rf_ram_if.v
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- rtl/serv_rf_ram.v
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- rtl/serv_state.v
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- rtl/serv_top.v
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- rtl/serv_rf_top.v
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