changed parameter to single bit

rtl/serv_bufreg.v

@@ -1,5 +1,5 @@
 module serv_bufreg #(
-      parameter MDU = 0
+      parameter [0:0] MDU = 0
 )(
    input wire 	      i_clk,
    //State

rtl/serv_decode.v

@@ -1,7 +1,7 @@
 `default_nettype none
 module serv_decode 
   #(parameter [0:0] PRE_REGISTER = 1,
-    parameter       MDU = 0)
+    parameter [0:0] MDU = 0)
   (
    input wire        clk,
    //Input

rtl/serv_mem_if.v

@@ -1,7 +1,7 @@
 `default_nettype none
 module serv_mem_if
   #(parameter WITH_CSR = 1,
-    parameter MDU = 0)
+    parameter [0:0] MDU = 0)
   (
    input wire 	      i_clk,
    //State

rtl/serv_rf_top.v

@@ -6,7 +6,7 @@ module serv_rf_top
        0 : Less hardware. Slow execution  of multipy/devide instructions
        1 : Increase hardware. Fast execution of multipy/devide instructions
     */
-    parameter MDU = 0,
+    parameter [0:0] MDU = 0,
     /* Register signals before or after the decoder
        0 : Register after the decoder. Faster but uses more resources
        1 : (default) Register before the decoder. Slower but uses less resources
@@ -203,8 +203,8 @@ generate
     assign dbus_rdt = ext_mdu_ready ? ext_mdu_rd:i_dbus_rdt;
     assign dbus_ack = i_dbus_ack | ext_mdu_ready;
   end else begin
-    assign dbus_rdt = 32'b0;  
-    assign dbus_ack =  1'b0;
+    assign dbus_rdt = i_dbus_rdt;  
+    assign dbus_ack = i_dbus_ack;
   end
   assign ext_mdu_rs2 = o_dbus_dat;
 endgenerate

rtl/serv_top.v

@@ -5,7 +5,7 @@ module serv_top
     parameter PRE_REGISTER = 1,
     parameter RESET_STRATEGY = "MINI",
     parameter RESET_PC = 32'd0,
-    parameter MDU = 1'b0)
+    parameter [0:0] MDU = 1'b0)
    (
    input wire 		      clk,
    input wire 		      i_rst,