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https://github.com/olofk/serv.git
synced 2025-04-20 03:47:09 -04:00
Fix misaligned jumps
This commit is contained in:
Olof Kindgren
parent
f12f8ecf61
commit
34fc93ba09
3 changed files with 72 additions and 36 deletions
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@ -3,6 +3,8 @@ module serv_ctrl
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(
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input clk,
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input i_en,
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input i_pc_en,
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input i_cnt_done,
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input i_jump,
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input i_offset,
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input i_rs1,
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@ -12,6 +14,7 @@ module serv_ctrl
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input i_csr_pc,
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output o_rd,
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output o_bad_pc,
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output reg o_misalign = 1'b0,
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output [31:0] o_ibus_adr,
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output reg o_ibus_cyc = 1'b0,
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input i_ibus_ack);
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@ -29,17 +32,17 @@ module serv_ctrl
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wire offset_a;
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assign plus_4 = en_2r & !en_3r;
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assign plus_4 = en_pc_2r & !en_pc_3r;
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assign o_ibus_adr[0] = pc;
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assign o_bad_pc = pc_plus_offset;
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assign o_bad_pc = pc_plus_offset_aligned;
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ser_add ser_add_pc_plus_4
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(
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.clk (clk),
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.a (pc),
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.b (plus_4),
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.clr (!i_en),
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.clr (i_cnt_done),
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.q (pc_plus_4),
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.o_v ());
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@ -50,13 +53,13 @@ module serv_ctrl
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pc_reg
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(
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.clk (clk),
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.i_en (i_en),
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.i_en (i_pc_en),
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.i_d (new_pc),
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.o_q (pc),
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.o_par (o_ibus_adr[31:1])
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);
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assign new_pc = i_trap ? i_csr_pc : i_jump ? pc_plus_offset_aligned : pc_plus_4;
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assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
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assign o_rd = i_auipc ? pc_plus_offset_aligned : pc_plus_4;
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assign offset_a = i_jalr ? i_rs1 : pc;
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@ -66,23 +69,31 @@ module serv_ctrl
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.clk (clk),
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.a (offset_a),
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.b (i_offset),
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.clr (!i_en),
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.clr (i_cnt_done),
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.q (pc_plus_offset),
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.o_v ());
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wire pc_plus_offset_aligned = pc_plus_offset & en_r;
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wire pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
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reg en_r = 1'b1;
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reg en_r = 1'b0;
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reg en_2r = 1'b0;
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reg en_3r = 1'b0;
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reg en_pc_r = 1'b1;
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reg en_pc_2r = 1'b0;
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reg en_pc_3r = 1'b0;
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always @(posedge clk) begin
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en_r <= i_en;
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en_2r <= en_r;
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en_3r <= en_2r;
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en_pc_r <= i_pc_en;
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en_pc_2r <= en_pc_r;
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en_pc_3r <= en_pc_2r;
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if (en_r & !i_en)
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if (en_r & !en_2r)
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o_misalign <= pc_plus_offset;
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if (en_pc_r & !i_pc_en)
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o_ibus_cyc <= 1'b1;
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else if (o_ibus_cyc & i_ibus_ack)
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o_ibus_cyc <= 1'b0;
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@ -1,15 +1,19 @@
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`default_nettype none
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module serv_decode
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(
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input clk,
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input [31:0] i_wb_rdt,
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input i_wb_en,
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output o_cnt_done,
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output o_ibus_active,
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output o_ctrl_en,
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output o_ctrl_pc_en,
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output o_ctrl_jump,
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output o_ctrl_jalr,
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output o_ctrl_auipc,
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output reg o_ctrl_trap = 1'b0,
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output o_ctrl_trap,
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output o_ctrl_mret,
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input i_ctrl_misalign,
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output o_rf_rd_en,
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output reg [4:0] o_rf_rd_addr,
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output o_rf_rs_en,
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@ -46,7 +50,8 @@ module serv_decode
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localparam [1:0]
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IDLE = 2'd0,
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INIT = 2'd1,
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RUN = 2'd2;
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RUN = 2'd2,
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TRAP = 2'd3;
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localparam [4:0]
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OP_LOAD = 5'b00000,
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@ -68,21 +73,30 @@ module serv_decode
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wire mem_op;
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wire shift_op;
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wire csr_op;
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wire slt_op;
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wire branch_op;
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wire jump_misaligned;
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reg signbit;
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assign o_cnt_done = cnt_done;
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assign o_ibus_active = (state == IDLE);
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assign mem_op = (opcode == OP_LOAD) | (opcode == OP_STORE);
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assign shift_op = ((opcode == OP_OPIMM) & (o_funct3[1:0] == 2'b01)) |
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((opcode == OP_OP ) & (o_funct3[1:0] == 2'b01));
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assign o_ctrl_en = running;
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assign slt_op = (((opcode == OP_OPIMM) | (opcode == OP_OP)) &
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(o_funct3[2:1] == 2'b01));
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assign branch_op = (opcode == OP_BRANCH);
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assign o_ctrl_pc_en = running | o_ctrl_trap;
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assign o_ctrl_jump = (opcode == OP_JAL) |
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(opcode == OP_JALR) |
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((opcode == OP_BRANCH) & i_alu_cmp);
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(branch_op & i_alu_cmp);
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assign o_ctrl_jalr = (opcode == OP_JALR);
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@ -92,25 +106,27 @@ module serv_decode
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assign o_rf_rd_en = running & !o_ctrl_trap &
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(opcode != OP_STORE) &
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(opcode != OP_BRANCH);
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!branch_op;
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assign o_rf_rs_en = cnt_en;
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assign o_alu_en = cnt_en;
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assign o_ctrl_en = cnt_en;
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assign o_alu_init = (state == INIT);
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assign o_alu_sub = (opcode == OP_OP) ? signbit /* ? 1'b1*/ :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b100)) ? 1'b1 :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b101)) ? 1'b1 :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b110)) ? 1'b1 :
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(branch_op & (o_funct3 == 3'b100)) ? 1'b1 :
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(branch_op & (o_funct3 == 3'b101)) ? 1'b1 :
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(branch_op & (o_funct3 == 3'b110)) ? 1'b1 :
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((opcode == OP_OPIMM) & (o_funct3 == 3'b000)) ? 1'b0 :
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1'bx;
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assign o_alu_cmp_neg = (opcode == OP_BRANCH) & o_funct3[0];
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assign o_alu_cmp_neg = branch_op & o_funct3[0];
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assign o_csr_en = ((opcode == OP_SYSTEM) & (|o_funct3) | o_ctrl_mret | o_ctrl_trap) & running;
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assign o_csr_en = ((opcode == OP_SYSTEM) & (|o_funct3) | o_ctrl_mret | o_ctrl_trap) & (running | o_ctrl_trap);
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always @(o_funct3) begin
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casez (o_funct3)
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@ -177,7 +193,7 @@ module serv_decode
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assign o_mem_init = mem_op & (state == INIT);
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assign jal_misalign = imm[21] & (opcode == OP_JAL);
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wire jal_misalign = imm[21] & (opcode == OP_JAL);
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reg [4:0] opcode;
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reg [31:0] imm;
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@ -261,41 +277,41 @@ module serv_decode
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always @(posedge clk)
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go <= i_wb_en;
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wire cnt_en =
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(state == RUN) |
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(state == INIT);
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wire cnt_en = (state != IDLE);
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wire cnt_done = cnt == 31;
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assign running = (state == RUN);
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assign o_ctrl_trap = (state == TRAP);
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always @(posedge clk) begin
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if (cnt_done)
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o_ctrl_trap <= i_mem_misalign;
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if (go)
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o_ctrl_trap <= jal_misalign;
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state <= state;
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case (state)
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IDLE : begin
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if (go) begin
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state <= RUN;
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if ((opcode == OP_BRANCH) |
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(((opcode == OP_OPIMM) | (opcode == OP_OP)) &
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(o_funct3[2:1] == 2'b01)) |
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if (branch_op |
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slt_op | (opcode == OP_JAL) | (opcode == OP_JALR) |
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mem_op | shift_op)
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state <= INIT;
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end
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if (i_mem_dbus_ack | i_mem_misalign)
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if (i_mem_dbus_ack)
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state <= RUN;
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end
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INIT : begin
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if (cnt_done)
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state <= mem_op ? IDLE : RUN;
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state <= (i_mem_misalign | (o_ctrl_jump & i_ctrl_misalign) /*| jal_misalign*/) ? TRAP :
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mem_op ? IDLE : RUN;
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end
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RUN : begin
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if (cnt_done)
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state <= IDLE;
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end
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default : state <= 3'bxxx;
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TRAP : begin
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if (cnt_done)
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state <= IDLE;
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end
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default : state <= 2'bxx;
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endcase
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cnt <= cnt + {4'd0,cnt_en};
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@ -61,6 +61,8 @@ module serv_top
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wire rd;
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wire ctrl_en;
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wire ctrl_pc_en;
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wire ctrl_misalign;
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wire jump;
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wire jalr;
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wire auipc;
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@ -70,6 +72,7 @@ module serv_top
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wire imm;
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wire trap;
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wire cnt_done;
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wire [2:0] funct3;
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wire alu_en;
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@ -113,13 +116,16 @@ module serv_top
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.clk (clk),
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.i_wb_rdt (i_ibus_rdt),
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.i_wb_en (o_ibus_cyc & i_ibus_ack),
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.o_cnt_done (cnt_done),
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.o_ibus_active (),
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.o_ctrl_en (ctrl_en),
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.o_ctrl_pc_en (ctrl_pc_en),
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.o_ctrl_jump (jump),
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.o_ctrl_jalr (jalr),
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.o_ctrl_auipc (auipc),
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.o_ctrl_trap (trap),
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.o_ctrl_mret (mret),
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.i_ctrl_misalign(ctrl_misalign),
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.o_funct3 (funct3),
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.o_alu_en (alu_en),
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.o_alu_init (alu_init),
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@ -157,6 +163,8 @@ module serv_top
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(
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.clk (clk),
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.i_en (ctrl_en),
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.i_pc_en (ctrl_pc_en),
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.i_cnt_done (cnt_done),
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.i_jump (jump),
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.i_offset (offset),
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.i_rs1 (rs1),
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@ -166,6 +174,7 @@ module serv_top
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.i_csr_pc (csr_rd),
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.o_rd (ctrl_rd),
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.o_bad_pc (bad_pc),
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.o_misalign (ctrl_misalign),
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.o_ibus_adr (o_ibus_adr),
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_ack (i_ibus_ack));
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@ -255,10 +264,10 @@ module serv_top
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`ifdef RISCV_FORMAL
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reg [31:0] rs1_fv, rs2_fv, rd_fv;
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reg [31:0] pc = RESET_PC;
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reg ctrl_en_r = 1'b0;
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reg ctrl_pc_en_r = 1'b0;
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always @(posedge clk) begin
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ctrl_en_r <= ctrl_en;
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ctrl_pc_en_r <= ctrl_pc_en;
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if (rs_en) begin
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rs1_fv <= {rs1,rs1_fv[31:1]};
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rs2_fv <= {rs2,rs2_fv[31:1]};
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@ -267,7 +276,7 @@ module serv_top
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rd_fv <= {rd,rd_fv[31:1]};
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end
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rvfi_valid <= 1'b0;
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if (ctrl_en_r & !ctrl_en) begin
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if (ctrl_pc_en_r & !ctrl_pc_en) begin
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pc <= o_ibus_adr;
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rvfi_valid <= 1'b1;
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rvfi_order <= rvfi_order + 1;
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