Remove unused signals

rtl/serv_ctrl.v

@@ -6,7 +6,7 @@ module serv_ctrl
    //State
    input wire 	      i_pc_en,
    input wire [4:2]   i_cnt,
-   input wire [2:1]   i_cnt_r,
+   input wire [2:2]   i_cnt_r,
    input wire 	      i_cnt_done,
    //Control
    input wire 	      i_jump,

rtl/serv_decode.v

@@ -5,7 +5,7 @@ module serv_decode
    //Input
    input wire 	     i_cnt_en,
    input wire 	     i_cnt_done,
-   input wire [31:0] i_wb_rdt,
+   input wire [31:2] i_wb_rdt,
    input wire 	     i_wb_en,
    input wire 	     i_alu_cmp,
    //To state

rtl/serv_mem_if.v

@@ -2,7 +2,6 @@
 module serv_mem_if
   (
    input wire 	      i_clk,
-   input wire 	      i_rst,
    input wire 	      i_en,
    input wire 	      i_init,
    input wire 	      i_mem_op,
@@ -41,9 +40,6 @@ module serv_mem_if
    wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
    assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
 
-
-   wire       upper_half = i_lsb[1];
-
    assign o_wb_sel[3] = i_word | (i_half & i_lsb[1]) | (i_lsb == 2'b11);
    assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
    assign o_wb_sel[1] = ((i_word | i_half) & !i_lsb[1]) | (i_lsb == 2'b01);

rtl/serv_rf_if.v

@@ -1,10 +1,6 @@
 `default_nettype none
 module serv_rf_if
-  (
-   input wire 	     i_clk,
-   input wire 	     i_rst,
-
-   //RF Interface
+  (//RF Interface
    output wire [5:0] o_wreg0,
    output wire [5:0] o_wreg1,
    output wire 	     o_wen0,

rtl/serv_rf_ram_if.v

@@ -72,7 +72,6 @@ module serv_rf_ram_if
    assign o_wen = wgo & ((wtrig0 & wen0_r) | (wtrig1 & wen1_r));
 
    reg 	      wreq_r;
-   reg 	      wreq_edge;
 
    generate if (width > 2)
      always @(posedge i_clk) wdata0_r  <= {i_wdata0, wdata0_r[width-2:1]};
@@ -84,7 +83,6 @@ module serv_rf_ram_if
       wen0_r    <= i_wen0;
       wen1_r    <= i_wen1;
       wreq_r    <= i_wreq | rgnt;
-      wreq_edge <= i_wreq & !wreq_r;
 
       wdata1_r  <= {i_wdata1,wdata1_r[width-1:1]};
 

rtl/serv_top.v

@@ -189,7 +189,7 @@ module serv_top
       //Input
       .i_cnt_en           (cnt_en),
       .i_cnt_done         (cnt_done),
-      .i_wb_rdt           (i_ibus_rdt),
+      .i_wb_rdt           (i_ibus_rdt[31:2]),
       .i_wb_en            (o_ibus_cyc & i_ibus_ack),
       .i_alu_cmp          (alu_cmp),
       //To state
@@ -271,7 +271,7 @@ module serv_top
       //State
       .i_pc_en    (ctrl_pc_en),
       .i_cnt      (cnt[4:2]),
-      .i_cnt_r    (cnt_r[2:1]),
+      .i_cnt_r    (cnt_r[2]),
       .i_cnt_done (cnt_done),
       //Control
       .i_jump     (jump),
@@ -319,10 +319,7 @@ module serv_top
    wire 	 rf_csr_out;
 
    serv_rf_if rf_if
-     (
-      .i_clk       (clk),
-      .i_rst       (i_rst),
-      //RF interface
+     (//RF interface
       .o_wreg0     (o_wreg0),
       .o_wreg1     (o_wreg1),
       .o_wen0      (o_wen0),
@@ -369,7 +366,6 @@ module serv_top
    serv_mem_if mem_if
      (
       .i_clk    (clk),
-      .i_rst    (i_rst),
       .i_en     (cnt_en),
       .i_init   (init),
       .i_mem_op (mem_op),

servant/servant.v

@@ -127,7 +127,7 @@ servant_arbiter servant_arbiter
    ram
      (// Wishbone interface
       .i_wb_clk (wb_clk),
-      .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:0]),
+      .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
       .i_wb_cyc (wb_mem_cyc),
       .i_wb_we  (wb_mem_we) ,
       .i_wb_sel (wb_mem_sel),
@@ -139,7 +139,6 @@ servant_arbiter servant_arbiter
      #(.WIDTH (32))
    timer
      (.i_clk    (wb_clk),
-      .i_rst    (wb_rst),
       .o_irq    (timer_irq),
       .i_wb_cyc (wb_timer_cyc),
       .i_wb_we  (wb_timer_we) ,

servant/servant_ram.v

@@ -5,7 +5,7 @@ module servant_ram
     parameter aw    = $clog2(depth),
     parameter memfile = "")
    (input wire 		i_wb_clk,
-    input wire [aw-1:0] i_wb_adr,
+    input wire [aw-1:2] i_wb_adr,
     input wire [31:0] 	i_wb_dat,
     input wire [3:0] 	i_wb_sel,
     input wire 		i_wb_we,

servant/servant_timer.v

@@ -3,7 +3,6 @@ module servant_timer
   #(parameter WIDTH = 16,
     parameter DIVIDER = 0)
   (input wire 	     i_clk,
-   input wire 	     i_rst,
    output reg 	     o_irq,
    input wire [31:0] i_wb_dat,
    input wire 	     i_wb_we,