mirror of
https://github.com/olofk/serv.git
synced 2025-06-27 17:00:33 -04:00
Introduce width parameter
Expose the width (or W internally) parameter to set the SERV datapath width. Note: Only width=1 is function at this time.
This commit is contained in:
Olof Kindgren
parent
1c5d44e5c4
commit
376dcd701d
9 changed files with 79 additions and 51 deletions
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@ -8,6 +8,7 @@ module servant_sim
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parameter memfile = "";
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parameter memsize = 8192;
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parameter width = 1;
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parameter with_csr = 1;
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parameter compressed = 0;
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parameter align = compressed;
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@ -22,6 +23,7 @@ module servant_sim
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servant
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#(.memfile (memfile),
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.memsize (memsize),
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.width (width),
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.sim (1),
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.with_csr (with_csr),
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.compress (compressed[0:0]),
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@ -3,8 +3,13 @@ module servant_tb;
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parameter memfile = "hello_uart.hex";
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parameter memsize = 8192;
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parameter width = 1;
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parameter with_csr = 1;
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localparam baud_rate =
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(width == 4) ? 57600*3 :
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57600;
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reg wb_clk = 1'b0;
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reg wb_rst = 1'b1;
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@ -15,11 +20,12 @@ module servant_tb;
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vlog_tb_utils vtu();
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uart_decoder #(57600) uart_decoder (q);
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uart_decoder #(baud_rate) uart_decoder (q);
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servant_sim
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#(.memfile (memfile),
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.memsize (memsize),
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.width (width),
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.with_csr (with_csr))
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dut
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(.wb_clk (wb_clk),
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@ -1,14 +1,12 @@
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`verilator_config
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// Bits [1:0] in i_wb_rdt are not used at all
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lint_off -rule UNUSED -file "*/serv_top.v" -lines 179
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lint_off -rule UNUSED -file "*/serv_top.v" -lines 181
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//Some bits in the instruction word are not used in serv_decode but it's easier
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//to just send in the whole word than picking out bits
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lint_off -rule UNUSED -file "*/serv_decode.v" -lines 8
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lint_off -rule UNUSED -file "*/serv_top.v" -lines 177
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//Some variables are only used when we connect an Extension with serv_decode
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lint_off -rule UNUSED -file "*/serv_top.v" -lines 67
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lint_off -rule UNUSED -file "*/serv_top.v" -lines 69
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@ -28,7 +28,8 @@ module serv_rf_top
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*/
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parameter RESET_STRATEGY = "MINI",
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parameter WITH_CSR = 1,
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parameter RF_WIDTH = 2,
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parameter W = 1,
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parameter RF_WIDTH = W * 2,
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parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
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(
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input wire clk,
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@ -86,13 +87,13 @@ module serv_rf_top
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wire [4+WITH_CSR:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [W-1:0] wdata0;
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wire [W-1:0] wdata1;
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wire [4+WITH_CSR:0] rreg0;
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wire [4+WITH_CSR:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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wire [W-1:0] rdata0;
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wire [W-1:0] rdata1;
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wire [RF_L2D-1:0] waddr;
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wire [RF_WIDTH-1:0] wdata;
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@ -104,7 +105,8 @@ module serv_rf_top
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serv_rf_ram_if
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#(.width (RF_WIDTH),
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.reset_strategy (RESET_STRATEGY),
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.csr_regs (CSR_REGS))
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.csr_regs (CSR_REGS),
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.W(W))
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rf_ram_if
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(.i_clk (clk),
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.i_rst (i_rst),
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@ -147,7 +149,8 @@ module serv_rf_top
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.WITH_CSR (WITH_CSR),
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.MDU(MDU),
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.COMPRESSED(COMPRESSED),
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.ALIGN(ALIGN))
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.ALIGN(ALIGN),
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.W(W))
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cpu
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(
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.clk (clk),
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@ -2,6 +2,8 @@
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module serv_top
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#(parameter WITH_CSR = 1,
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parameter W = 1,
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parameter B = W-1,
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parameter PRE_REGISTER = 1,
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parameter RESET_STRATEGY = "MINI",
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parameter RESET_PC = 32'd0,
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@ -43,12 +45,12 @@ module serv_top
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output wire [4+WITH_CSR:0] o_wreg1,
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output wire o_wen0,
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output wire o_wen1,
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output wire o_wdata0,
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output wire o_wdata1,
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output wire [B:0] o_wdata0,
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output wire [B:0] o_wdata1,
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output wire [4+WITH_CSR:0] o_rreg0,
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output wire [4+WITH_CSR:0] o_rreg1,
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input wire i_rdata0,
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input wire i_rdata1,
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input wire [B:0] i_rdata0,
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input wire [B:0] i_rdata1,
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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@ -92,10 +94,10 @@ module serv_top
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wire rd_alu_en;
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wire rd_csr_en;
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wire rd_mem_en;
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wire ctrl_rd;
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wire alu_rd;
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wire mem_rd;
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wire csr_rd;
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wire [B:0] ctrl_rd;
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wire [B:0] alu_rd;
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wire [B:0] mem_rd;
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wire [B:0] csr_rd;
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wire mtval_pc;
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wire ctrl_pc_en;
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@ -103,7 +105,7 @@ module serv_top
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wire jal_or_jalr;
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wire utype;
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wire mret;
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wire imm;
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wire [B:0] imm;
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wire trap;
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wire pc_rel;
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wire iscomp;
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@ -127,8 +129,8 @@ module serv_top
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wire bufreg_rs1_en;
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wire bufreg_imm_en;
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wire bufreg_clr_lsb;
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wire bufreg_q;
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wire bufreg2_q;
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wire [B:0] bufreg_q;
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wire [B:0] bufreg2_q;
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wire [31:0] dbus_rdt;
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wire dbus_ack;
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@ -139,11 +141,11 @@ module serv_top
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wire alu_cmp;
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wire [2:0] alu_rd_sel;
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wire rs1;
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wire rs2;
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wire [B:0] rs1;
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wire [B:0] rs2;
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wire rd_en;
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wire op_b;
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wire [B:0] op_b;
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wire op_b_sel;
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wire mem_signed;
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@ -156,20 +158,20 @@ module serv_top
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wire mem_misalign;
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wire bad_pc;
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wire [B:0] bad_pc;
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wire csr_mstatus_en;
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wire csr_mie_en;
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wire csr_mcause_en;
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wire [1:0] csr_source;
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wire csr_imm;
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wire [B:0] csr_imm;
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wire csr_d_sel;
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wire csr_en;
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wire [1:0] csr_addr;
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wire csr_pc;
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wire [B:0] csr_pc;
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wire csr_imm_en;
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wire csr_in;
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wire rf_csr_out;
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wire [B:0] csr_in;
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wire [B:0] rf_csr_out;
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wire dbus_en;
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wire new_irq;
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@ -226,7 +228,8 @@ module serv_top
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#(.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR[0:0]),
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.MDU(MDU),
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.ALIGN(ALIGN))
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.ALIGN(ALIGN),
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.W(W))
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state
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(
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.i_clk (clk),
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@ -420,7 +423,8 @@ module serv_top
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serv_ctrl
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#(.RESET_PC (RESET_PC),
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.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR))
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.WITH_CSR (WITH_CSR),
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.W (W))
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ctrl
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(
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.clk (clk),
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@ -447,7 +451,7 @@ module serv_top
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//External
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.o_ibus_adr (wb_ibus_adr));
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serv_alu alu
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serv_alu #(.W (W)) alu
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(
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.clk (clk),
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//State
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@ -467,7 +471,7 @@ module serv_top
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.o_rd (alu_rd));
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serv_rf_if
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#(.WITH_CSR (WITH_CSR))
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#(.WITH_CSR (WITH_CSR), .W(W))
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rf_if
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(//RF interface
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.i_cnt_en (cnt_en),
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@ -485,7 +489,7 @@ module serv_top
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//Trap interface
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.i_trap (trap),
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.i_mret (mret),
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.i_mepc (wb_ibus_adr[0]),
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.i_mepc (wb_ibus_adr[B:0]),
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.i_mtval_pc (mtval_pc),
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.i_bufreg_q (bufreg_q),
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.i_bad_pc (bad_pc),
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@ -516,7 +520,8 @@ module serv_top
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.o_csr (rf_csr_out));
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serv_mem_if
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#(.WITH_CSR (WITH_CSR[0:0]))
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#(.WITH_CSR (WITH_CSR[0:0]),
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.W (W))
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mem_if
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(
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.i_clk (clk),
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@ -539,7 +544,8 @@ module serv_top
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generate
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if (|WITH_CSR) begin : gen_csr
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serv_csr
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#(.RESET_STRATEGY (RESET_STRATEGY))
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#(.RESET_STRATEGY (RESET_STRATEGY),
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.W(W))
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csr
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(
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.i_clk (clk),
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@ -574,8 +580,8 @@ module serv_top
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.i_rs1 (rs1),
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.o_q (csr_rd));
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end else begin : gen_no_csr
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assign csr_in = 1'b0;
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assign csr_rd = 1'b0;
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assign csr_in = {W{1'b0}};
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assign csr_rd = {W{1'b0}};
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assign new_irq = 1'b0;
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end
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endgenerate
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@ -597,7 +603,7 @@ module serv_top
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/* Store data written to rd */
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if (o_wen0)
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rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]};
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rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:W]};
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if (cnt_done & ctrl_pc_en) begin
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rvfi_pc_rdata <= pc;
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@ -626,8 +632,8 @@ module serv_top
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rvfi_rd_addr <= rd_addr;
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end
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if (rs_en) begin
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rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]};
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rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]};
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rvfi_rs1_rdata <= {(!immdec_en[1] ? rs1 : {W{1'b0}}),rvfi_rs1_rdata[31:W]};
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rvfi_rs2_rdata <= {(!immdec_en[2] ? rs2 : {W{1'b0}}),rvfi_rs2_rdata[31:W]};
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end
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if (i_dbus_ack) begin
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@ -580,6 +580,7 @@ targets:
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filesets : [soc, servant_tb]
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parameters :
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- RISCV_FORMAL
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- width
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- "mdu? (MDU=1)"
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- SERV_CLEAR_RAM=true
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- firmware
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@ -649,6 +650,7 @@ targets:
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- uart_baudrate
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- vcd
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- vcd_start
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- width
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- compressed
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- align
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- with_csr=1
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@ -744,6 +746,11 @@ parameters:
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description : Delay start of VCD dumping until the specified time
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paramtype : plusarg
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width:
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datatype : int
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description : Interal datapath width (1=SERV, 4=QERV)
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paramtype : vlogparam
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with_csr:
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datatype : int
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description : Enable/Disable CSR support
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@ -8,6 +8,7 @@ module servant
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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parameter reset_strategy = "MINI";
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parameter width = 1;
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parameter sim = 0;
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parameter with_csr = 1;
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parameter [0:0] compress = 0;
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@ -23,7 +24,7 @@ module servant
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localparam aw = $clog2(memsize);
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localparam csr_regs = with_csr*4;
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localparam rf_width = 2;
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localparam rf_width = width * 2;
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localparam rf_l2d = $clog2((32+csr_regs)*32/rf_width);
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wire timer_irq;
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@ -133,7 +134,7 @@ module servant
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.o_rdata (rf_rdata));
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servile
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#(.rf_width (rf_width),
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#(.width (width),
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.sim (sim[0]),
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.with_c (compress[0]),
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.with_csr (with_csr[0]),
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@ -159,7 +160,7 @@ module servant
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.o_wb_ext_stb (wb_ext_stb),
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.i_wb_ext_rdt (wb_ext_rdt),
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.i_wb_ext_ack (wb_ext_ack),
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.o_rf_waddr (rf_waddr),
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.o_rf_wdata (rf_wdata),
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.o_rf_wen (rf_wen),
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@ -8,14 +8,16 @@
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`default_nettype none
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module servile
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#(
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parameter width = 1,
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parameter reset_pc = 32'h00000000,
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parameter reset_strategy = "MINI",
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parameter rf_width = 8,
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parameter rf_width = 2*width,
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parameter [0:0] sim = 1'b0,
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parameter [0:0] with_c = 1'b0,
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parameter [0:0] with_csr = 1'b0,
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parameter [0:0] with_mdu = 1'b0,
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//Internally calculated. Do not touch
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parameter B = width-1,
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parameter regs = 32+with_csr*4,
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parameter rf_l2d = $clog2(regs*32/rf_width))
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(
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@ -78,13 +80,13 @@ module servile
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wire [$clog2(regs)-1:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [B:0] wdata0;
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wire [B:0] wdata1;
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wire [$clog2(regs)-1:0] rreg0;
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wire [$clog2(regs)-1:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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wire [B:0] rdata0;
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wire [B:0] rdata1;
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wire [31:0] mdu_rs1;
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wire [31:0] mdu_rs2;
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@ -149,6 +151,7 @@ module servile
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serv_rf_ram_if
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#(.width (rf_width),
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.W (width),
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.reset_strategy (reset_strategy),
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.csr_regs (with_csr*4))
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rf_ram_if
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@ -196,6 +199,7 @@ module servile
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serv_top
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#(
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.WITH_CSR (with_csr?1:0),
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.W (width),
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.PRE_REGISTER (1'b1),
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.RESET_STRATEGY (reset_strategy),
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.RESET_PC (reset_pc),
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@ -109,6 +109,7 @@ module serving
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servile
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#(.reset_pc (32'h0000_0000),
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.reset_strategy (RESET_STRATEGY),
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.rf_width (rf_width),
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.sim (sim),
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.with_csr (WITH_CSR))
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servile
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