Add zcu106 support to servant

data/zcu106.xdc

@@ -0,0 +1,8 @@
+## Clock signal
+set_property -dict { PACKAGE_PIN H9 IOSTANDARD LVDS } [get_ports i_clk_p];
+set_property -dict { PACKAGE_PIN G9 IOSTANDARD LVDS } [get_ports i_clk_n];
+create_clock -add -name sys_clk_pin -period 8 [get_nets i_clk];
+
+## LED
+set_property -dict { PACKAGE_PIN AL11 IOSTANDARD LVCMOS12 } [get_ports q];
+set_property -dict { PACKAGE_PIN AL17 IOSTANDARD LVCMOS12 } [get_ports o_uart_tx]

servant.core

@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : ::servant:1.0
+name : ::servant:1.0.1
 
 filesets:
   service:
@@ -56,6 +56,13 @@ filesets:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
       - servant/servix.v : {file_type : verilogSource}
       - data/arty_a7_35t.xdc : {file_type : xdc}
+
+  zcu106:
+    files:
+      - servant/servus_clock_gen.v : {file_type : verilogSource}
+      - servant/servus.v : {file_type : verilogSource}
+      - data/zcu106.xdc : {file_type : xdc}
+
 targets:
   default:
     filesets : [soc]
@@ -144,6 +151,15 @@ targets:
         verilator_options : [--trace]
     toplevel : servant_sim
 
+  zcu106:
+    default_tool: vivado
+    description : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit
+    filesets : [mem_files, soc, zcu106]
+    parameters : [memfile, memsize]
+    tools:
+      vivado: {part : xczu7ev-ffvc1156-2-e}
+    toplevel : servus
+
 parameters:
   PLL:
     datatype : str

servant/servus.v

@@ -0,0 +1,36 @@
+`default_nettype none
+module servus
+  (input wire  i_clk_p,
+   input wire  i_clk_n,
+   output wire o_uart_tx,
+   output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      i_clk;
+   wire      clk;
+   wire      rst;
+
+   assign o_uart_tx = q;
+
+   IBUFDS ibufds
+     (.I  (i_clk_p),
+      .IB (i_clk_n),
+      .O  (i_clk));
+
+   servus_clock_gen
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (clk),
+      .o_rst (rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (clk),
+      .wb_rst (rst),
+      .q      (q));
+
+endmodule

servant/servus_clock_gen.v

@@ -0,0 +1,44 @@
+`default_nettype none
+module servus_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   clkfb;
+   wire   locked;
+   reg 	  locked_r;
+
+   MMCME4_ADV
+     #(.DIVCLK_DIVIDE    (5),
+       .CLKFBOUT_MULT_F  (48.000),
+       .CLKOUT0_DIVIDE_F (75.0),
+       .CLKIN1_PERIOD    (8.0), //125MHz
+       .STARTUP_WAIT     ("FALSE"))
+   mmcm
+     (.CLKFBOUT    (clkfb),
+      .CLKFBOUTB   (),
+      .CLKOUT0     (o_clk),
+      .CLKOUT0B    (),
+      .CLKOUT1     (),
+      .CLKOUT1B    (),
+      .CLKOUT2     (),
+      .CLKOUT2B    (),
+      .CLKOUT3     (),
+      .CLKOUT3B    (),
+      .CLKOUT4     (),
+      .CLKOUT5     (),
+      .CLKOUT6     (),
+      .CLKIN1      (i_clk),
+      .CLKIN2      (1'b0),
+      .CLKINSEL    (1'b1),
+      .LOCKED      (locked),
+      .PWRDWN      (1'b0),
+      .RST         (1'b0),
+      .CLKFBIN     (clkfb));
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule