Silence LSE warnings

rtl/ser_shift.v

@@ -25,7 +25,7 @@ module ser_shift
       .o_par (shiftreg[31:1]));
 
    always @(posedge i_clk) begin
-      cnt <= cnt + 1;
+      cnt <= cnt + 5'd1;
       if (cnt == 31) begin
          signbit <= shiftreg[cnt];
          wrapped <= 1'b1;

rtl/serv_ctrl.v

@@ -23,6 +23,12 @@ module serv_ctrl
 
    parameter RESET_PC = 32'd8;
 
+   reg        en_r;
+   reg        en_2r;
+   reg 	      en_pc_r;
+   reg 	      en_pc_2r;
+   reg 	      en_pc_3r;
+
    wire       pc_plus_4;
    wire       pc_plus_offset;
 
@@ -81,12 +87,6 @@ module serv_ctrl
    wire       pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
 
 
-   reg        en_r;
-   reg        en_2r;
-   reg 	      en_pc_r;
-   reg 	      en_pc_2r;
-   reg 	      en_pc_3r;
-
    always @(posedge clk) begin
       en_r <= i_en;
       en_2r <= en_r;

rtl/serv_decode.v

@@ -77,6 +77,17 @@ module serv_decode
    reg [1:0]    state;
 
    reg [4:0] cnt;
+   reg 	cnt_done;
+
+   reg [4:0] opcode;
+   reg [30:7] op;
+   reg 	      signbit;
+
+   reg [8:0]  imm19_12_20;
+   reg 	      imm7;
+   reg [5:0]  imm30_25;
+   reg [4:0]  imm24_20;
+   reg [4:0]  imm11_7;
 
    assign o_cnt = cnt;
 
@@ -206,15 +217,6 @@ module serv_decode
 
    wire jal_misalign  = op[21] & opcode[1] & opcode[4];
 
-   reg [4:0] opcode;
-   reg [30:7] op;
-   reg 	      signbit;
-
-   reg [8:0]  imm19_12_20;
-   reg 	      imm7;
-   reg [5:0]  imm30_25;
-   reg [4:0]  imm24_20;
-   reg [4:0]  imm11_7;
 
    always @(posedge clk) begin
       casez(o_funct3)
@@ -283,8 +285,6 @@ module serv_decode
 
    wire cnt_en = (state != IDLE);
 
-   reg 	cnt_done;
-
    assign running = (state == RUN);
 
    assign o_ctrl_trap = (state == TRAP);

rtl/serv_regfile.v

@@ -26,17 +26,21 @@ module serv_regfile
 
    reg rd_r;
 
+   reg [1:0]  rdata;
    reg [4:0] rcnt;
    reg [4:0] wcnt;
    reg 	     rs1;
    reg 	     rs2;
    reg 	     rs1_r;
 
+   wire rs1_en = rcnt[0];
+   wire rs1_tmp = (rs1_en ? rdata[0] : rs1);
+
    wire [1:0] wdata = {i_rd, rd_r};
    always @(posedge i_clk) begin
       rd_r <= i_rd;
       if (i_rs_en)
-	wcnt <= wcnt + 1;
+	wcnt <= wcnt + 5'd1;
 
       if (i_go)
 	rcnt <= 5'd0;
@@ -53,7 +57,6 @@ module serv_regfile
       end
    end
 
-   wire rs1_tmp = (rs1_en ? rdata[0] : rs1);
 
    assign o_rs1 = (|i_rs1_addr) & rs1_r;
    assign o_rs2 = (|i_rs2_addr) & (rs1_en ? rs2 : rdata[0]);
@@ -62,10 +65,8 @@ module serv_regfile
    wire wr_en = wcnt[0] & i_rd_en;
 
    wire [8:0] raddr = {!rs1_en ? i_rs1_addr : i_rs2_addr, rcnt[4:1]};
-   wire rs1_en = rcnt[0];
 
    reg [1:0]  memory [0:511];
-   reg [1:0]  rdata;
 
    always @(posedge i_clk) begin
       if (wr_en)