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bufreg refactoring in preparation of qerv integration

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Olof Kindgren 2024-03-06 19:49:54 +01:00
parent b937ef61aa
commit 4537abb965
1 changed files with 34 additions and 20 deletions
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54
rtl/serv_bufreg.v
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@ -1,5 +1,7 @@
module serv_bufreg #(
parameter [0:0] MDU = 0
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
@ -15,37 +17,49 @@ module serv_bufreg #(
input wire i_clr_lsb,
input wire i_sh_signed,
//Data
input wire i_rs1,
input wire i_imm,
output wire o_q,
input wire [B:0] i_rs1,
input wire [B:0] i_imm,
output wire [B:0] o_q,
//External
output wire [31:0] o_dbus_adr,
//Extension
output wire [31:0] o_ext_rs1);
wire c, q;
reg c_r;
reg [31:2] data;
reg [1:0] lsb;
wire c;
wire [B:0] q;
reg [B:0] c_r;
reg [31:0] data;
wire [B:0] clr_lsb;
wire clr_lsb = i_cnt0 & i_clr_lsb;
assign clr_lsb[0] = i_cnt0 & i_clr_lsb;
assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r;
assign {c,q} = {1'b0,(i_rs1 & {W{i_rs1_en}})} + {1'b0,(i_imm & {W{i_imm_en}} & ~clr_lsb)} + c_r;
always @(posedge i_clk) begin
//Make sure carry is cleared before loading new data
c_r <= c & i_en;
if (i_en)
data <= {i_init ? q : (data[31] & i_sh_signed), data[31:3]};
if (i_init ? (i_cnt0 | i_cnt1) : i_en)
lsb <= {i_init ? q : data[2],lsb[1]};
c_r <= {W{1'b0}};
c_r[0] <= c & i_en;
end
assign o_q = lsb[0] & i_en;
assign o_dbus_adr = {data, 2'b00};
assign o_ext_rs1 = {o_dbus_adr[31:2],lsb};
reg [1:0] lsb;
generate
if (W == 1) begin : gen_w_eq_1
always @(posedge i_clk) begin
if (i_en)
data[31:2] <= {i_init ? q : {W{data[31] & i_sh_signed}}, data[31:3]};
if (i_init ? (i_cnt0 | i_cnt1) : i_en)
data[1:0] <= {i_init ? q : data[2], data[1]};
end
always @(*) lsb = data[1:0];
assign o_q = data[0] & {W{i_en}};
end
endgenerate
assign o_dbus_adr = {data[31:2], 2'b00};
assign o_ext_rs1 = data;
assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
endmodule