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added support for MAX10 10M08 Evaluation Kit
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4 changed files with 64 additions and 0 deletions
8
data/max10_10m08evk.sdc
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8
data/max10_10m08evk.sdc
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@ -0,0 +1,8 @@
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# Main system clock (50 Mhz)
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create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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24
data/max10_10m08evk.tcl
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24
data/max10_10m08evk.tcl
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#MAX10_CLK2_50 3.3V
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set_location_assignment PIN_27 -to i_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
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#LED[0]
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set_location_assignment PIN_132 -to q
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
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#P8 3 ARDUINO_IO1
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set_location_assignment PIN_75 -to uart_txd
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd
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#KEY[0]
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set_location_assignment PIN_121 -to i_rst_n
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n
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# Configuration mode that allows Memory Initialisation
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set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
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# Generate SVF File for openFPGALoader
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set_global_assignment -name GENERATE_SVF_FILE ON
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# set_global_assignment -name GENERATE_JBC_FILE ON
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set_global_assignment -name GENERATE_JAM_FILE ON
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@ -183,6 +183,13 @@ Pin B1 is used for UART output with 115200 baud rate. The serial port on Kolibri
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ldprog -Ks build/servant_1.2.1/machdyne_kolibri-icestorm/servant_1.2.1.bin
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MAX10 10M08 Evaluation Kit
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^^^^^^^^^^^^^^^^^^^^
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FPGA Pin 75 (Arduino_IO01 J5 pin 7) is used for UART output with 57600 baud rate. SW1 is reset and Led 1 q output.
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fusesoc run --target=max10_10m08evk servant
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Nandland Go Board
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^^^^^^^^^^^^^^^^^
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25
servant.core
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servant.core
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@ -172,6 +172,13 @@ filesets:
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- servant/servant_md_kolibri.v : {file_type : verilogSource}
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- data/machdyne_kolibri.pcf : {file_type : PCF}
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max10_10m08evk:
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files:
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- data/max10_10m08evk.sdc : {file_type : SDC}
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- data/max10_10m08evk.tcl : {file_type : tclSource}
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- servant/servive_clock_gen.v : {file_type : verilogSource}
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- servant/servive.v : {file_type : verilogSource}
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nexys_2:
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files:
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- servant/servax_clock_gen.v : {file_type : verilogSource}
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@ -472,6 +479,19 @@ targets:
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pnr: next
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toplevel : servant_md_kolibri
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max10_10m08evk:
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default_tool : quartus
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description: MAX10 10M08 evaluation kit
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hooks:
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post_run: [jbc]
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filesets : [mem_files, soc, max10_10m08evk]
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parameters : [memfile, memsize]
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tools:
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quartus:
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family : MAX 10
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device : 10M08SAE144C8G
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toplevel: servive
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nexys_2_500:
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default_tool: ise
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filesets : [mem_files, soc, nexys_2]
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@ -719,3 +739,8 @@ parameters:
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generate:
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ice40pll:
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generator: icepll
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scripts:
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jbc:
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cmd : [quartus_jbcc, "-n", servant_1_2_1_pof.jam, servant_1_2_1_pof.jbc]
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