Nexys 2 Board support

Added nexys 2 target support for servant

data/nexys_2.tcl

@@ -0,0 +1 @@
+project set "Other XST Command Line Options" "-use_new_parser yes"

data/nexys_2.ucf

@@ -0,0 +1,8 @@
+NET "i_clk" LOC = "B8" | IOSTANDARD = LVCMOS33 ;   
+NET "i_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+# Pin assignment for Uart tx
+NET "q" LOC = "L15"  | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8 ; 
+
+# Pin assignment for LED
+# NET "q" LOC = "J14"  | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8 ; 

servant.core

@@ -110,6 +110,13 @@ filesets:
       - servant/servant_lx9.v : {file_type : verilogSource}
       - data/lx9_microboard.ucf : {file_type : UCF}
 
+  nexys_2:
+    files:
+      - servant/servax_clock_gen.v : {file_type : verilogSource}
+      - servant/servax.v : {file_type : verilogSource}
+      - data/nexys_2.tcl : {file_type : tclSource}
+      - data/nexys_2.ucf : {file_type : UCF}
+  
   nexys_a7:
     files:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
@@ -309,6 +316,30 @@ targets:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : servix
 
+  nexys_2_500:
+    default_tool: ise
+    filesets : [mem_files, soc, nexys_2]
+    parameters : [memfile, memsize]
+    tools:
+      ise:
+        family  : Spartan3E
+        device  : xc3s500e
+        package : fg320
+        speed   : -4
+    toplevel : servax
+
+  nexys_2_1200:
+    default_tool: ise
+    filesets : [mem_files, soc, nexys_2]
+    parameters : [memfile, memsize]
+    tools:
+      ise:
+        family  : Spartan3E
+        device  : xc3s1600e
+        package : fg320
+        speed   : -4
+    toplevel : servax
+
   cmod_a7_35t:
     default_tool: vivado
     filesets : [mem_files, soc, cmod_a7_35t]

servant/servax.v

@@ -0,0 +1,28 @@
+`default_nettype none
+module servax   // top level for nexys 2 (Xilinx's Spartan-3E based) target board
+(
+ input wire  i_clk,
+ output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+   parameter PLL = "NONE";
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   servax_clock_gen
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servax_clock_gen.v

@@ -0,0 +1,31 @@
+`default_nettype none
+module servax_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   locked;
+   reg 	  locked_r;    
+
+
+    DCM_SP #(
+      .CLKFX_DIVIDE(25),   // Can be any integer from 1 to 32
+      .CLKFX_MULTIPLY(8), // Can be any integer from 2 to 32
+      .CLKIN_PERIOD(20.0)  //50Mhz
+    ) 
+    DCM_SP_inst (
+      .CLKFX(o_clk),   // DCM CLK synthesis out (M/D)
+      .CLKFX180(), // 180 degree CLK synthesis out
+      .LOCKED(locked), // DCM LOCK status output
+      .STATUS(), // 8-bit DCM status bits output
+      .CLKFB(),   // DCM clock feedback
+      .CLKIN(i_clk),   // Clock input
+      .RST(1'b0)        // DCM asynchronous reset input
+   );
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule