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Avoid exposing funct3 from decode
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Olof Kindgren
parent
9575eb4fef
commit
5a44634ee5
3 changed files with 44 additions and 37 deletions
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@ -39,7 +39,9 @@ module serv_decode
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output reg [4:0] o_rf_rs1_addr,
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output reg [4:0] o_rf_rs2_addr,
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//To mem IF
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output reg [2:0] o_funct3,
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output wire o_mem_signed,
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output wire o_mem_word,
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output wire o_mem_half,
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output wire o_mem_cmd,
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//To CSR
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output wire o_csr_en,
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@ -59,6 +61,7 @@ module serv_decode
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`include "serv_params.vh"
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reg [4:0] opcode;
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reg [2:0] funct3;
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reg [31:0] imm;
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reg op20;
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reg op21;
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@ -70,13 +73,13 @@ module serv_decode
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wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
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assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
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assign o_shift_op = op_or_opimm & (o_funct3[1:0] == 2'b01);
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assign o_slt_op = op_or_opimm & (o_funct3[2:1] == 2'b01);
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assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01);
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assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01);
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assign o_branch_op = opcode[4] & !opcode[2];
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//Matches system opcodes except CSR accesses (o_funct3 == 0)
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//Matches system opcodes except CSR accesses (funct3 == 0)
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//No idea anymore why the !op21 condition is needed here
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assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|o_funct3);
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assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3);
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assign o_ebreak = op20;
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@ -92,11 +95,11 @@ module serv_decode
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//Take branch for jump or branch instructions (opcode == 1x0xx) if
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//a) It's an unconditional branch (opcode[0] == 1)
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//b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (o_funct3[0] == 0) and ALU compare is true
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//c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (o_funct3[0] == 1) and ALU compare is false
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//b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true
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//c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false
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//Only valid during the last cycle of INIT, when the branch condition has
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//been calculated.
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wire o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^o_funct3[0]));
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wire o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0]));
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assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
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assign o_ctrl_jalr = opcode[4] & (opcode[1:0] == 2'b01);
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@ -132,7 +135,7 @@ module serv_decode
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wire csr_valid = op20 | (op26 & !op22 & !op21);
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//Matches system ops except eceall/ebreak
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wire csr_op = opcode[4] & opcode[2] & (|o_funct3);
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wire csr_op = opcode[4] & opcode[2] & (|funct3);
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assign o_rd_csr_en = csr_op;
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assign o_csr_en = csr_op & csr_valid;
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@ -140,18 +143,21 @@ module serv_decode
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assign o_csr_mie_en = csr_op & !op26 & op22 & !op20;
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assign o_csr_mcause_en = csr_op & op21 & !op20;
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assign o_csr_source = o_funct3[1:0];
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assign o_csr_d_sel = o_funct3[2];
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assign o_csr_source = funct3[1:0];
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assign o_csr_d_sel = funct3[2];
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assign o_alu_cmp_eq = o_funct3[2:1] == 2'b00;
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assign o_alu_cmp_eq = funct3[2:1] == 2'b00;
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assign o_alu_cmp_uns = (o_funct3[0] & o_funct3[1]) | (o_funct3[1] & o_funct3[2]);
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assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]);
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assign o_alu_sh_signed = imm30;
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assign o_alu_sh_right = o_funct3[2];
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assign o_alu_sh_right = funct3[2];
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assign o_mem_cmd = opcode[3];
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assign o_mem_signed = ~funct3[2];
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assign o_mem_word = funct3[1];
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assign o_mem_half = funct3[0];
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assign o_alu_bool_op = o_funct3[1:0];
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assign o_alu_bool_op = funct3[1:0];
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wire sign_bit = i_wb_rdt[31];
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@ -167,20 +173,20 @@ module serv_decode
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wire sorbtype = op_code[3:0] == 4'b1000;
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always @(posedge clk) begin
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casez(o_funct3)
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casez(funct3)
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3'b000 : o_alu_rd_sel <= ALU_RESULT_ADD;
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3'b001 : o_alu_rd_sel <= ALU_RESULT_SR;
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3'b01? : o_alu_rd_sel <= ALU_RESULT_LT;
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3'b100 : o_alu_rd_sel <= ALU_RESULT_BOOL;
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3'b101 : o_alu_rd_sel <= ALU_RESULT_SR;
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3'b11? : o_alu_rd_sel <= ALU_RESULT_BOOL;
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endcase // casez (o_funct3)
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endcase // casez (funct3)
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if (i_wb_en) begin
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o_rf_rd_addr <= i_wb_rdt[11:7];
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o_rf_rs1_addr <= i_wb_rdt[19:15];
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o_rf_rs2_addr <= i_wb_rdt[24:20];
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o_funct3 <= i_wb_rdt[14:12];
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funct3 <= i_wb_rdt[14:12];
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imm30 <= i_wb_rdt[30];
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opcode <= i_wb_rdt[6:2];
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op20 <= i_wb_rdt[20];
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@ -5,10 +5,11 @@ module serv_mem_if
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input wire i_rst,
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input wire i_en,
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input wire i_init,
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input wire i_cnt_done,
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input wire i_cmd,
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input wire i_signed,
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input wire i_word,
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input wire i_half,
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input wire [1:0] i_bytecnt,
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input wire [2:0] i_funct3,
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input wire i_rs2,
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output wire o_rd,
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input wire [1:0] i_lsb,
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@ -40,24 +41,19 @@ module serv_mem_if
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(dat_sel == 2) ? dat2[0] :
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(dat_sel == 1) ? dat1[0] : dat0[0];
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wire is_signed = ~i_funct3[2];
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wire is_word = i_funct3[1];
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wire is_half = i_funct3[0];
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wire is_byte = !(|i_funct3[1:0]);
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wire dat_valid = is_word | (i_bytecnt == 2'b00) | (is_half & !i_bytecnt[1]);
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assign o_rd = dat_valid ? dat_cur : signbit & is_signed;
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wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
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assign o_rd = dat_valid ? dat_cur : signbit & i_signed;
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wire upper_half = bytepos[1];
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/*
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assign o_wb_sel = (is_word ? 4'b1111 :
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is_half ? {{2{upper_half}}, ~{2{upper_half}}} :
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assign o_wb_sel = (i_word ? 4'b1111 :
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i_half ? {{2{upper_half}}, ~{2{upper_half}}} :
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4'd1 << bytepos);
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*/
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assign o_wb_sel[3] = is_word | (is_half & bytepos[1]) | (bytepos == 2'b11);
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assign o_wb_sel[2] = (bytepos == 2'b10) | is_word;
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assign o_wb_sel[1] = ((is_word | is_half) & !bytepos[1]) | (bytepos == 2'b01);
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assign o_wb_sel[3] = i_word | (i_half & bytepos[1]) | (bytepos == 2'b11);
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assign o_wb_sel[2] = (bytepos == 2'b10) | i_word;
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assign o_wb_sel[1] = ((i_word | i_half) & !bytepos[1]) | (bytepos == 2'b01);
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assign o_wb_sel[0] = (bytepos == 2'b00);
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assign o_wb_we = i_cmd;
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@ -91,7 +87,7 @@ module serv_mem_if
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if (wb_en)
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{dat3,dat2,dat1,dat0} <= i_wb_rdt;
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o_misalign <= (bytepos[0] & !is_byte) | (bytepos[1] & is_word);
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o_misalign <= (bytepos[0] & (i_word | i_half)) | (bytepos[1] & i_word);
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if (dat_valid)
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signbit <= dat_cur;
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@ -80,7 +80,6 @@ module serv_top
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wire [3:0] cnt_r;
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wire cnt_done;
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wire [2:0] funct3;
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wire bufreg_hold;
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wire bufreg_rs1_en;
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@ -110,6 +109,9 @@ module serv_top
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wire mem_cmd;
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wire mem_signed;
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wire mem_word;
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wire mem_half;
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wire [1:0] mem_bytecnt;
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wire mem_misalign;
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@ -208,8 +210,10 @@ module serv_top
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.o_rf_rs1_addr (rs1_addr),
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.o_rf_rs2_addr (rs2_addr),
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//To mem IF
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.o_funct3 (funct3),
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.o_mem_cmd (mem_cmd),
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.o_mem_signed (mem_signed),
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.o_mem_word (mem_word),
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.o_mem_half (mem_half),
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//To CSR
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.o_csr_en (csr_en),
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.o_csr_addr (csr_addr),
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@ -356,10 +360,11 @@ module serv_top
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.i_rst (i_rst),
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.i_en (cnt_en),
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.i_init (init),
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.i_cnt_done (cnt_done),
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.i_cmd (mem_cmd),
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.i_signed (mem_signed),
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.i_word (mem_word),
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.i_half (mem_half),
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.i_bytecnt (mem_bytecnt),
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.i_funct3 (funct3),
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.i_rs2 (rs2),
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.o_rd (mem_rd),
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.i_lsb (lsb),
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