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Add modified core dependencies

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Olof Kindgren 2018-11-18 22:31:53 +01:00
parent 530eaafdb9
commit 5db1864ba9
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1254
cores/techlibs/cells_sim.v Normal file
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cores/techlibs/ice40-0.7.core Normal file
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CAPI=2:
name : yosys:techlibs:ice40fork:0.7
filesets:
ice40_cells:
files:
- cells_sim.v : {file_type : verilogSource}
targets:
default:
filesets : [ice40_cells]

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cores/wb_ram_1.1/README.md Normal file
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wb_ram
======
wb_ram is a generic memory that is intended to map against on-chip RAM or registers. It is currently hard coded to use 32 bits and has a Wishbone B3 interface for burst accesses
Parameters
----------
Name | Description | Default value |
----- | -------------------- | ------------------------- |
dw | Wishbone data width | 32 (only supported value) |
depth | Memory size in bytes | 256 |
aw | Address width | clog2(depth) |
Test bench
----------
wb_ram comes with a self-checking test bench that uses the `wb_bfm_transactor` from [wb_bfm](https://github.com/olofk/wb_bfm).
TODO
----
- Make width configurable
- Add technology-specific backends
- Only allow wrap bursts less than memory size

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cores/wb_ram_1.1/bench/wb_ram_tb.v Normal file
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/*
* Copyright (c) 2014, 2016 Olof Kindgren <olof.kindgren@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_ram_tb;
localparam MEMORY_SIZE = 1024;
vlog_tb_utils vlog_tb_utils0();
vlog_tap_generator #("wb_ram.tap", 1) vtg();
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
always #5 wb_clk <= ~wb_clk;
initial #100 wb_rst <= 1'b0;
wire done;
wire [31:0] wb_adr;
wire [31:0] wb_dat;
wire [3:0] wb_sel;
wire wb_we;
wire wb_cyc;
wire wb_stb;
wire [2:0] wb_cti;
wire [1:0] wb_bte;
wire [31:0] wb_rdt;
wire wb_ack;
wb_bfm_transactor
#(.MEM_HIGH (MEMORY_SIZE-1),
.AUTORUN (0),
.VERBOSE (0))
master
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_o (wb_adr),
.wb_dat_o (wb_dat),
.wb_sel_o (wb_sel),
.wb_we_o (wb_we ),
.wb_cyc_o (wb_cyc),
.wb_stb_o (wb_stb),
.wb_cti_o (wb_cti),
.wb_bte_o (wb_bte),
.wb_dat_i (wb_rdt),
.wb_ack_i (wb_ack),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done (done));
wb_ram
#(.depth (MEMORY_SIZE))
dut
(// Wishbone interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_adr[$clog2(MEMORY_SIZE)-1:0]),
.wb_stb_i (wb_stb),
.wb_cyc_i (wb_cyc),
.wb_cti_i (wb_cti),
.wb_bte_i (wb_bte),
.wb_we_i (wb_we) ,
.wb_sel_i (wb_sel),
.wb_dat_i (wb_dat),
.wb_dat_o (wb_rdt),
.wb_ack_o (wb_ack),
.wb_err_o ());
integer TRANSACTIONS;
integer SUBTRANSACTIONS;
integer SEED;
initial begin
//Grab CLI parameters
if($value$plusargs("transactions=%d", TRANSACTIONS))
master.set_transactions(TRANSACTIONS);
if($value$plusargs("subtransactions=%d", SUBTRANSACTIONS))
master.set_subtransactions(SUBTRANSACTIONS);
if($value$plusargs("seed=%d", SEED))
master.SEED = SEED;
master.display_settings;
master.run;
master.display_stats;
end
always @(posedge done) begin
vtg.ok("All tests complete");
$display("All tests complete");
$finish;
end
endmodule

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cores/wb_ram_1.1/rtl/verilog/wb_ram.v Normal file
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/*
* Copyright (c) 2014, 2016 Olof Kindgren <olof.kindgren@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o = 1'b0,
output wb_err_o,
output [dw-1:0] wb_dat_o);
wire [31:0] wb_rdt;
reg [31:0] wb_rdt_r;
always@(posedge wb_clk_i) begin
//Ack generation
wb_ack_o <= wb_cyc_i & wb_stb_i & !wb_ack_o;
if (wb_cyc_i & wb_stb_i)
wb_rdt_r <= wb_rdt;
if (wb_rst_i)
wb_ack_o <= 1'b0;
end
assign wb_dat_o = (wb_cyc_i & wb_stb_i) ? wb_rdt : wb_rdt_r;
wire ram_we = wb_we_i & wb_cyc_i & wb_stb_i & wb_ack_o;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr(wb_adr_i[aw-1:2]),
.raddr (wb_adr_i[aw-1:2]),
.dout (wb_rdt));
endmodule

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cores/wb_ram_1.1/rtl/verilog/wb_ram_generic.v Normal file
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/*
* Copyright (c) 2016 Olof Kindgren <olof.kindgren@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_ram_generic
#(parameter depth=256,
parameter memfile = "")
(input clk,
input [3:0] we,
input [31:0] din,
input [$clog2(depth)-1:0] waddr,
input [$clog2(depth)-1:0] raddr,
output reg [31:0] dout);
reg [31:0] mem [0:depth-1] /* verilator public */;
always @(posedge clk) begin
if (we[0]) mem[waddr][7:0] <= din[7:0];
if (we[1]) mem[waddr][15:8] <= din[15:8];
if (we[2]) mem[waddr][23:16] <= din[23:16];
if (we[3]) mem[waddr][31:24] <= din[31:24];
dout <= mem[raddr];
end
generate
initial
if(|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
endgenerate
endmodule

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cores/wb_ram_1.1/wb_ram.core Normal file
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CAPI=1
[main]
name = ::wb_ram:1.1
description = Wishbone RAM with selectable backends
simulators = icarus modelsim
depend = wb_common
[fileset rtl]
files =
rtl/verilog/wb_ram.v
rtl/verilog/wb_ram_generic.v
file_type = verilogSource
[fileset tb]
files = bench/wb_ram_tb.v
file_type = verilogSource
scope = private
usage = sim
[simulator]
toplevel = wb_ram_tb
[icarus]
depend = >=vlog_tb_utils-1.0 >=wb_bfm-1.0
[modelsim]
depend = >=vlog_tb_utils-1.0 >=wb_bfm-1.0
[parameter transactions]
datatype = int
description = Number of wishbone transactions to run in test bench
paramtype = plusarg
scope = private