Add UART decoder

bench/serv_soc_tb.cpp

@@ -25,21 +25,33 @@ void INThandler(int signal)
 
 int main(int argc, char **argv, char **env)
 {
+  vluint64_t sample_time = 0;
 	uint32_t insn = 0;
 	uint32_t ex_pc = 0;
-
+	int baud_rate = 0;
+	int baud_t    = 0;
 	int uart_state = 0;
 	char uart_ch = 0;
 	Verilated::commandArgs(argc, argv);
 
 	Vserv_wrapper* top = new Vserv_wrapper;
 
+	const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
+	if (arg[0]) {
+	  baud_rate = atoi(arg+15);
+	  if (baud_rate) {
+	    baud_t = 1000*1000*1000/baud_rate;
+	  }
+	}
+
+	VerilatedVcdC * tfp = 0;
 	const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
-	//if (vcd[0]) == '\0' || atoi(arg + 11) != 0)
-	Verilated::traceEverOn(true);
-        VerilatedVcdC* tfp = new VerilatedVcdC;
-        top->trace (tfp, 99);
-        tfp->open ("trace.vcd");
+	if (vcd[0]) {
+	  Verilated::traceEverOn(true);
+	  tfp = new VerilatedVcdC;
+	  top->trace (tfp, 99);
+	  tfp->open ("trace.vcd");
+	}
 
 	signal(SIGINT, INThandler);
 
@@ -47,14 +59,47 @@ int main(int argc, char **argv, char **env)
 	bool q = top->q;
 	while (!(done || Verilated::gotFinish())) {
 	  top->eval();
-	  tfp->dump(main_time);
-	  /*if (q != top->q) {
-	    q = top->q;
-	    printf("%lu output is %s\n", main_time, q ? "ON" : "OFF");
+	  if (tfp)
+	    tfp->dump(main_time);
+	  if (baud_rate) {
+	    if (uart_state == 0) {
+	      if (!top->q) {
+		sample_time = main_time + baud_t/2;
+		uart_state++;
+	      }
+	    }
+	    else if(uart_state == 1) {
+	      if (main_time > sample_time) {
+		sample_time += baud_t;
+		uart_ch = 0;
+		uart_state++;
+	      }
+	    }
+	    else if (uart_state < 10) {
+	      if (main_time > sample_time) {
+		sample_time += baud_t;
+		uart_ch |= top->q << (uart_state-2);
+		uart_state++;
+	      }
+	    }
+	    else {
+	      if (main_time > sample_time) {
+		sample_time += baud_t;
+		putchar(uart_ch);
+		uart_state=0;
+	      }
+	    }
+	  }
+	  /*else {
+	    if (q != top->q) {
+	      q = top->q;
+	      printf("%lu output q is %s\n", main_time, q ? "ON" : "OFF");
+	    }
 	    }*/
 	  top->wb_clk = !top->wb_clk;
 	  main_time+=31.25;
 	}
-	tfp->close();
+	if (tfp)
+	  tfp->close();
 	exit(0);
 }

bench/serv_wrapper.v

@@ -93,7 +93,7 @@ module serv_wrapper
       .i_wb_dat (wb_m2s_gpio_dat[0]),
       .i_wb_cyc (wb_m2s_gpio_cyc),
       .o_wb_ack (wb_s2m_gpio_ack),
-      .o_gpio   (/*q*/));
+      .o_gpio   (q));
 
    reg canary;
 
@@ -106,7 +106,7 @@ module serv_wrapper
      else if (wb_m2s_cpu_dbus_cyc & wb_s2m_cpu_dbus_ack)
        canary <= ~canary;
 
-   assign q = canary;
+//   assign q = canary;
 
    assign wb_s2m_gpio_dat = 32'h0;
 

rtl/wb_gpio.v

@@ -5,7 +5,7 @@ module wb_gpio
    input wire i_wb_dat,
    input wire i_wb_cyc,
    output reg o_wb_ack,
-   output reg o_gpio = 1'b0);
+   output reg o_gpio = 1'b1);
    
    always @(posedge i_wb_clk) begin
       o_wb_ack <= 1'b0;

serv.core

@@ -104,7 +104,7 @@ targets:
     default_tool: verilator
     filesets : [core, wrapper, verilator_tb]
     generate : [wb_intercon]
-    parameters : [RISCV_FORMAL=true, firmware, signature]
+    parameters : [RISCV_FORMAL=true, firmware, signature, uart_baudrate, vcd]
     tools:
       verilator:
         verilator_options : [-Wno-fatal, --trace]
@@ -122,6 +122,14 @@ parameters:
   signature:
     datatype : file
     paramtype : plusarg
+  uart_baudrate:
+    datatype : int
+    description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
+    paramtype : plusarg
+
+  vcd:
+    datatype : bool
+    paramtype : plusarg
 
 generate:
   wb_intercon: