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Simplify control logic for bool ops

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Olof Kindgren 2021-03-14 00:12:29 +01:00
parent 7624466ddd
commit 727bb40a87
2 changed files with 2 additions and 2 deletions
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2
rtl/serv_alu.v
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@ -39,7 +39,7 @@ module serv_alu
assign o_cmp = i_cmp_eq ? result_eq : result_lt;
localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
localparam [15:0] BOOL_LUT = 16'h8E06;//And, Or, 0, xor
wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}];
assign o_rd = (i_rd_sel[0] & result_add) |

2
rtl/serv_decode.v
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@ -207,7 +207,7 @@ module serv_decode
assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift
assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT*
assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool
assign o_alu_rd_sel[3] = funct3[2]; //Bool
always @(posedge clk) begin
if (i_wb_en) begin
funct3 <= i_wb_rdt[14:12];