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Properly reset stage_two_req signal

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Olof Kindgren 2021-08-26 10:47:03 +02:00
parent b10a871499
commit 781c07b7dc
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rtl/serv_state.v
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@ -186,6 +186,7 @@ endgenerate
init_done <= 1'b0;
o_ctrl_jump <= 1'b0;
o_cnt_r <= 4'b0000;
stage_two_req <= 1'b0;
end
end
end