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Create toplevel without RF
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Olof Kindgren
parent
4532c8dafd
commit
8b82c85fb6
4 changed files with 164 additions and 46 deletions
133
rtl/serv_rf_top.v
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133
rtl/serv_rf_top.v
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@ -0,0 +1,133 @@
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`default_nettype none
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module serv_rf_top
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(
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input wire clk,
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input wire i_rst,
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input wire i_timer_irq,
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`ifdef RISCV_FORMAL
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output wire rvfi_valid,
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output wire [63:0] rvfi_order,
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output wire [31:0] rvfi_insn,
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output wire rvfi_trap,
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output wire rvfi_halt,
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output wire rvfi_intr,
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output wire [1:0] rvfi_mode,
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output wire [1:0] rvfi_ixl,
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output wire [4:0] rvfi_rs1_addr,
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output wire [4:0] rvfi_rs2_addr,
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output wire [31:0] rvfi_rs1_rdata,
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output wire [31:0] rvfi_rs2_rdata,
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output wire [4:0] rvfi_rd_addr,
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output wire [31:0] rvfi_rd_wdata,
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output wire [31:0] rvfi_pc_rdata,
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output wire [31:0] rvfi_pc_wdata,
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output wire [31:0] rvfi_mem_addr,
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output wire [3:0] rvfi_mem_rmask,
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output wire [3:0] rvfi_mem_wmask,
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output wire [31:0] rvfi_mem_rdata,
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output wire [31:0] rvfi_mem_wdata,
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`endif
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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output wire [31:0] o_dbus_adr,
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output wire [31:0] o_dbus_dat,
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output wire [3:0] o_dbus_sel,
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output wire o_dbus_we ,
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output wire o_dbus_cyc,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack);
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parameter RESET_PC = 32'd0;
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wire rf_wreq;
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wire rf_rreq;
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wire [5:0] wreg0;
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wire [5:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [5:0] rreg0;
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wire [5:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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serv_rf_2bit rf
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(.i_clk (clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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.i_rreq (rf_rreq),
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.o_rgnt (rf_ready),
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.i_wreg0 (wreg0),
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.i_wreg1 (wreg1),
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.i_wen0 (wen0),
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.i_wen1 (wen1),
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.i_wdata0 (wdata0),
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.i_wdata1 (wdata1),
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1));
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serv_top
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#(.RESET_PC (RESET_PC))
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cpu
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_timer_irq (i_timer_irq),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_mode (rvfi_mode ),
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.rvfi_ixl (rvfi_ixl ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata),
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.rvfi_rs2_rdata (rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask),
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.rvfi_mem_wmask (rvfi_mem_wmask),
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.rvfi_mem_rdata (rvfi_mem_rdata),
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.rvfi_mem_wdata (rvfi_mem_wdata),
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`endif
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.o_wreg0 (wreg0),
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.o_wreg1 (wreg1),
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.o_wen0 (wen0),
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.o_wen1 (wen1),
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.o_wdata0 (wdata0),
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.o_wdata1 (wdata1),
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.o_rreg0 (rreg0),
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.o_rreg1 (rreg1),
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.i_rdata0 (rdata0),
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.i_rdata1 (rdata1),
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.o_ibus_adr (o_ibus_adr),
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_rdt (i_ibus_rdt),
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.i_ibus_ack (i_ibus_ack),
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.o_dbus_adr (o_dbus_adr),
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.o_dbus_dat (o_dbus_dat),
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.o_dbus_sel (o_dbus_sel),
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.o_dbus_we (o_dbus_we),
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.o_dbus_cyc (o_dbus_cyc),
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.i_dbus_rdt (i_dbus_rdt),
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.i_dbus_ack (i_dbus_ack));
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endmodule
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@ -28,6 +28,21 @@ module serv_top
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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`endif
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//RF Interface
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output wire o_rf_rreq,
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output wire o_rf_wreq,
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input wire i_rf_ready,
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output wire [5:0] o_wreg0,
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output wire [5:0] o_wreg1,
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output wire o_wen0,
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output wire o_wen1,
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output wire o_wdata0,
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output wire o_wdata1,
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output wire [5:0] o_rreg0,
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output wire [5:0] o_rreg1,
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input wire i_rdata0,
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input wire i_rdata1,
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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@ -95,9 +110,6 @@ module serv_top
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wire alu_sh_done;
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wire [1:0] alu_rd_sel;
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wire rf_rreq;
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wire rf_wreq;
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wire rf_ready;
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wire rs1;
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wire rs2;
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wire rd_en;
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@ -124,18 +136,7 @@ module serv_top
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wire [1:0] csr_addr;
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wire csr_pc;
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wire [5:0] wreg0;
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wire [5:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [5:0] rreg0;
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wire [5:0] rreg1;
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wire rdata0;
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wire rdata1;
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parameter RESET_PC = 32'd8;
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parameter RESET_PC = 32'd0;
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wire new_irq;
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wire trap_taken;
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@ -153,9 +154,9 @@ module serv_top
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.o_pending_irq (pending_irq),
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.i_dbus_ack (i_dbus_ack),
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.i_ibus_ack (i_ibus_ack),
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.o_rf_rreq (o_rf_rreq),
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.o_rf_wreq (o_rf_wreq),
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.i_rf_ready (i_rf_ready),
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.i_take_branch (take_branch),
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.i_branch_op (branch_op),
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.i_mem_op (mem_op),
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@ -322,16 +323,16 @@ module serv_top
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.i_clk (clk),
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.i_rst (i_rst),
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//RF interface
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.o_wreg0 (wreg0),
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.o_wreg1 (wreg1),
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.o_wen0 (wen0),
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.o_wen1 (wen1),
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.o_wdata0 (wdata0),
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.o_wdata1 (wdata1),
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.o_rreg0 (rreg0),
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.o_rreg1 (rreg1),
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.i_rdata0 (rdata0),
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.i_rdata1 (rdata1),
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.o_wreg0 (o_wreg0),
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.o_wreg1 (o_wreg1),
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.o_wen0 (o_wen0),
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.o_wen1 (o_wen1),
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.o_wdata0 (o_wdata0),
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.o_wdata1 (o_wdata1),
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.o_rreg0 (o_rreg0),
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.o_rreg1 (o_rreg1),
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.i_rdata0 (i_rdata0),
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.i_rdata1 (i_rdata1),
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.i_run (run),
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//Trap interface
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@ -366,23 +367,6 @@ module serv_top
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//CSR read port
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.o_csr (rf_csr_out));
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serv_rf_2bit rf
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(.i_clk (clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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.i_rreq (rf_rreq),
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.o_rgnt (rf_ready),
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.i_wreg0 (wreg0),
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.i_wreg1 (wreg1),
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.i_wen0 (wen0),
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.i_wen1 (wen1),
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.i_wdata0 (wdata0),
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.i_wdata1 (wdata1),
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1));
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serv_mem_if mem_if
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(
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.i_clk (clk),
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@ -20,6 +20,7 @@ filesets:
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- rtl/serv_rf_2bit.v
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- rtl/serv_state.v
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- rtl/serv_top.v
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- rtl/serv_rf_top.v
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file_type : verilogSource
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targets:
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@ -154,7 +154,7 @@ servant_arbiter servant_arbiter
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.o_wb_rdt (wb_gpio_rdt),
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.o_gpio (q));
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serv_top
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serv_rf_top
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#(.RESET_PC (32'h0000_0000))
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cpu
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(
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