github-mirrors/serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2025-04-19 11:34:42 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Use Servile as a base for servant

Browse source
This commit is contained in:
Olof Kindgren 2024-01-29 22:28:05 +01:00
parent 8d91e2d288
commit 970c6fddca
6 changed files with 98 additions and 240 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
bench/servant_sim.v
View file

@ -28,7 +28,7 @@ module servant_sim
.align (align[0:0]))
dut(wb_clk, wb_rst, q);
assign pc_adr = dut.wb_ibus_adr;
assign pc_vld = dut.wb_ibus_ack;
assign pc_adr = dut.wb_mem_adr;
assign pc_vld = dut.wb_mem_ack;
endmodule

BIN
doc/servant.png
View file

Binary file not shown.
Side by side Swipe Overlay

Before

Width:  |  Height:  |  Size: 42 KiB

After

Width:  |  Height:  |  Size: 8.7 KiB

3
servant.core
View file

@ -30,13 +30,12 @@ filesets:
files:
- servant/servant_timer.v
- servant/servant_gpio.v
- servant/servant_arbiter.v
- servant/servant_mux.v
- "tool_quartus? (servant/servant_ram_quartus.sv)" : {file_type : systemVerilogSource}
- "!tool_quartus? (servant/servant_ram.v)"
- servant/servant.v
file_type : verilogSource
depend : [serv, "mdu? (mdu)"]
depend : [servile, "mdu? (mdu)"]
verilator_tb:
files:

248
servant/servant.v
View file

@ -13,103 +13,75 @@ module servant
parameter [0:0] compress = 0;
parameter [0:0] align = compress;
`ifdef MDU
localparam [0:0] with_mdu = 1'b1;
`else
localparam [0:0] with_mdu = 1'b0;
`endif
localparam aw = $clog2(memsize);
localparam csr_regs = with_csr*4;
localparam rf_width = 2;
localparam rf_l2d = $clog2((32+csr_regs)*32/rf_width);
wire timer_irq;
wire [31:0] wb_ibus_adr;
wire wb_ibus_cyc;
wire [31:0] wb_ibus_rdt;
wire wb_ibus_ack;
wire [31:0] wb_dbus_adr;
wire [31:0] wb_dbus_dat;
wire [3:0] wb_dbus_sel;
wire wb_dbus_we;
wire wb_dbus_cyc;
wire [31:0] wb_dbus_rdt;
wire wb_dbus_ack;
wire [31:0] wb_dmem_adr;
wire [31:0] wb_dmem_dat;
wire [3:0] wb_dmem_sel;
wire wb_dmem_we;
wire wb_dmem_cyc;
wire [31:0] wb_dmem_rdt;
wire wb_dmem_ack;
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
wire wb_mem_we;
wire wb_mem_cyc;
wire wb_mem_stb;
wire [31:0] wb_mem_rdt;
wire wb_mem_ack;
wire wb_gpio_dat;
wire wb_gpio_we;
wire wb_gpio_cyc;
wire wb_gpio_stb;
wire wb_gpio_rdt;
wire [31:0] wb_timer_dat;
wire wb_timer_we;
wire wb_timer_cyc;
wire wb_timer_stb;
wire [31:0] wb_timer_rdt;
wire [31:0] mdu_rs1;
wire [31:0] mdu_rs2;
wire [ 2:0] mdu_op;
wire mdu_valid;
wire [31:0] mdu_rd;
wire mdu_ready;
wire [31:0] wb_ext_adr;
wire [31:0] wb_ext_dat;
wire [3:0] wb_ext_sel;
wire wb_ext_we;
wire wb_ext_stb;
wire [31:0] wb_ext_rdt;
wire wb_ext_ack;
servant_arbiter arbiter
(.i_wb_cpu_dbus_adr (wb_dmem_adr),
.i_wb_cpu_dbus_dat (wb_dmem_dat),
.i_wb_cpu_dbus_sel (wb_dmem_sel),
.i_wb_cpu_dbus_we (wb_dmem_we ),
.i_wb_cpu_dbus_cyc (wb_dmem_cyc),
.o_wb_cpu_dbus_rdt (wb_dmem_rdt),
.o_wb_cpu_dbus_ack (wb_dmem_ack),
wire [rf_l2d-1:0] rf_waddr;
wire [rf_width-1:0] rf_wdata;
wire rf_wen;
wire [rf_l2d-1:0] rf_raddr;
wire rf_ren;
wire [rf_width-1:0] rf_rdata;
.i_wb_cpu_ibus_adr (wb_ibus_adr),
.i_wb_cpu_ibus_cyc (wb_ibus_cyc),
.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
.o_wb_cpu_ibus_ack (wb_ibus_ack),
.o_wb_cpu_adr (wb_mem_adr),
.o_wb_cpu_dat (wb_mem_dat),
.o_wb_cpu_sel (wb_mem_sel),
.o_wb_cpu_we (wb_mem_we ),
.o_wb_cpu_cyc (wb_mem_cyc),
.i_wb_cpu_rdt (wb_mem_rdt),
.i_wb_cpu_ack (wb_mem_ack));
servant_mux #(sim) servant_mux
servant_mux servant_mux
(
.i_clk (wb_clk),
.i_rst (wb_rst & (reset_strategy != "NONE")),
.i_wb_cpu_adr (wb_dbus_adr),
.i_wb_cpu_dat (wb_dbus_dat),
.i_wb_cpu_sel (wb_dbus_sel),
.i_wb_cpu_we (wb_dbus_we),
.i_wb_cpu_cyc (wb_dbus_cyc),
.o_wb_cpu_rdt (wb_dbus_rdt),
.o_wb_cpu_ack (wb_dbus_ack),
.o_wb_mem_adr (wb_dmem_adr),
.o_wb_mem_dat (wb_dmem_dat),
.o_wb_mem_sel (wb_dmem_sel),
.o_wb_mem_we (wb_dmem_we),
.o_wb_mem_cyc (wb_dmem_cyc),
.i_wb_mem_rdt (wb_dmem_rdt),
.i_wb_cpu_adr (wb_ext_adr),
.i_wb_cpu_dat (wb_ext_dat),
.i_wb_cpu_sel (wb_ext_sel),
.i_wb_cpu_we (wb_ext_we),
.i_wb_cpu_cyc (wb_ext_stb),
.o_wb_cpu_rdt (wb_ext_rdt),
.o_wb_cpu_ack (wb_ext_ack),
.o_wb_gpio_dat (wb_gpio_dat),
.o_wb_gpio_we (wb_gpio_we),
.o_wb_gpio_cyc (wb_gpio_cyc),
.o_wb_gpio_cyc (wb_gpio_stb),
.i_wb_gpio_rdt (wb_gpio_rdt),
.o_wb_timer_dat (wb_timer_dat),
.o_wb_timer_we (wb_timer_we),
.o_wb_timer_cyc (wb_timer_cyc),
.o_wb_timer_cyc (wb_timer_stb),
.i_wb_timer_rdt (wb_timer_rdt));
servant_ram
@ -121,114 +93,78 @@ module servant
.i_wb_clk (wb_clk),
.i_wb_rst (wb_rst),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
.i_wb_cyc (wb_mem_cyc),
.i_wb_cyc (wb_mem_stb),
.i_wb_we (wb_mem_we) ,
.i_wb_sel (wb_mem_sel),
.i_wb_dat (wb_mem_dat),
.o_wb_rdt (wb_mem_rdt),
.o_wb_ack (wb_mem_ack));
generate
if (|with_csr) begin
servant_timer
#(.RESET_STRATEGY (reset_strategy),
.WIDTH (32))
timer
(.i_clk (wb_clk),
.i_rst (wb_rst),
.o_irq (timer_irq),
.i_wb_cyc (wb_timer_cyc),
.i_wb_we (wb_timer_we) ,
.i_wb_dat (wb_timer_dat),
.o_wb_dat (wb_timer_rdt));
end else begin
assign wb_timer_rdt = 32'd0;
assign timer_irq = 1'b0;
end
endgenerate
servant_timer
#(.RESET_STRATEGY (reset_strategy),
.WIDTH (32))
timer
(.i_clk (wb_clk),
.i_rst (wb_rst),
.o_irq (timer_irq),
.i_wb_cyc (wb_timer_stb),
.i_wb_we (wb_timer_we) ,
.i_wb_dat (wb_timer_dat),
.o_wb_dat (wb_timer_rdt));
servant_gpio gpio
(.i_wb_clk (wb_clk),
.i_wb_dat (wb_gpio_dat),
.i_wb_we (wb_gpio_we),
.i_wb_cyc (wb_gpio_cyc),
.i_wb_cyc (wb_gpio_stb),
.o_wb_rdt (wb_gpio_rdt),
.o_gpio (q));
serv_rf_top
#(.RESET_PC (32'h0000_0000),
.RESET_STRATEGY (reset_strategy),
`ifdef MDU
.MDU(1),
`endif
.WITH_CSR (with_csr),
.COMPRESSED(compress),
.ALIGN(align))
serv_rf_ram
#(.width (rf_width),
.csr_regs (csr_regs))
rf_ram
(.i_clk (wb_clk),
.i_waddr (rf_waddr),
.i_wdata (rf_wdata),
.i_wen (rf_wen),
.i_raddr (rf_raddr),
.i_ren (rf_ren),
.o_rdata (rf_rdata));
servile
#(.rf_width (rf_width),
.sim (sim[0]),
.with_c (compress[0]),
.with_csr (with_csr[0]),
.with_mdu (with_mdu))
cpu
(
.clk (wb_clk),
.i_rst (wb_rst),
.i_clk (wb_clk),
.i_rst (wb_rst),
.i_timer_irq (timer_irq),
`ifdef RISCV_FORMAL
.rvfi_valid (),
.rvfi_order (),
.rvfi_insn (),
.rvfi_trap (),
.rvfi_halt (),
.rvfi_intr (),
.rvfi_mode (),
.rvfi_ixl (),
.rvfi_rs1_addr (),
.rvfi_rs2_addr (),
.rvfi_rs1_rdata (),
.rvfi_rs2_rdata (),
.rvfi_rd_addr (),
.rvfi_rd_wdata (),
.rvfi_pc_rdata (),
.rvfi_pc_wdata (),
.rvfi_mem_addr (),
.rvfi_mem_rmask (),
.rvfi_mem_wmask (),
.rvfi_mem_rdata (),
.rvfi_mem_wdata (),
`endif
.o_ibus_adr (wb_ibus_adr),
.o_ibus_cyc (wb_ibus_cyc),
.i_ibus_rdt (wb_ibus_rdt),
.i_ibus_ack (wb_ibus_ack),
.o_wb_mem_adr (wb_mem_adr),
.o_wb_mem_dat (wb_mem_dat),
.o_wb_mem_sel (wb_mem_sel),
.o_wb_mem_we (wb_mem_we),
.o_wb_mem_stb (wb_mem_stb),
.i_wb_mem_rdt (wb_mem_rdt),
.i_wb_mem_ack (wb_mem_ack),
.o_dbus_adr (wb_dbus_adr),
.o_dbus_dat (wb_dbus_dat),
.o_dbus_sel (wb_dbus_sel),
.o_dbus_we (wb_dbus_we),
.o_dbus_cyc (wb_dbus_cyc),
.i_dbus_rdt (wb_dbus_rdt),
.i_dbus_ack (wb_dbus_ack),
.o_wb_ext_adr (wb_ext_adr),
.o_wb_ext_dat (wb_ext_dat),
.o_wb_ext_sel (wb_ext_sel),
.o_wb_ext_we (wb_ext_we),
.o_wb_ext_stb (wb_ext_stb),
.i_wb_ext_rdt (wb_ext_rdt),
.i_wb_ext_ack (wb_ext_ack),
//Extension
.o_ext_rs1 (mdu_rs1),
.o_ext_rs2 (mdu_rs2),
.o_ext_funct3 (mdu_op),
.i_ext_rd (mdu_rd),
.i_ext_ready (mdu_ready),
//MDU
.o_mdu_valid (mdu_valid));
`ifdef MDU
mdu_top mdu_serv
(
.i_clk(wb_clk),
.i_rst(wb_rst),
.i_mdu_rs1(mdu_rs1),
.i_mdu_rs2(mdu_rs2),
.i_mdu_op(mdu_op),
.i_mdu_valid(mdu_valid),
.o_mdu_ready(mdu_ready),
.o_mdu_rd(mdu_rd));
`else
assign mdu_ready = 1'b0;
assign mdu_rd = 32'b0;
`endif
.o_rf_waddr (rf_waddr),
.o_rf_wdata (rf_wdata),
.o_rf_wen (rf_wen),
.o_rf_raddr (rf_raddr),
.o_rf_ren (rf_ren),
.i_rf_rdata (rf_rdata));
endmodule

39
servant/servant_arbiter.v
View file

@ -1,39 +0,0 @@
/* Arbitrates between dbus and ibus accesses.
* Relies on the fact that not both masters are active at the same time
*/
module servant_arbiter
(
input wire [31:0] i_wb_cpu_dbus_adr,
input wire [31:0] i_wb_cpu_dbus_dat,
input wire [3:0] i_wb_cpu_dbus_sel,
input wire i_wb_cpu_dbus_we,
input wire i_wb_cpu_dbus_cyc,
output wire [31:0] o_wb_cpu_dbus_rdt,
output wire o_wb_cpu_dbus_ack,
input wire [31:0] i_wb_cpu_ibus_adr,
input wire i_wb_cpu_ibus_cyc,
output wire [31:0] o_wb_cpu_ibus_rdt,
output wire o_wb_cpu_ibus_ack,
output wire [31:0] o_wb_cpu_adr,
output wire [31:0] o_wb_cpu_dat,
output wire [3:0] o_wb_cpu_sel,
output wire o_wb_cpu_we,
output wire o_wb_cpu_cyc,
input wire [31:0] i_wb_cpu_rdt,
input wire i_wb_cpu_ack);
assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_wb_cpu_ibus_cyc;
assign o_wb_cpu_ibus_rdt = i_wb_cpu_rdt;
assign o_wb_cpu_ibus_ack = i_wb_cpu_ack & i_wb_cpu_ibus_cyc;
assign o_wb_cpu_adr = i_wb_cpu_ibus_cyc ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
assign o_wb_cpu_dat = i_wb_cpu_dbus_dat;
assign o_wb_cpu_sel = i_wb_cpu_dbus_sel;
assign o_wb_cpu_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_cyc;
assign o_wb_cpu_cyc = i_wb_cpu_ibus_cyc | i_wb_cpu_dbus_cyc;
endmodule

44
servant/servant_mux.v
View file

@ -16,13 +16,6 @@ module servant_mux
output wire [31:0] o_wb_cpu_rdt,
output reg o_wb_cpu_ack,
output wire [31:0] o_wb_mem_adr,
output wire [31:0] o_wb_mem_dat,
output wire [3:0] o_wb_mem_sel,
output wire o_wb_mem_we,
output wire o_wb_mem_cyc,
input wire [31:0] i_wb_mem_rdt,
output wire o_wb_gpio_dat,
output wire o_wb_gpio_we,
output wire o_wb_gpio_cyc,
@ -37,8 +30,8 @@ module servant_mux
wire [1:0] s = i_wb_cpu_adr[31:30];
assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt :
s[0] ? {31'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt : {31'd0,i_wb_gpio_rdt};
always @(posedge i_clk) begin
o_wb_cpu_ack <= 1'b0;
if (i_wb_cpu_cyc & !o_wb_cpu_ack)
@ -47,43 +40,12 @@ module servant_mux
o_wb_cpu_ack <= 1'b0;
end
assign o_wb_mem_adr = i_wb_cpu_adr;
assign o_wb_mem_dat = i_wb_cpu_dat;
assign o_wb_mem_sel = i_wb_cpu_sel;
assign o_wb_mem_we = i_wb_cpu_we;
assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
assign o_wb_gpio_dat = i_wb_cpu_dat[0];
assign o_wb_gpio_we = i_wb_cpu_we;
assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
assign o_wb_gpio_cyc = i_wb_cpu_cyc & !s[1];
assign o_wb_timer_dat = i_wb_cpu_dat;
assign o_wb_timer_we = i_wb_cpu_we;
assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
generate
if (sim) begin
wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
reg [1023:0] signature_file;
integer f = 0;
initial
/* verilator lint_off WIDTH */
if ($value$plusargs("signature=%s", signature_file)) begin
$display("Writing signature to %0s", signature_file);
f = $fopen(signature_file, "w");
end
/* verilator lint_on WIDTH */
always @(posedge i_clk)
if (sig_en & (f != 0))
$fwrite(f, "%c", i_wb_cpu_dat[7:0]);
else if(halt_en) begin
$display("Test complete");
$finish;
end
end
endgenerate
endmodule