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Simplify optional MDU logic

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Olof Kindgren 2021-10-03 23:28:45 +02:00
parent 8843005407
commit 99f82af6eb
3 changed files with 16 additions and 55 deletions
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6
rtl/serv_bufreg.v
View file

@ -46,10 +46,6 @@ module serv_bufreg #(
assign o_q = lsb[0] & i_en;
assign o_dbus_adr = {data, 2'b00};
assign o_ext_rs1 = {o_dbus_adr[31:2],lsb};
generate
if (MDU) assign o_lsb = i_mdu_op ? 2'b00 : lsb;
else assign o_lsb = lsb;
endgenerate
assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
endmodule

33
rtl/serv_decode.v
View file

@ -1,5 +1,5 @@
`default_nettype none
module serv_decode
module serv_decode
#(parameter [0:0] PRE_REGISTER = 1,
parameter [0:0] MDU = 0)
(
@ -69,35 +69,16 @@ module serv_decode
reg imm25;
reg imm30;
generate
wire co_mdu_op;
wire [2:0]co_ext_funct3;
wire co_shift_op;
wire co_slt_op;
wire co_mem_word;
wire co_rd_alu_en;
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mdu_op = MDU & (opcode == 5'b01100) & imm25;
wire co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
if (MDU) begin
assign co_mdu_op = ((opcode == 5'b01100) & imm25);
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
assign co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
assign co_mem_word = co_mdu_op ? co_mdu_op :funct3[1];
assign co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
end else begin
assign co_mdu_op = 1'b0;
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01);
assign co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01);
assign co_mem_word = funct3[1];
assign co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
end
assign co_ext_funct3 = funct3;
endgenerate
wire co_mem_word = co_mdu_op | funct3[1];
wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
wire [2:0] co_ext_funct3 = funct3;
//jal,branch = imm
//jalr = rs1+imm

32
rtl/serv_state.v
View file

@ -85,34 +85,18 @@ module serv_state
//been calculated.
wire take_branch = i_branch_op & (!i_cond_branch | (i_alu_cmp^i_bne_or_bge));
generate
if (MDU) begin
//slt*, branch/jump, shift, load/store
assign two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op | i_mdu_op;
//slt*, branch/jump, shift, load/store, (optionally mdu ops)
assign two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op | (MDU & i_mdu_op);
//valid signal for mdu
assign o_mdu_valid = !o_cnt_en & init_done & i_mdu_op;
//valid signal for mdu
assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op;
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync &
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync &
((i_shift_op & (i_sh_done | !i_sh_right) & !o_cnt_en & init_done) |
(i_mem_op & i_dbus_ack) | i_mdu_ready |
(i_mem_op & i_dbus_ack) | (MDU & i_mdu_ready) |
(stage_two_req & (i_slt_op | i_branch_op)));
end else begin
//slt*, branch/jump, shift, load/store
assign two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op;
//valid signal for mdu turned-off
assign o_mdu_valid = 1'b0;
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync &
((i_shift_op & (i_sh_done | !i_sh_right) & !o_cnt_en & init_done) |
(i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op)));
end
endgenerate
assign o_dbus_cyc = !o_cnt_en & init_done & i_mem_op & !i_mem_misalign;